DWC_pcie_dbi_cpcie_usp_4x8.csr/project/jenkins/workspace/Esperanto_DV/soc_hal/esperanto-soc/dv/common/scripts/semifore_css/etsoc_esr.cssPE0_DWC_pcie_ctlcomponentPE0_DWC_pcie_ctlPE0_DWC_pcie_ctlDWC_pcie_dbi_cpcie_usp_4x8.csr114187NAPE0_DWC_pcie_ctladdressmapPE0_DWC_pcie_ctl.AXI_SlaveaddressmapPE0_DWC_pcie_ctl.DBI_SlaveaddressmapPE0_DWC_pcie_ctl.AXI_SlaveAXI_SlaveDWC_pcie_dbi_cpcie_usp_4x8.csr114185R/WPE0_DWC_pcie_ctl_AXI_SlaveDWC PCIE-EP Memory MapgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDRgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_PM_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_LTR_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_LNR_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_DLINK_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_RESBAR_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_VF_RESBAR_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGICgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR_DBI2memoryPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP_DBI2groupPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP_DBI2groupPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP_DBI2groupPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP0x00x381123AXI_SlavePE0_DWC_pcie_ctl.AXI_Slave0x00x3FAXI_Slave.PF0_TYPE0_HDRPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR0x00x0AXI_Slave.PF0_TYPE0_HDR.DEVICE_ID_VENDOR_ID_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.DEVICE_ID_VENDOR_ID_REG0x40x4AXI_Slave.PF0_TYPE0_HDR.STATUS_COMMAND_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.STATUS_COMMAND_REG0x80x8AXI_Slave.PF0_TYPE0_HDR.CLASS_CODE_REVISION_IDPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.CLASS_CODE_REVISION_ID0xC0xCAXI_Slave.PF0_TYPE0_HDR.BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG0x100x10AXI_Slave.PF0_TYPE0_HDR.BAR0_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.BAR0_REG0x140x14AXI_Slave.PF0_TYPE0_HDR.BAR1_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.BAR1_REG0x180x18AXI_Slave.PF0_TYPE0_HDR.BAR2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.BAR2_REG0x1C0x1CAXI_Slave.PF0_TYPE0_HDR.BAR3_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.BAR3_REG0x200x20AXI_Slave.PF0_TYPE0_HDR.BAR4_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.BAR4_REG0x240x24AXI_Slave.PF0_TYPE0_HDR.BAR5_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.BAR5_REG0x280x28AXI_Slave.PF0_TYPE0_HDR.CARDBUS_CIS_PTR_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.CARDBUS_CIS_PTR_REG0x2C0x2CAXI_Slave.PF0_TYPE0_HDR.SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG0x300x30AXI_Slave.PF0_TYPE0_HDR.EXP_ROM_BASE_ADDR_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.EXP_ROM_BASE_ADDR_REG0x340x34AXI_Slave.PF0_TYPE0_HDR.PCI_CAP_PTR_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.PCI_CAP_PTR_REG0x380x3B0x3C0x3CAXI_Slave.PF0_TYPE0_HDR.MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG0x400x47AXI_Slave.PF0_PM_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_PM_CAP0x400x40AXI_Slave.PF0_PM_CAP.CAP_ID_NXT_PTR_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PM_CAP.CAP_ID_NXT_PTR_REG0x440x44AXI_Slave.PF0_PM_CAP.CON_STATUS_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PM_CAP.CON_STATUS_REG0x480x4F0x500x67AXI_Slave.PF0_MSI_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP0x500x50AXI_Slave.PF0_MSI_CAP.PCI_MSI_CAP_ID_NEXT_CTRL_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.PCI_MSI_CAP_ID_NEXT_CTRL_REG0x540x54AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_04H_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_04H_REG0x580x58AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_08H_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_08H_REG0x5C0x5CAXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_0CH_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_0CH_REG0x600x60AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_10H_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_10H_REG0x640x64AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_14H_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_14H_REG0x680x6F0x700xABAXI_Slave.PF0_PCIE_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP0x700x70AXI_Slave.PF0_PCIE_CAP.PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG0x740x74AXI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES_REG0x780x78AXI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL_DEVICE_STATUSPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL_DEVICE_STATUS0x7C0x7CAXI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES_REG0x800x80AXI_Slave.PF0_PCIE_CAP.LINK_CONTROL_LINK_STATUS_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.LINK_CONTROL_LINK_STATUS_REG0x840x930x940x94AXI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES2_REG0x980x98AXI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL2_DEVICE_STATUS2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL2_DEVICE_STATUS2_REG0x9C0x9CAXI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES2_REG0xA00xA0AXI_Slave.PF0_PCIE_CAP.LINK_CONTROL2_LINK_STATUS2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.LINK_CONTROL2_LINK_STATUS2_REG0xA40xAB0xAC0xAF0xB00xBCAXI_Slave.PF0_MSIX_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP0xB00xB0AXI_Slave.PF0_MSIX_CAP.PCI_MSIX_CAP_ID_NEXT_CTRL_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP.PCI_MSIX_CAP_ID_NEXT_CTRL_REG0xB40xB4AXI_Slave.PF0_MSIX_CAP.MSIX_TABLE_OFFSET_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP.MSIX_TABLE_OFFSET_REG0xB80xB8AXI_Slave.PF0_MSIX_CAP.MSIX_PBA_OFFSET_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP.MSIX_PBA_OFFSET_REG0xBC0xBC0xBD0xFF0x1000x147AXI_Slave.PF0_AER_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP0x1000x100AXI_Slave.PF0_AER_CAP.AER_EXT_CAP_HDR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.AER_EXT_CAP_HDR_OFF0x1040x104AXI_Slave.PF0_AER_CAP.UNCORR_ERR_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.UNCORR_ERR_STATUS_OFF0x1080x108AXI_Slave.PF0_AER_CAP.UNCORR_ERR_MASK_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.UNCORR_ERR_MASK_OFF0x10C0x10CAXI_Slave.PF0_AER_CAP.UNCORR_ERR_SEV_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.UNCORR_ERR_SEV_OFF0x1100x110AXI_Slave.PF0_AER_CAP.CORR_ERR_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.CORR_ERR_STATUS_OFF0x1140x114AXI_Slave.PF0_AER_CAP.CORR_ERR_MASK_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.CORR_ERR_MASK_OFF0x1180x118AXI_Slave.PF0_AER_CAP.ADV_ERR_CAP_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.ADV_ERR_CAP_CTRL_OFF0x11C0x11CAXI_Slave.PF0_AER_CAP.HDR_LOG_0_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.HDR_LOG_0_OFF0x1200x120AXI_Slave.PF0_AER_CAP.HDR_LOG_1_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.HDR_LOG_1_OFF0x1240x124AXI_Slave.PF0_AER_CAP.HDR_LOG_2_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.HDR_LOG_2_OFF0x1280x128AXI_Slave.PF0_AER_CAP.HDR_LOG_3_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.HDR_LOG_3_OFF0x12C0x1370x1380x138AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_1_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_1_OFF0x13C0x13CAXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_2_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_2_OFF0x1400x140AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_3_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_3_OFF0x1440x144AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_4_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_4_OFF0x1480x197AXI_Slave.PF0_VC_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP0x1480x148AXI_Slave.PF0_VC_CAP.VC_BASEPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.VC_BASE0x14C0x14CAXI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_10x1500x150AXI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_20x1540x154AXI_Slave.PF0_VC_CAP.VC_STATUS_CONTROL_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.VC_STATUS_CONTROL_REG0x1580x158AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC0PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC00x15C0x15CAXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC0PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC00x1600x160AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC0PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC00x1640x164AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC1PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC10x1680x168AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC1PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC10x16C0x16CAXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC1PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC10x1700x170AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC2PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC20x1740x174AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC2PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC20x1780x178AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC2PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC20x17C0x17CAXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC3PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC30x1800x180AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC3PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC30x1840x184AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC3PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC30x1880x1970x1980x1B7AXI_Slave.PF0_SPCIE_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP0x1980x198AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_HEADER_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_HEADER_REG0x19C0x19CAXI_Slave.PF0_SPCIE_CAP.LINK_CONTROL3_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.LINK_CONTROL3_REG0x1A00x1A0AXI_Slave.PF0_SPCIE_CAP.LANE_ERR_STATUS_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.LANE_ERR_STATUS_REG0x1A40x1A4AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_0CH_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_0CH_REG0x1A80x1A8AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_10H_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_10H_REG0x1AC0x1ACAXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_14H_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_14H_REG0x1B00x1B0AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_18H_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_18H_REG0x1B40x1B70x1B80x1DFAXI_Slave.PF0_PL16G_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP0x1B80x1B8AXI_Slave.PF0_PL16G_CAP.PL16G_EXT_CAP_HDR_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_EXT_CAP_HDR_REG0x1BC0x1BCAXI_Slave.PF0_PL16G_CAP.PL16G_CAPABILITY_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_CAPABILITY_REG0x1C00x1C0AXI_Slave.PF0_PL16G_CAP.PL16G_CONTROL_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_CONTROL_REG0x1C40x1C4AXI_Slave.PF0_PL16G_CAP.PL16G_STATUS_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_STATUS_REG0x1C80x1C8AXI_Slave.PF0_PL16G_CAP.PL16G_LC_DPAR_STATUS_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_LC_DPAR_STATUS_REG0x1CC0x1CCAXI_Slave.PF0_PL16G_CAP.PL16G_FIRST_RETIMER_DPAR_STATUS_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_FIRST_RETIMER_DPAR_STATUS_REG0x1D00x1D0AXI_Slave.PF0_PL16G_CAP.PL16G_SECOND_RETIMER_DPAR_STATUS_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_SECOND_RETIMER_DPAR_STATUS_REG0x1D40x1D70x1D80x1D8AXI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_20H_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_20H_REG0x1DC0x1DCAXI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_24H_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_24H_REG0x1E00x207AXI_Slave.PF0_MARGIN_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP0x1E00x1E0AXI_Slave.PF0_MARGIN_CAP.MARGIN_EXT_CAP_HDR_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_EXT_CAP_HDR_REG0x1E40x1E4AXI_Slave.PF0_MARGIN_CAP.MARGIN_PORT_CAPABILITIES_STATUS_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_PORT_CAPABILITIES_STATUS_REG0x1E80x1E8AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS0_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS0_REG0x1EC0x1ECAXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS1_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS1_REG0x1F00x1F0AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS2_REG0x1F40x1F4AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS3_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS3_REG0x1F80x1F8AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS4_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS4_REG0x1FC0x1FCAXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS5_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS5_REG0x2000x200AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS6_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS6_REG0x2040x204AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS7_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS7_REG0x2080x293AXI_Slave.PF0_TPH_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP0x2080x208AXI_Slave.PF0_TPH_CAP.TPH_EXT_CAP_HDR_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP.TPH_EXT_CAP_HDR_REG0x20C0x20CAXI_Slave.PF0_TPH_CAP.TPH_REQ_CAP_REG_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP.TPH_REQ_CAP_REG_REG0x2100x210AXI_Slave.PF0_TPH_CAP.TPH_REQ_CONTROL_REG_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP.TPH_REQ_CONTROL_REG_REG0x2140x214AXI_Slave.PF0_TPH_CAP.TPH_ST_TABLE_REG_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP.TPH_ST_TABLE_REG_00x2180x2930x2940x29BAXI_Slave.PF0_LTR_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_LTR_CAP0x2940x294AXI_Slave.PF0_LTR_CAP.LTR_CAP_HDR_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_LTR_CAP.LTR_CAP_HDR_REG0x2980x298AXI_Slave.PF0_LTR_CAP.LTR_LATENCY_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_LTR_CAP.LTR_LATENCY_REG0x29C0x2ABAXI_Slave.PF0_L1SUB_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAP0x29C0x29CAXI_Slave.PF0_L1SUB_CAP.L1SUB_CAP_HEADER_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAP.L1SUB_CAP_HEADER_REG0x2A00x2A0AXI_Slave.PF0_L1SUB_CAP.L1SUB_CAPABILITY_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAP.L1SUB_CAPABILITY_REG0x2A40x2A4AXI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL1_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL1_REG0x2A80x2A8AXI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL2_REG0x2AC0x2BB0x2BC0x2C3AXI_Slave.PF0_LNR_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_LNR_CAP0x2BC0x2BCAXI_Slave.PF0_LNR_CAP.LNR_EXT_CAP_HDR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_LNR_CAP.LNR_EXT_CAP_HDR_OFF0x2C00x2C0AXI_Slave.PF0_LNR_CAP.LNR_CAP_CONTROL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_LNR_CAP.LNR_CAP_CONTROL_OFF0x2C40x3C3AXI_Slave.PF0_RAS_DES_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP0x2C40x2C4AXI_Slave.PF0_RAS_DES_CAP.RAS_DES_CAP_HEADER_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.RAS_DES_CAP_HEADER_REG0x2C80x2C8AXI_Slave.PF0_RAS_DES_CAP.VENDOR_SPECIFIC_HEADER_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.VENDOR_SPECIFIC_HEADER_REG0x2CC0x2CCAXI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_CONTROL_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_CONTROL_REG0x2D00x2D0AXI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_DATA_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_DATA_REG0x2D40x2D4AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_CONTROL_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_CONTROL_REG0x2D80x2D8AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_REG0x2DC0x2DCAXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_63_32_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_63_32_REG0x2E00x2F30x2F40x2F4AXI_Slave.PF0_RAS_DES_CAP.EINJ_ENABLE_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ_ENABLE_REG0x2F80x2F8AXI_Slave.PF0_RAS_DES_CAP.EINJ0_CRC_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ0_CRC_REG0x2FC0x2FCAXI_Slave.PF0_RAS_DES_CAP.EINJ1_SEQNUM_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ1_SEQNUM_REG0x3000x300AXI_Slave.PF0_RAS_DES_CAP.EINJ2_DLLP_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ2_DLLP_REG0x3040x304AXI_Slave.PF0_RAS_DES_CAP.EINJ3_SYMBOL_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ3_SYMBOL_REG0x3080x308AXI_Slave.PF0_RAS_DES_CAP.EINJ4_FC_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ4_FC_REG0x30C0x30CAXI_Slave.PF0_RAS_DES_CAP.EINJ5_SP_TLP_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ5_SP_TLP_REG0x3100x310AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H0_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H0_REG0x3140x314AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H1_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H1_REG0x3180x318AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H2_REG0x31C0x31CAXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H3_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H3_REG0x3200x320AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H0_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H0_REG0x3240x324AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H1_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H1_REG0x3280x328AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H2_REG0x32C0x32CAXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H3_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H3_REG0x3300x330AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H0_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H0_REG0x3340x334AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H1_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H1_REG0x3380x338AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H2_REG0x33C0x33CAXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H3_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H3_REG0x3400x340AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H0_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H0_REG0x3440x344AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H1_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H1_REG0x3480x348AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H2_REG0x34C0x34CAXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H3_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H3_REG0x3500x350AXI_Slave.PF0_RAS_DES_CAP.EINJ6_TLP_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_TLP_REG0x3540x3630x3640x364AXI_Slave.PF0_RAS_DES_CAP.SD_CONTROL1_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_CONTROL1_REG0x3680x368AXI_Slave.PF0_RAS_DES_CAP.SD_CONTROL2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_CONTROL2_REG0x36C0x3730x3740x374AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LANE_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LANE_REG0x3780x378AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LTSSM_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LTSSM_REG0x37C0x37CAXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_PM_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_PM_REG0x3800x380AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L2_REG0x3840x384AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3FC_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3FC_REG0x3880x388AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3_REG0x38C0x3930x3940x394AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL1_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL1_REG0x3980x398AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL2_REG0x39C0x39CAXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL3_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL3_REG0x3A00x3A30x3A40x3A4AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS1_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS1_REG0x3A80x3A8AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS2_REG0x3AC0x3ACAXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS3_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS3_REG0x3B00x3C30x3C40x3FBAXI_Slave.PF0_VSECRAS_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP0x3C40x3C4AXI_Slave.PF0_VSECRAS_CAP.RASDP_EXT_CAP_HDR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_EXT_CAP_HDR_OFF0x3C80x3C8AXI_Slave.PF0_VSECRAS_CAP.RASDP_VENDOR_SPECIFIC_HDR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_VENDOR_SPECIFIC_HDR_OFF0x3CC0x3CCAXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_PROT_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_PROT_CTRL_OFF0x3D00x3D0AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNTER_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNTER_CTRL_OFF0x3D40x3D4AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNT_REPORT_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNT_REPORT_OFF0x3D80x3D8AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNTER_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNTER_CTRL_OFF0x3DC0x3DCAXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNT_REPORT_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNT_REPORT_OFF0x3E00x3E0AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_INJ_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_INJ_CTRL_OFF0x3E40x3E4AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_ERROR_LOCATION_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_ERROR_LOCATION_OFF0x3E80x3E8AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_ERROR_LOCATION_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_ERROR_LOCATION_OFF0x3EC0x3ECAXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_EN_OFF0x3F00x3F0AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_CLEAR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_CLEAR_OFF0x3F40x3F4AXI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_CORR_ERROR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_CORR_ERROR_OFF0x3F80x3F8AXI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_UNCORR_ERROR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_UNCORR_ERROR_OFF0x3FC0x407AXI_Slave.PF0_DLINK_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_DLINK_CAP0x3FC0x3FCAXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_EXT_HDR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_EXT_HDR_OFF0x4000x400AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_CAP_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_CAP_OFF0x4040x404AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_STATUS_OFF0x4080x43BAXI_Slave.PF0_RESBAR_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_RESBAR_CAP0x4080x408AXI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_HDR_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_HDR_REG0x40C0x40CAXI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_REG_0_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_REG_0_REG0x4100x410AXI_Slave.PF0_RESBAR_CAP.RESBAR_CTRL_REG_0_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RESBAR_CAP.RESBAR_CTRL_REG_0_REG0x4140x43B0x43C0x4470x4480x47BAXI_Slave.PF0_VF_RESBAR_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_VF_RESBAR_CAP0x4480x448AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_HDR_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_HDR_REG0x44C0x44CAXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_0_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_0_REG0x4500x450AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_0_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_0_REG0x4540x454AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_1_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_1_REG0x4580x458AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_1_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_1_REG0x45C0x45CAXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_2_REG0x4600x460AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_2_REG0x4640x47B0x47C0x6FF0x7000xCFFAXI_Slave.PF0_PORT_LOGICPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC0x7000x700AXI_Slave.PF0_PORT_LOGIC.ACK_LATENCY_TIMER_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.ACK_LATENCY_TIMER_OFF0x7040x704AXI_Slave.PF0_PORT_LOGIC.VENDOR_SPEC_DLLP_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VENDOR_SPEC_DLLP_OFF0x7080x708AXI_Slave.PF0_PORT_LOGIC.PORT_FORCE_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PORT_FORCE_OFF0x70C0x70CAXI_Slave.PF0_PORT_LOGIC.ACK_F_ASPM_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.ACK_F_ASPM_CTRL_OFF0x7100x710AXI_Slave.PF0_PORT_LOGIC.PORT_LINK_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PORT_LINK_CTRL_OFF0x7140x714AXI_Slave.PF0_PORT_LOGIC.LANE_SKEW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.LANE_SKEW_OFF0x7180x718AXI_Slave.PF0_PORT_LOGIC.TIMER_CTRL_MAX_FUNC_NUM_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TIMER_CTRL_MAX_FUNC_NUM_OFF0x71C0x71CAXI_Slave.PF0_PORT_LOGIC.SYMBOL_TIMER_FILTER_1_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.SYMBOL_TIMER_FILTER_1_OFF0x7200x720AXI_Slave.PF0_PORT_LOGIC.FILTER_MASK_2_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.FILTER_MASK_2_OFF0x7240x724AXI_Slave.PF0_PORT_LOGIC.AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF0x7280x728AXI_Slave.PF0_PORT_LOGIC.PL_DEBUG0_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PL_DEBUG0_OFF0x72C0x72CAXI_Slave.PF0_PORT_LOGIC.PL_DEBUG1_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PL_DEBUG1_OFF0x7300x730AXI_Slave.PF0_PORT_LOGIC.TX_P_FC_CREDIT_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TX_P_FC_CREDIT_STATUS_OFF0x7340x734AXI_Slave.PF0_PORT_LOGIC.TX_NP_FC_CREDIT_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TX_NP_FC_CREDIT_STATUS_OFF0x7380x738AXI_Slave.PF0_PORT_LOGIC.TX_CPL_FC_CREDIT_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TX_CPL_FC_CREDIT_STATUS_OFF0x73C0x73CAXI_Slave.PF0_PORT_LOGIC.QUEUE_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.QUEUE_STATUS_OFF0x7400x740AXI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_1_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_1_OFF0x7440x744AXI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_2_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_2_OFF0x7480x748AXI_Slave.PF0_PORT_LOGIC.VC0_P_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC0_P_RX_Q_CTRL_OFF0x74C0x74CAXI_Slave.PF0_PORT_LOGIC.VC0_NP_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC0_NP_RX_Q_CTRL_OFF0x7500x750AXI_Slave.PF0_PORT_LOGIC.VC0_CPL_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC0_CPL_RX_Q_CTRL_OFF0x7540x754AXI_Slave.PF0_PORT_LOGIC.VC1_P_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC1_P_RX_Q_CTRL_OFF0x7580x758AXI_Slave.PF0_PORT_LOGIC.VC1_NP_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC1_NP_RX_Q_CTRL_OFF0x75C0x75CAXI_Slave.PF0_PORT_LOGIC.VC1_CPL_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC1_CPL_RX_Q_CTRL_OFF0x7600x760AXI_Slave.PF0_PORT_LOGIC.VC2_P_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC2_P_RX_Q_CTRL_OFF0x7640x764AXI_Slave.PF0_PORT_LOGIC.VC2_NP_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC2_NP_RX_Q_CTRL_OFF0x7680x768AXI_Slave.PF0_PORT_LOGIC.VC2_CPL_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC2_CPL_RX_Q_CTRL_OFF0x76C0x76CAXI_Slave.PF0_PORT_LOGIC.VC3_P_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC3_P_RX_Q_CTRL_OFF0x7700x770AXI_Slave.PF0_PORT_LOGIC.VC3_NP_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC3_NP_RX_Q_CTRL_OFF0x7740x774AXI_Slave.PF0_PORT_LOGIC.VC3_CPL_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC3_CPL_RX_Q_CTRL_OFF0x7780x80B0x80C0x80CAXI_Slave.PF0_PORT_LOGIC.GEN2_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN2_CTRL_OFF0x8100x810AXI_Slave.PF0_PORT_LOGIC.PHY_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PHY_STATUS_OFF0x8140x814AXI_Slave.PF0_PORT_LOGIC.PHY_CONTROL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PHY_CONTROL_OFF0x8180x81B0x81C0x81CAXI_Slave.PF0_PORT_LOGIC.TRGT_MAP_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TRGT_MAP_CTRL_OFF0x8200x820AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_ADDR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_ADDR_OFF0x8240x824AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_UPPER_ADDR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_UPPER_ADDR_OFF0x8280x828AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_EN_OFF0x82C0x82CAXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_MASK_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_MASK_OFF0x8300x830AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_STATUS_OFF0x8340x834AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_EN_OFF0x8380x838AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_MASK_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_MASK_OFF0x83C0x83CAXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_STATUS_OFF0x8400x840AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_EN_OFF0x8440x844AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_MASK_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_MASK_OFF0x8480x848AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_STATUS_OFF0x84C0x84CAXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_EN_OFF0x8500x850AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_MASK_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_MASK_OFF0x8540x854AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_STATUS_OFF0x8580x858AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_EN_OFF0x85C0x85CAXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_MASK_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_MASK_OFF0x8600x860AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_STATUS_OFF0x8640x864AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_EN_OFF0x8680x868AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_MASK_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_MASK_OFF0x86C0x86CAXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_STATUS_OFF0x8700x870AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_EN_OFF0x8740x874AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_MASK_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_MASK_OFF0x8780x878AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_STATUS_OFF0x87C0x87CAXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_EN_OFF0x8800x880AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_MASK_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_MASK_OFF0x8840x884AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_STATUS_OFF0x8880x888AXI_Slave.PF0_PORT_LOGIC.MSI_GPIO_IO_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_GPIO_IO_OFF0x88C0x88CAXI_Slave.PF0_PORT_LOGIC.CLOCK_GATING_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.CLOCK_GATING_CTRL_OFF0x8900x890AXI_Slave.PF0_PORT_LOGIC.GEN3_RELATED_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN3_RELATED_OFF0x8940x8A70x8A80x8A8AXI_Slave.PF0_PORT_LOGIC.GEN3_EQ_CONTROL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN3_EQ_CONTROL_OFF0x8AC0x8ACAXI_Slave.PF0_PORT_LOGIC.GEN3_EQ_FB_MODE_DIR_CHANGE_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN3_EQ_FB_MODE_DIR_CHANGE_OFF0x8B00x8B30x8B40x8B4AXI_Slave.PF0_PORT_LOGIC.ORDER_RULE_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.ORDER_RULE_CTRL_OFF0x8B80x8B8AXI_Slave.PF0_PORT_LOGIC.PIPE_LOOPBACK_CONTROL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PIPE_LOOPBACK_CONTROL_OFF0x8BC0x8BCAXI_Slave.PF0_PORT_LOGIC.MISC_CONTROL_1_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MISC_CONTROL_1_OFF0x8C00x8C0AXI_Slave.PF0_PORT_LOGIC.MULTI_LANE_CONTROL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MULTI_LANE_CONTROL_OFF0x8C40x8C4AXI_Slave.PF0_PORT_LOGIC.PHY_INTEROP_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PHY_INTEROP_CTRL_OFF0x8C80x8C8AXI_Slave.PF0_PORT_LOGIC.TRGT_CPL_LUT_DELETE_ENTRY_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TRGT_CPL_LUT_DELETE_ENTRY_OFF0x8CC0x8CCAXI_Slave.PF0_PORT_LOGIC.LINK_FLUSH_CONTROL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.LINK_FLUSH_CONTROL_OFF0x8D00x8D0AXI_Slave.PF0_PORT_LOGIC.AMBA_ERROR_RESPONSE_DEFAULT_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AMBA_ERROR_RESPONSE_DEFAULT_OFF0x8D40x8D4AXI_Slave.PF0_PORT_LOGIC.AMBA_LINK_TIMEOUT_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AMBA_LINK_TIMEOUT_OFF0x8D80x8D8AXI_Slave.PF0_PORT_LOGIC.AMBA_ORDERING_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AMBA_ORDERING_CTRL_OFF0x8DC0x8DF0x8E00x8E0AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_1_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_1_OFF0x8E40x8E4AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_2_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_2_OFF0x8E80x8E8AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_3_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_3_OFF0x8EC0x8EF0x8F00x8F0AXI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_LOW_OFF0x8F40x8F4AXI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_HIGH_OFF0x8F80x8F8AXI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_NUMBER_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_NUMBER_OFF0x8FC0x8FCAXI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_TYPE_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_TYPE_OFF0x9000x93F0x9400x940AXI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_LOW_OFF0x9440x944AXI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_HIGH_OFF0x9480x948AXI_Slave.PF0_PORT_LOGIC.MSIX_DOORBELL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSIX_DOORBELL_OFF0x94C0x94CAXI_Slave.PF0_PORT_LOGIC.MSIX_RAM_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSIX_RAM_CTRL_OFF0x9500xB2F0xB300xB30AXI_Slave.PF0_PORT_LOGIC.PL_LTR_LATENCY_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PL_LTR_LATENCY_OFF0xB340xB3F0xB400xB40AXI_Slave.PF0_PORT_LOGIC.AUX_CLK_FREQ_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AUX_CLK_FREQ_OFF0xB440xB44AXI_Slave.PF0_PORT_LOGIC.L1_SUBSTATES_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.L1_SUBSTATES_OFF0xB480xB48AXI_Slave.PF0_PORT_LOGIC.POWERDOWN_CTRL_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.POWERDOWN_CTRL_STATUS_OFF0xB4C0xB7F0xB800xB80AXI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_1_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_1_OFF0xB840xB84AXI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_2_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_2_OFF0xB880xB8F0xB900xB90AXI_Slave.PF0_PORT_LOGIC.PIPE_RELATED_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PIPE_RELATED_OFF0xB940xCFF0xD000xFFFFF0x1000000x10003FAXI_Slave.PF0_TYPE0_HDR_DBI2PE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR_DBI20x1000000x10000F0x1000100x100010AXI_Slave.PF0_TYPE0_HDR_DBI2.BAR0_MASK_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR_DBI2.BAR0_MASK_REG0x1000140x100014AXI_Slave.PF0_TYPE0_HDR_DBI2.BAR1_MASK_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR_DBI2.BAR1_MASK_REG0x1000180x100018AXI_Slave.PF0_TYPE0_HDR_DBI2.BAR2_MASK_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR_DBI2.BAR2_MASK_REG0x10001C0x10001CAXI_Slave.PF0_TYPE0_HDR_DBI2.BAR3_MASK_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR_DBI2.BAR3_MASK_REG0x1000200x100020AXI_Slave.PF0_TYPE0_HDR_DBI2.BAR4_MASK_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR_DBI2.BAR4_MASK_REG0x1000240x100024AXI_Slave.PF0_TYPE0_HDR_DBI2.BAR5_MASK_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR_DBI2.BAR5_MASK_REG0x1000280x10002F0x1000300x100030AXI_Slave.PF0_TYPE0_HDR_DBI2.EXP_ROM_BAR_MASK_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR_DBI2.EXP_ROM_BAR_MASK_REG0x1000340x10003F0x1000400x10006F0x1000700x1000ABAXI_Slave.PF0_PCIE_CAP_DBI2PE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP_DBI20x1000AC0x1000AF0x1000B00x1000BCAXI_Slave.PF0_MSIX_CAP_DBI2PE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP_DBI20x1000B00x1000B0AXI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG0x1000B40x1000B4AXI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_TABLE_OFFSET_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_TABLE_OFFSET_REG0x1000B80x1000B8AXI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_PBA_OFFSET_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_PBA_OFFSET_REG0x1000BC0x1000BC0x1000BD0x1002070x1002080x100293AXI_Slave.PF0_TPH_CAP_DBI2PE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP_DBI20x1002080x10020B0x10020C0x10020CAXI_Slave.PF0_TPH_CAP_DBI2.SHADOW_TPH_REQ_CAP_REG_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP_DBI2.SHADOW_TPH_REQ_CAP_REG_REG0x1002100x1002930x1002940x2FFFFF0x3000000x31FF23AXI_Slave.PF0_ATU_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP0x3000000x300000AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_00x3000040x300004AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_00x3000080x300008AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_00x30000C0x30000CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_00x3000100x300010AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_00x3000140x300014AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_00x3000180x300018AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_00x30001C0x30001F0x3000200x300020AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_00x3000240x3000FF0x3001000x300100AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_00x3001040x300104AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_00x3001080x300108AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_00x30010C0x30010CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_00x3001100x300110AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_00x3001140x300114AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_00x3001180x300118AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_00x30011C0x30011F0x3001200x300120AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_00x3001240x3001FF0x3002000x300200AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_10x3002040x300204AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_10x3002080x300208AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10x30020C0x30020CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10x3002100x300210AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_10x3002140x300214AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10x3002180x300218AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10x30021C0x30021F0x3002200x300220AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10x3002240x3002FF0x3003000x300300AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_10x3003040x300304AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_10x3003080x300308AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_10x30030C0x30030CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_10x3003100x300310AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_10x3003140x300314AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_10x3003180x300318AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10x30031C0x30031F0x3003200x300320AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10x3003240x3003FF0x3004000x300400AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_20x3004040x300404AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_20x3004080x300408AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_20x30040C0x30040CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_20x3004100x300410AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_20x3004140x300414AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_20x3004180x300418AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_20x30041C0x30041F0x3004200x300420AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_20x3004240x3004FF0x3005000x300500AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_20x3005040x300504AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_20x3005080x300508AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_20x30050C0x30050CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_20x3005100x300510AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_20x3005140x300514AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_20x3005180x300518AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20x30051C0x30051F0x3005200x300520AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20x3005240x3005FF0x3006000x300600AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_30x3006040x300604AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_30x3006080x300608AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_30x30060C0x30060CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_30x3006100x300610AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_30x3006140x300614AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_30x3006180x300618AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_30x30061C0x30061F0x3006200x300620AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_30x3006240x3006FF0x3007000x300700AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_30x3007040x300704AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_30x3007080x300708AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_30x30070C0x30070CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_30x3007100x300710AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_30x3007140x300714AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_30x3007180x300718AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30x30071C0x30071F0x3007200x300720AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30x3007240x3007FF0x3008000x300800AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_40x3008040x300804AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_40x3008080x300808AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_40x30080C0x30080CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_40x3008100x300810AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_40x3008140x300814AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_40x3008180x300818AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_40x30081C0x30081F0x3008200x300820AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_40x3008240x3008FF0x3009000x300900AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_40x3009040x300904AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_40x3009080x300908AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_40x30090C0x30090CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_40x3009100x300910AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_40x3009140x300914AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_40x3009180x300918AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_40x30091C0x30091F0x3009200x300920AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_40x3009240x3009FF0x300A000x300A00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_50x300A040x300A04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_50x300A080x300A08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_50x300A0C0x300A0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_50x300A100x300A10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_50x300A140x300A14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_50x300A180x300A18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_50x300A1C0x300A1F0x300A200x300A20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_50x300A240x300AFF0x300B000x300B00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_50x300B040x300B04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_50x300B080x300B08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_50x300B0C0x300B0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_50x300B100x300B10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_50x300B140x300B14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_50x300B180x300B18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_50x300B1C0x300B1F0x300B200x300B20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_50x300B240x300BFF0x300C000x300C00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_60x300C040x300C04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_60x300C080x300C08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_60x300C0C0x300C0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_60x300C100x300C10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_60x300C140x300C14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_60x300C180x300C18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_60x300C1C0x300C1F0x300C200x300C20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_60x300C240x300CFF0x300D000x300D00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_60x300D040x300D04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_60x300D080x300D08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_60x300D0C0x300D0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_60x300D100x300D10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_60x300D140x300D14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_60x300D180x300D18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_60x300D1C0x300D1F0x300D200x300D20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_60x300D240x300DFF0x300E000x300E00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_70x300E040x300E04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_70x300E080x300E08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_70x300E0C0x300E0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_70x300E100x300E10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_70x300E140x300E14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_70x300E180x300E18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_70x300E1C0x300E1F0x300E200x300E20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_70x300E240x300EFF0x300F000x300F00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_70x300F040x300F04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_70x300F080x300F08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_70x300F0C0x300F0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_70x300F100x300F10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_70x300F140x300F14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_70x300F180x300F18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_70x300F1C0x300F1F0x300F200x300F20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_70x300F240x300FFF0x3010000x301000AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_80x3010040x301004AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_80x3010080x301008AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_80x30100C0x30100CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_80x3010100x301010AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_80x3010140x301014AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_80x3010180x301018AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_80x30101C0x30101F0x3010200x301020AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_80x3010240x3010FF0x3011000x301100AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_80x3011040x301104AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_80x3011080x301108AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_80x30110C0x30110CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_80x3011100x301110AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_80x3011140x301114AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_80x3011180x301118AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_80x30111C0x30111F0x3011200x301120AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_80x3011240x3011FF0x3012000x301200AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_90x3012040x301204AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_90x3012080x301208AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_90x30120C0x30120CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_90x3012100x301210AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_90x3012140x301214AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_90x3012180x301218AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_90x30121C0x30121F0x3012200x301220AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_90x3012240x3012FF0x3013000x301300AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_90x3013040x301304AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_90x3013080x301308AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_90x30130C0x30130CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_90x3013100x301310AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_90x3013140x301314AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_90x3013180x301318AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_90x30131C0x30131F0x3013200x301320AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_90x3013240x3013FF0x3014000x301400AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_100x3014040x301404AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_100x3014080x301408AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_100x30140C0x30140CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_100x3014100x301410AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_100x3014140x301414AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_100x3014180x301418AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_100x30141C0x30141F0x3014200x301420AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_100x3014240x3014FF0x3015000x301500AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_100x3015040x301504AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_100x3015080x301508AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_100x30150C0x30150CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_100x3015100x301510AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_100x3015140x301514AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_100x3015180x301518AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_100x30151C0x30151F0x3015200x301520AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_100x3015240x3015FF0x3016000x301600AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_110x3016040x301604AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_110x3016080x301608AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_110x30160C0x30160CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_110x3016100x301610AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_110x3016140x301614AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_110x3016180x301618AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_110x30161C0x30161F0x3016200x301620AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_110x3016240x3016FF0x3017000x301700AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_110x3017040x301704AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_110x3017080x301708AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_110x30170C0x30170CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_110x3017100x301710AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_110x3017140x301714AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_110x3017180x301718AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_110x30171C0x30171F0x3017200x301720AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_110x3017240x3017FF0x3018000x301800AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_120x3018040x301804AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_120x3018080x301808AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_120x30180C0x30180CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_120x3018100x301810AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_120x3018140x301814AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_120x3018180x301818AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_120x30181C0x30181F0x3018200x301820AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_120x3018240x3018FF0x3019000x301900AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_120x3019040x301904AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_120x3019080x301908AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_120x30190C0x30190CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_120x3019100x301910AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_120x3019140x301914AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_120x3019180x301918AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_120x30191C0x30191F0x3019200x301920AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_120x3019240x3019FF0x301A000x301A00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_130x301A040x301A04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_130x301A080x301A08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_130x301A0C0x301A0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_130x301A100x301A10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_130x301A140x301A14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_130x301A180x301A18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_130x301A1C0x301A1F0x301A200x301A20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_130x301A240x301AFF0x301B000x301B00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_130x301B040x301B04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_130x301B080x301B08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_130x301B0C0x301B0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_130x301B100x301B10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_130x301B140x301B14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_130x301B180x301B18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_130x301B1C0x301B1F0x301B200x301B20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_130x301B240x301BFF0x301C000x301C00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_140x301C040x301C04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_140x301C080x301C08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_140x301C0C0x301C0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_140x301C100x301C10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_140x301C140x301C14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_140x301C180x301C18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_140x301C1C0x301C1F0x301C200x301C20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_140x301C240x301CFF0x301D000x301D00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_140x301D040x301D04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_140x301D080x301D08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_140x301D0C0x301D0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_140x301D100x301D10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_140x301D140x301D14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_140x301D180x301D18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_140x301D1C0x301D1F0x301D200x301D20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_140x301D240x301DFF0x301E000x301E00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_150x301E040x301E04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_150x301E080x301E08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_150x301E0C0x301E0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_150x301E100x301E10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_150x301E140x301E14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_150x301E180x301E18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_150x301E1C0x301E1F0x301E200x301E20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_150x301E240x301EFF0x301F000x301F00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_150x301F040x301F04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_150x301F080x301F08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_150x301F0C0x301F0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_150x301F100x301F10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_150x301F140x301F14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_150x301F180x301F18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_150x301F1C0x301F1F0x301F200x301F20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_150x301F240x3020FF0x3021000x302100AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_16PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_160x3021040x302104AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_16PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_160x3021080x302108AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_160x30210C0x30210CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_160x3021100x302110AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_160x3021140x302114AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_160x3021180x302118AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_160x30211C0x30211F0x3021200x302120AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_160x3021240x3022FF0x3023000x302300AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_17PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_170x3023040x302304AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_17PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_170x3023080x302308AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_170x30230C0x30230CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_170x3023100x302310AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_170x3023140x302314AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_170x3023180x302318AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_170x30231C0x30231F0x3023200x302320AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_170x3023240x3024FF0x3025000x302500AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_18PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_180x3025040x302504AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_18PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_180x3025080x302508AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_180x30250C0x30250CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_180x3025100x302510AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_180x3025140x302514AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_180x3025180x302518AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_180x30251C0x30251F0x3025200x302520AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_180x3025240x3026FF0x3027000x302700AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_19PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_190x3027040x302704AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_19PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_190x3027080x302708AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_190x30270C0x30270CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_190x3027100x302710AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_190x3027140x302714AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_190x3027180x302718AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_190x30271C0x30271F0x3027200x302720AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_190x3027240x3028FF0x3029000x302900AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_20PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_200x3029040x302904AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_20PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_200x3029080x302908AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_200x30290C0x30290CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_200x3029100x302910AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_200x3029140x302914AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_200x3029180x302918AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_200x30291C0x30291F0x3029200x302920AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_200x3029240x302AFF0x302B000x302B00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_21PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_210x302B040x302B04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_21PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_210x302B080x302B08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_210x302B0C0x302B0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_210x302B100x302B10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_210x302B140x302B14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_210x302B180x302B18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_210x302B1C0x302B1F0x302B200x302B20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_210x302B240x302CFF0x302D000x302D00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_22PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_220x302D040x302D04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_22PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_220x302D080x302D08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_220x302D0C0x302D0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_220x302D100x302D10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_220x302D140x302D14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_220x302D180x302D18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_220x302D1C0x302D1F0x302D200x302D20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_220x302D240x302EFF0x302F000x302F00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_23PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_230x302F040x302F04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_23PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_230x302F080x302F08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_230x302F0C0x302F0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_230x302F100x302F10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_230x302F140x302F14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_230x302F180x302F18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_230x302F1C0x302F1F0x302F200x302F20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_230x302F240x3030FF0x3031000x303100AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_24PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_240x3031040x303104AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_24PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_240x3031080x303108AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_240x30310C0x30310CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_240x3031100x303110AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_240x3031140x303114AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_240x3031180x303118AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_240x30311C0x30311F0x3031200x303120AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_240x3031240x3032FF0x3033000x303300AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_25PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_250x3033040x303304AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_25PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_250x3033080x303308AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_250x30330C0x30330CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_250x3033100x303310AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_250x3033140x303314AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_250x3033180x303318AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_250x30331C0x30331F0x3033200x303320AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_250x3033240x3034FF0x3035000x303500AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_26PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_260x3035040x303504AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_26PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_260x3035080x303508AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_260x30350C0x30350CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_260x3035100x303510AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_260x3035140x303514AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_260x3035180x303518AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_260x30351C0x30351F0x3035200x303520AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_260x3035240x3036FF0x3037000x303700AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_27PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_270x3037040x303704AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_27PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_270x3037080x303708AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_270x30370C0x30370CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_270x3037100x303710AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_270x3037140x303714AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_270x3037180x303718AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_270x30371C0x30371F0x3037200x303720AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_270x3037240x3038FF0x3039000x303900AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_28PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_280x3039040x303904AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_28PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_280x3039080x303908AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_280x30390C0x30390CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_280x3039100x303910AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_280x3039140x303914AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_280x3039180x303918AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_280x30391C0x30391F0x3039200x303920AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_280x3039240x303AFF0x303B000x303B00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_29PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_290x303B040x303B04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_29PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_290x303B080x303B08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_290x303B0C0x303B0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_290x303B100x303B10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_290x303B140x303B14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_290x303B180x303B18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_290x303B1C0x303B1F0x303B200x303B20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_290x303B240x303CFF0x303D000x303D00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_30PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_300x303D040x303D04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_30PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_300x303D080x303D08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_300x303D0C0x303D0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_300x303D100x303D10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_300x303D140x303D14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_300x303D180x303D18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_300x303D1C0x303D1F0x303D200x303D20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_300x303D240x303EFF0x303F000x303F00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_31PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_310x303F040x303F04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_31PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_310x303F080x303F08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_310x303F0C0x303F0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_310x303F100x303F10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_310x303F140x303F14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_310x303F180x303F18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_310x303F1C0x303F1F0x303F200x303F20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_310x303F240x31FF230x31FF240x37FFFF0x3800000x381123AXI_Slave.PF0_DMA_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP0x3800000x380000AXI_Slave.PF0_DMA_CAP.DMA_CTRL_DATA_ARB_PRIOR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CTRL_DATA_ARB_PRIOR_OFF0x3800040x3800070x3800080x380008AXI_Slave.PF0_DMA_CAP.DMA_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CTRL_OFF0x38000C0x38000CAXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_EN_OFF0x3800100x380010AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DOORBELL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DOORBELL_OFF0x3800140x3800170x3800180x380018AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF0x38001C0x38001CAXI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF0x3800200x38002B0x38002C0x38002CAXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_EN_OFF0x3800300x380030AXI_Slave.PF0_DMA_CAP.DMA_READ_DOORBELL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DOORBELL_OFF0x3800340x3800370x3800380x380038AXI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF0x38003C0x38003CAXI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF0x3800400x38004B0x38004C0x38004CAXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_STATUS_OFF0x3800500x3800530x3800540x380054AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_MASK_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_MASK_OFF0x3800580x380058AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_CLEAR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_CLEAR_OFF0x38005C0x38005CAXI_Slave.PF0_DMA_CAP.DMA_WRITE_ERR_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ERR_STATUS_OFF0x3800600x380060AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_LOW_OFF0x3800640x380064AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_HIGH_OFF0x3800680x380068AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_LOW_OFF0x38006C0x38006CAXI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_HIGH_OFF0x3800700x380070AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH01_IMWR_DATA_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH01_IMWR_DATA_OFF0x3800740x380074AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH23_IMWR_DATA_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH23_IMWR_DATA_OFF0x3800780x380078AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH45_IMWR_DATA_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH45_IMWR_DATA_OFF0x38007C0x38007CAXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH67_IMWR_DATA_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH67_IMWR_DATA_OFF0x3800800x38008F0x3800900x380090AXI_Slave.PF0_DMA_CAP.DMA_WRITE_LINKED_LIST_ERR_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_LINKED_LIST_ERR_EN_OFF0x3800940x38009F0x3800A00x3800A0AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_STATUS_OFF0x3800A40x3800A70x3800A80x3800A8AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_MASK_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_MASK_OFF0x3800AC0x3800ACAXI_Slave.PF0_DMA_CAP.DMA_READ_INT_CLEAR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_CLEAR_OFF0x3800B00x3800B30x3800B40x3800B4AXI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_LOW_OFF0x3800B80x3800B8AXI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_HIGH_OFF0x3800BC0x3800C30x3800C40x3800C4AXI_Slave.PF0_DMA_CAP.DMA_READ_LINKED_LIST_ERR_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_LINKED_LIST_ERR_EN_OFF0x3800C80x3800CB0x3800CC0x3800CCAXI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_LOW_OFF0x3800D00x3800D0AXI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_HIGH_OFF0x3800D40x3800D4AXI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_LOW_OFF0x3800D80x3800D8AXI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_HIGH_OFF0x3800DC0x3800DCAXI_Slave.PF0_DMA_CAP.DMA_READ_CH01_IMWR_DATA_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH01_IMWR_DATA_OFF0x3800E00x3800E0AXI_Slave.PF0_DMA_CAP.DMA_READ_CH23_IMWR_DATA_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH23_IMWR_DATA_OFF0x3800E40x3800E4AXI_Slave.PF0_DMA_CAP.DMA_READ_CH45_IMWR_DATA_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH45_IMWR_DATA_OFF0x3800E80x3800E8AXI_Slave.PF0_DMA_CAP.DMA_READ_CH67_IMWR_DATA_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH67_IMWR_DATA_OFF0x3800EC0x3801070x3801080x380108AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF0x38010C0x38010CAXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF0x3801100x3801170x3801180x380118AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF0x38011C0x38011CAXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF0x3801200x3801FF0x3802000x380200AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_00x3802040x380204AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_00x3802080x380208AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_00x38020C0x38020CAXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_00x3802100x380210AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_00x3802140x380214AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_00x3802180x380218AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_00x38021C0x38021CAXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_00x3802200x380220AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_00x3802240x3802FF0x3803000x380300AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_00x3803040x380304AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_00x3803080x380308AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_00x38030C0x38030CAXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_00x3803100x380310AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_00x3803140x380314AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_00x3803180x380318AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_00x38031C0x38031CAXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_00x3803200x380320AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_00x3803240x3803FF0x3804000x380400AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_10x3804040x380404AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_10x3804080x380408AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_10x38040C0x38040CAXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_10x3804100x380410AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_10x3804140x380414AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_10x3804180x380418AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_10x38041C0x38041CAXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_10x3804200x380420AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_10x3804240x3804FF0x3805000x380500AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_10x3805040x380504AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_10x3805080x380508AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_10x38050C0x38050CAXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_10x3805100x380510AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_10x3805140x380514AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_10x3805180x380518AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_10x38051C0x38051CAXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_10x3805200x380520AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_10x3805240x3805FF0x3806000x380600AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_20x3806040x380604AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_20x3806080x380608AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_20x38060C0x38060CAXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_20x3806100x380610AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_20x3806140x380614AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_20x3806180x380618AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_20x38061C0x38061CAXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_20x3806200x380620AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_20x3806240x3806FF0x3807000x380700AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_20x3807040x380704AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_20x3807080x380708AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_20x38070C0x38070CAXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_20x3807100x380710AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_20x3807140x380714AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_20x3807180x380718AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_20x38071C0x38071CAXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_20x3807200x380720AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_20x3807240x3807FF0x3808000x380800AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_30x3808040x380804AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_30x3808080x380808AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_30x38080C0x38080CAXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_30x3808100x380810AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_30x3808140x380814AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_30x3808180x380818AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_30x38081C0x38081CAXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_30x3808200x380820AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_30x3808240x3808FF0x3809000x380900AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_30x3809040x380904AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_30x3809080x380908AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_30x38090C0x38090CAXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_30x3809100x380910AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_30x3809140x380914AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_30x3809180x380918AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_30x38091C0x38091CAXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_30x3809200x380920AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_30x3809240x381123groupPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDRPF0_TYPE0_HDRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr14080x0R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDRPF PCI-Compatible Configuration Space Header Type0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.DEVICE_ID_VENDOR_ID_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.STATUS_COMMAND_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.CLASS_CODE_REVISION_IDregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.BAR0_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.BAR1_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.BAR2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.BAR3_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.BAR4_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.BAR5_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.CARDBUS_CIS_PTR_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.EXP_ROM_BASE_ADDR_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.PCI_CAP_PTR_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.DEVICE_ID_VENDOR_ID_REGDEVICE_ID_VENDOR_ID_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr660x0R0xeb011e0aPE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REGDevice ID and Vendor ID Register.falsefalsefalsefalsePCI_TYPE0_VENDOR_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49Vendor ID.The Vendor ID register identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to populate this register with a value of FFFFh, which is an invalid value for Vendor ID.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x1e0aRPCI_TYPE0_DEVICE_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65Device ID. The Device ID register identifies the particular Function. This identifier is allocated by the vendor.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31160xeb01RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.STATUS_COMMAND_REGSTATUS_COMMAND_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr4020x4R/W0x00100000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_STATUS_COMMAND_REGStatus and Command Register.falsefalsefalsefalsePCI_TYPE0_IO_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88IO Space Enable.Controls a Function's response to I/O Space accesses. - When this bit is set, the Function is enabled to decode the address and further process I/O Space accesses. - When this bit is clear, all received I/O accesses are caused to be handled as Unsupported Requests.For a Function that does not support I/O Space accesses, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: !has_io_bar ? RO : RW - Dbi: !has_io_bar ? RO : RW 000x0R/WPCI_TYPE0_MEM_SPACE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107Memory Space Enable.Controls a Function's response to Memory Space accesses. - When this bit is set, the Function is enabled to decode the address and further process Memory Space accesses. - When this bit is clear, all received Memory Space accesses are caused to be handled as Unsupported Requests.For a Function does not support Memory Space accesses, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: !has_mem_bar ? RO : RW - Dbi: !has_mem_bar ? RO : RW 110x0R/WPCI_TYPE0_BUS_MASTER_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr130Bus Master Enable.Controls the ability of a Function to issue Memory and I/O Read/Write requests. - When this bit is set, the Function is allowed to issue Memory or I/O Requests. - When this bit is clear, the Function is not allowed to issue any Memory or I/O Requests.Requests other than Memory or I/O Requests are not controlled by this bit.Note: MSI/MSI-X interrupt Messages are in-band memory writes, setting the Bus Master Enable bit to 0b disables MSI/MSI-X interrupt Messages as well.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WPCI_TYPE0_SPECIAL_CYCLE_OPERATIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr141Special Cycle Enable.This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.330x0RPCI_TYPE_MWI_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr154Memory Write and Invalidate.This bit was originally described in the PCI Local Bus Specification and thePCI-to-PCI Bridge architecture specification. Its functionality does not applyto PCI Express, the controller hardwires this bit to 0b.440x0RPCI_TYPE_VGA_PALETTE_SNOOPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr166VGA Palette Snoop.This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge architecture specification. Its functionality does not apply to PCI Express, the controller hardwires this bit to 0b.550x0RPCI_TYPE0_PARITY_ERR_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr178Parity Error Response.This bit controls the logging of poisoned TLPs in the Master Data Parity Errorbit in the Status register. For more details see the "Error Registers" section of the PCI Express Base Specification.660x0R/WPCI_TYPE_IDSEL_STEPPINGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_SETDWC_pcie_dbi_cpcie_usp_4x8.csr189IDSEL Stepping/Wait Cycle Control.This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.770x0RPCI_TYPE0_SERRENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr205SERR# Enable.When set, this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function.Note: The errors are reported if enabled either through this bit orthrough the PCI Express specific bits in the Device Control register. For moredetails see the "Error Registers" section of the PCI Express Base Specification.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_SETDWC_pcie_dbi_cpcie_usp_4x8.csr213Reserved for future use.990x0RPCI_TYPE0_INT_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr235Interrupt Disable.Controls the ability of a Function to generate INTx emulation interrupts. - When set, Functions are prevented from asserting INTx interrupts.Note: - Any INTx emulation interrupts already asserted by the Function must be deasserted when this bit is Set. INTx interrupts use virtual wires that must, if asserted, be deasserted using the appropriate Deassert_INTx message(s) when this bit is set. - Only the INTx virtual wire interrupt(s) associated with the Function(s) for which this bit is set are affected. - For functions that generate INTx interrupts, this bit is required. For functions that do not generate INTx interrupts, this bit is optional.10100x0R/WPCI_TYPE_RESERVPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_SETDWC_pcie_dbi_cpcie_usp_4x8.csr244Reserved.15110x00R--16160x0rRSVDP_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_SETDWC_pcie_dbi_cpcie_usp_4x8.csr252Reserved for future use.18170x0RINT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr266Emulation interrupt pending.When set, indicates that an INTx emulation interrupt is pending internally in the Function. Setting the Interrupt Disable bit has no effect on the state of this bit. For Functions that do not generate INTx interrupts, the controller hardwires this bit to 0b.1919RCAP_LISTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr278Capabilities List.Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure, the controller hardwires this bit to 1b.20200x1RFAST_66MHZ_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28966MHz Capable.This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.21210x0RRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_SETDWC_pcie_dbi_cpcie_usp_4x8.csr297Reserved for future use.22220x0RFAST_B2B_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr308Fast Back to Back Transaction Capable.This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.23230x0RMASTER_DPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr324Master Data Parity Error.This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Function receives a Poisoned Completion - Function transmits a Poisoned RequestIf the Parity Error Response bit is 0b, this bit is never set.24240x0R/W1CDEV_SEL_TIMINGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_SETDWC_pcie_dbi_cpcie_usp_4x8.csr335DEVSEL Timing.This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this field to 00b.26250x0RSIGNALED_TARGET_ABORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr348Signaled Target Abort.This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. The controller hardwires this bit to 0b for Functions that do not signal Completer Abort.27270x0R/W1CRCVD_TARGET_ABORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr361Received Target Abort.This bit is set when a Requester receives a Completion with Completer Abort Completion Status. For Functions that do not make Non-Posted Requests on their own behalf, the controller hardwires this bit to 0b.28280x0R/W1CRCVD_MASTER_ABORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr375Received Master Abort.This bit is set when a Requester receives a Completion with Unsupported Request Completion Status. For Functions that do not make Non-Posted Requests on their own behalf, the controller hardwires this bit to 0b.29290x0R/W1CSIGNALED_SYS_ERRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr389Signaled System Error.This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL message, and the SERR# Enable bit in the Command register is 1b. For Functions that do not send ERR_FATAL or ERR_NONFATAL messages, the controller hardwires this bit to 0b.30300x0R/W1CDETECTED_PARITY_ERRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr401Detected Parity Error.This bit is set by a Function whenever it receives a Poisoned TLP, regardless of the state the Parity Error Response bit in the Command register.31310x0R/W1CregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.CLASS_CODE_REVISION_IDCLASS_CODE_REVISION_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr4830x8R0x00000001PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_CLASS_CODE_REVISION_IDClass Code and Revision ID Register.falsefalsefalsefalseREVISION_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr424Revision ID.The value in this register specifies a Function specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should be viewed as a vendor defined extension to the Device ID.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.700x01RPROGRAM_INTERFACEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr444Programming Interface.This field identifies a specific register-level programming interface (if any) so that device independent software can interact with the Function.Encodings for interface are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are Reserved.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1580x00RSUBCLASS_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr463Sub-Class Code.Specifies a base class sub-class, which identifies more specifically the operation of the Function.Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are Reserved.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23160x00RBASE_CLASS_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr482Base Class Code.A code that broadly classifies the type of operation the Function performs.Encodings for base class, are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are Reserved.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REGBIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr5850xCR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REGBIST, Header Type, Latency Timer, and Cache Line Size Register.falsefalsefalsefalseCACHE_LINE_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr503Cache Line Size.The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However, legacy conventional PCI software may not always be able to program this register correctly especially in the case of Hot-Plug devices. This read-write register is implemented for legacy compatibility purposes but has no effect on any PCI Express devicebehavior.700x00R/WLATENCY_MASTER_TIMERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr516Latency Timer.The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this register to 00h.1580x00RHEADER_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr527Header Layout.This field identifies the layout of the second part of the predefined header.The controller uses 000 0000b encoding.22160x00RMULTI_FUNCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr551Multi-Function Device. - When set, indicates that the Device may contain multiple Functions, but not necessarily. Software is permitted to probe for Functions other than Function 0. - When clear, software must not probe for Functions other than Function 0 unless explicitly indicated by another mechanism, such as an ARI or SR-IOV Capability structure.Except where stated otherwise, it is recommended that this bit be set if there are multiple Functions, and clear if there is only one Function.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0RBISTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr584BIST.This register is used for control and status of BIST. For Functions that do not support BIST the controller hardwires the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link.Bit descriptions: - [31]: BIST Capable.When Set, this bit indicates that the Function supports BIST. When Clear, the Function does not support BIST. - [30]: Start BIST.If BIST Capable is Set, Set this bit to invoke BIST. The Function resets the bit when BIST is complete. Software is permitted to fail the device if this bit is not Clear (BIST is not complete) 2 seconds after it had been Set. Writing this bit to 0b has no effect. This bit must be hardwired to 0b if BIST Capable is Clear. - [29:28]: Reserved. - [27:24]: Completion Code.This field encodes the status of the most recent test. A value of 0000b means that the Function has passed its test. Non-zero values mean the Function failed. Function-specific failure codes can be encoded in the non-zero values. This field's value is only meaningful when BIST Capable is Set and Start BIST is Clear. This field must be hardwired to 0000b if BIST Capable is clear.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.BAR0_REGBAR0_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr6880x10R/W0x00000004PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_BAR0_REGBAR0 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR0_MEM_IOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr620BAR0 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0RBAR0_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr648BAR0 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x2RBAR0_PREFETCHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr670BAR0 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0RBAR0_STARTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_SETDWC_pcie_dbi_cpcie_usp_4x8.csr687BAR0 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.BAR1_REGBAR1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr7850x14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_BAR1_REGBAR1 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR1_MEM_IOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr721BAR1 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0R/WBAR1_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr747BAR1 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x0R/WBAR1_PREFETCHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr767BAR1 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0R/WBAR1_STARTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_SETDWC_pcie_dbi_cpcie_usp_4x8.csr784BAR1 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.BAR2_REGBAR2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr8880x18R/W0x00000004PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_BAR2_REGBAR2 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR2_MEM_IOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr820BAR2 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0RBAR2_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr848BAR2 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x2RBAR2_PREFETCHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr870BAR2 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0RBAR2_STARTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_SETDWC_pcie_dbi_cpcie_usp_4x8.csr887BAR2 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.BAR3_REGBAR3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr9850x1CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_BAR3_REGBAR3 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR3_MEM_IOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr921BAR3 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0R/WBAR3_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr947BAR3 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x0R/WBAR3_PREFETCHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr967BAR3 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0R/WBAR3_STARTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_SETDWC_pcie_dbi_cpcie_usp_4x8.csr984BAR3 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.BAR4_REGBAR4_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr10880x20R/W0x00000004PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_BAR4_REGBAR4 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR4_MEM_IOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1020BAR4 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0RBAR4_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1048BAR4 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x2RBAR4_PREFETCHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1070BAR4 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0RBAR4_STARTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1087BAR4 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.BAR5_REGBAR5_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr11850x24R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_BAR5_REGBAR5 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR5_MEM_IOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1121BAR5 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0R/WBAR5_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1147BAR5 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x0R/WBAR5_PREFETCHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1167BAR5 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0R/WBAR5_STARTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1184BAR5 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.CARDBUS_CIS_PTR_REGCARDBUS_CIS_PTR_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr12060x28R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REGCardBus CIS Pointer Register.falsefalsefalsefalseCARDBUS_CIS_POINTERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1205CardBus CIS Pointer.Its functionality does not apply to PCI Express. It must be hardwired to 0000 0000h.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.3100x00000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REGSUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr12500x2CR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REGSubsystem ID and Subsystem Vendor ID Register.These registers are used to uniquely identify the add-in card or subsystem where the PCI Express component resides. They provide a mechanism for vendors to distinguish their products from one another even though the assemblies may have the same PCI Express component on them (and, therefore, the same Vendor ID and Device ID).falsefalsefalsefalseSUBSYS_VENDOR_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1234Subsystem Vendor ID.Subsystem Vendor IDs can be obtained from the PCI SIG and are used to identify the vendor of the add-in card or subsystem. Values for the Subsystem ID are vendor-specific.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0000RSUBSYS_DEV_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1249Subsystem ID.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31160x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.EXP_ROM_BASE_ADDR_REGEXP_ROM_BASE_ADDR_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr13070x30R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REGExpansion ROM BAR Register. This register handles the base address and size information for this expansion ROM.falsefalsefalsefalseROM_BAR_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1280Expansion ROM Enable.This bit controls whether or not the Function accepts accesses to its expansion ROM. - When this bit is 0b, the Function's expansion ROM address space is disabled. - When the bit is 1b, address decoding is enabled using the parameters in the other part of the Expansion ROM Base Address register.The Memory Space Enable bit in the Command register has precedence over the Expansion ROM Enable bit. A Function must claim accesses to its expansion ROM only if both the Memory Space Enable bit and the Expansion ROM Enable bit are set.Note: The access attributes of this field are as follows: - Wire: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R - Dbi: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R 000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1288Reserved for future use.1010x000REXP_ROM_BASE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1306Expansion ROM Base Address.Upper 21 bits of the Expansion ROM base address.The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires.Note: The access attributes of this field are as follows: - Wire: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R - Dbi: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R 31110x000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.PCI_CAP_PTR_REGPCI_CAP_PTR_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr13410x34R0x00000040PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_PCI_CAP_PTR_REGCapabilities Pointer Register. This register is used to point to a linked list of capabilities implemented by a Function.falsefalsefalsefalseCAP_POINTERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1333Capabilities Pointer. This register points to a valid capability structure. Either this structure is the PCI Express Capability structure, or a subsequent list item points to the PCI Express Capability structure. The bottom two bits are reserved, the controller sets it to 00b. Software must mask these bits off before using this register as a pointer in Configuration Space to the first entry of a linked list of new capabilities.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.700x40RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1340Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR.MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REGMAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr14070x3CR/W0x000001ffPE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REGMax_Lat, Min_Gnt, Interrupt Pin, and Interrupt Line Register. The Interrupt Line register communicates interrupt line routing information. The Interrupt Pin register identifies the legacy interrupt Message(s) the Function uses.falsefalsefalsefalseINT_LINEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1361Interrupt Line.The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin.Values in this register are programmed by system software and are system architecture specific. The Function itself does not use this value; rather the value in this register is used by device drivers and operating systems.700xffR/WINT_PINPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1398Interrupt Pin.The Interrupt Pin register identifies the legacy interrupt Message(s) the Function uses.The valid values are: - 01h, 02h, 03h, and 04h: Map to legacy interrupt Messages for INTA, INTB, INTC, and INTD respectively. - 00h: Indicates that the Function uses no legacy interrupt Message(s). - 05h through FFh: Reserved.PCI Express defines one legacy interrupt Message for a single Function device and up to four legacy interrupt Messages for a multi-Function device. For a single Function device, only INTA may be used.Any Function on a multi-Function device can use any of the INTx Messages. If a device implements a single legacy interrupt Message, it must be INTA; if it implements two legacy interrupt Messages, they must be INTA and INTB; and so forth.For a multi-Function device, all Functions may use the same INTx Message or each may have its own (up to a maximum of four Functions) or any combination thereof. A single Function can never generate an interrupt request on more than one INTx Message.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580x01RRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1406Reserved for future use.31160x0000RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_PM_CAPPF0_PM_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr17940x40R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_PM_CAPPF PCI Power Management Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PM_CAP.CAP_ID_NXT_PTR_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PM_CAP.CON_STATUS_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PM_CAP.CAP_ID_NXT_PTR_REGCAP_ID_NXT_PTR_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr16000x0R0x03c35001PE0_DWC_pcie_ctl_AXI_Slave_PF0_PM_CAP_CAP_ID_NXT_PTR_REGPower Management Capabilities Register.falsefalsefalsefalsePM_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1427Capability ID.This field returns 01h to indicate that this is the PCI Power Management Capability. Each function may have only one item in its capability list with Capability ID set to 01h.700x01RPM_NEXT_POINTERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1444Next Capability Pointer.This field provides an offset into the function's configuration space pointing to the location of next item in the capabilities list. If there are no additional items in the capabilities list, this field is set to 00h.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580x50RPM_SPEC_VERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1461Version.This field provides the Power Management specification version. The controller hardwires this field to 011b for functions compliant to PCI Express Base Specification, Revision 4.0, Version 1.0>.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.18160x3RPME_CLKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1472PME Clock.Does not apply to PCI Express, the controller hardwires it to 0b.Note: This register field is sticky.19190x0R--20200x0rDSIPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1491Device Specific Initialization.The DSI bit indicates whether special initialization of this function is required.When set, indicates that the function requires a device specific initialization sequence following a transition to the D0uninitialized state.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.21210x0RAUX_CURRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1524Aux_Current.This 3 bit field reports the Vaux auxiliary current requirements for the function.If this function implements the Data Register, the controller hardwires this field to 000b.If PME_Support is 0 xxxxb (PME assertion from D3cold is not supported), the controller hardwires this field to 0000b.For functions where PME_Support is 1 xxxxb (PME assertion from D3cold is supported), and which do not implement the Data field, the following encodings apply: - b111 375mA Vaux Max. Current Required - b110 320mA Vaux Max. Current Required - b101 270mA Vaux Max. Current Required - b100 220mA Vaux Max. Current Required - b011 160mA Vaux Max. Current Required - b010 100mA Vaux Max. Current Required - b001 55mA Vaux Max. Current Required - b000 0 self poweredNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.24220x7RD1_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1540D1_Support.If this bit is set, this function supports the D1 Power Management state. Functions that do not support D1 must always return a value of 0b for this bit.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.25250x1RD2_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1556D2_Support.If this bit is set, this function supports the D2 Power Management state. Functions that do not support D2 must always return a value of 0b for this bit.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.26260x0RPME_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1599PME_Support.This 5-bit field indicates the power states in which the function may generate a PME and/or forward PME messages.A value of 0b for any bit indicates that the function is not capable of asserting PME while in that power state. - bit(27) X XXX1b - PME can be generated from D0 - bit(28) X XX1Xb - PME can be generated from D1 - bit(29) X X1XXb - PME can be generated from D2 - bit(30) X 1XXXb - PME can be generated from D3hot - bit(31) 1 XXXXb - PME can be generated from D3coldBit 31 (PME can be asserted from D3cold) represents a special case. Functions that set this bit require some sort of auxiliary power source. Implementation specific mechanisms are recommended to validate that the power source is available before setting this bit.Each bit that corresponds to a supported D-state must be set for PCI-PCI Bridge structures representing Ports on Root Complexes/Switches to indicate that the Bridge will forward PME Messages. Bit 31 must only be set if the Port is still able to forward PME Messages when main power is not available.The read value from this field is the write value && (sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1), where D1_SUPPORT and D2_SUPPORT are fields in this register.The reset value PME_SUPPORT_n && (sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1), where PME_SUPPORT_n is a configuration parameter.Note: The access attributes of this field are as follows: - Wire: R - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.3127RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PM_CAP.CON_STATUS_REGCON_STATUS_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr17930x4R/W0x00000008PE0_DWC_pcie_ctl_AXI_Slave_PF0_PM_CAP_CON_STATUS_REGPower Management Control and Status Register.This register is used to manage the PCI function's power management state as well as to enable/monitor PMEs.falsefalsefalsefalsePOWER_STATEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1644PowerState.This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below.You can write to this register; however, the read-back value is the actual power state, not the write value. If you attempt to write an unsupported, optional state to this field, the write operation completes normally; however, the data is discarded and no state change occurs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 10R/WfalsetruefalseD00x0D0 power stateD10x1D1 power stateD20x2D2 power stateD3hot0x3D3hot D3hot power stateRSVDP_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1652Reserved for future use.220x0RNO_SOFT_RSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1678No_Soft_Reset.This bit indicates the state of the function after writing the PowerState field to transition the function from D3hot to D0. - When set, this transition preserves internal function state. The function is in D0Active and no additional software intervention is required. - When clear, this transition results in undefined internal function state.Regardless of this bit, functions that transition from D3hot to D0 by Fundamental Reset will return to D0Uninitialized with only PME context preserved if PME is supported and enabled.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.330x1RRSVDP_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1686Reserved for future use.740x0RPME_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1707PME_En. - When set, the function is permitted to generate a PME. - When clear, the function is not permitted to generate a PME.If PME_Support is 1 xxxxb (PME generation from D3cold) or the function consumes Aux power and Aux power is available this bit is RWS and the bit is not modified by Conventional Reset or FLR.If PME_Support is 0 xxxxb, this field is not sticky (RW).If PME_Support is 0 0000b, the controller hardwires this bit to 0b.Note: This register field is sticky.88R/WDATA_SELECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1719Data_Select.This 4-bit field is used to select which data is to be reported through the Data and Data_Scale field. If the Data field is not implemented, this field must be hardwired to 0000b.1290x0RDATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1733Data_Scale.This field indicates the scaling factor to be used when interpreting the value of the Data field. The value and meaning of this field varies depending on which data value has been selected by the Data_Select field. For more details, see 7.5.2.3 section of PCI Express Base Specification.14130x0RPME_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1752PME_Status.This bit is set when the function normally generates a PME signal. The value of this bit is not affected by the value of the PME_En bit.If PME_Support bit 31 of the Power Management Capabilities register is clear, this bit is permitted to be hardwired to 0b.Functions that consume Aux power must preserve the value of this sticky register when Aux power is available. In such functions, this register value is not modified by Conventional Reset or FLR.15150x0R/W1CRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1760Reserved for future use.21160x00RB2_B3_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1770B2B3 Support for D3hot.For a description of this standard PCIe register field, see the PCI Express Base Specification.22220x0RBUS_PWR_CLK_CON_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1780Bus Power/Clock Control Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.23230x0RDATA_REG_ADD_INFOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1792Data.This field is used to report the state dependent data requested by the Data_Select field. The value of this field is scaled by the value reported by the Data_Scale field.31240x00RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAPPF0_MSI_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr21920x50R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_MSI_CAPPF MSI Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.PCI_MSI_CAP_ID_NEXT_CTRL_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_04H_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_08H_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_0CH_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_10H_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_14H_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.PCI_MSI_CAP_ID_NEXT_CTRL_REGPCI_MSI_CAP_ID_NEXT_CTRL_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr19730x0R/W0x038a7005PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REGMSI Capability Header and Message Control Register.falsefalsefalsefalsePCI_MSI_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1812Capability ID.Indicates the MSI Capability structure. This field returns a Capability ID of 05h indicating that this is an MSI Capability structure.700x05RPCI_MSI_CAP_NEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1829Next Capability Pointer.This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580x70RPCI_MSI_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1846MSI Enable. - If set and the MSI-X Enable bit in the MSI-X Message Control register is clear, the function is permitted to use MSI to request service and is prohibited from using INTx interrupts. System configuration software sets this bit to enable MSI. A device driver is prohibited from writing this bit to mask a function's service request. For more details on control of INTx interrupts, see section 7.5.1.1 of PCI Express Base Specification. - If clear, the function is prohibited from using MSI to request service.16160x0R/WPCI_MSI_MULTIPLE_MSG_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1872Multiple Message Capable.System software reads this field to determine the number of requested vectors. The number of requested vectors must be aligned to a power of two (if a function requires three vectors, it requests four by initializing this field to 010b). The encoding is defined as: - 000b: 1 vector requested - 001b: 2 vectors requested - 010b: 4 vectors requested - 011b: 8 vectors requested - 100b: 16 vectors requested - 101b: 32 vectors requested - 110b: Reserved - 111b: ReservedNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.19170x5RPCI_MSI_MULTIPLE_MSG_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1897Multiple Message Enable.Software writes to this field to indicate the number of allocated vectors (equal to or less than the number of requested vectors). The number of allocated vectors is aligned to a power of two. If a function requests four vectors (indicated by a Multiple Message Capable encoding of 010b), system software can allocate either four, two, or one vector by writing a 010b, 001b, or 000b to this field, respectively. When MSI is enabled, a function will be allocated at least 1 vector. The encoding is defined as: - 000b: 1 vector allocated - 001b: 2 vectors allocated - 010b: 4 vectors allocated - 011b: 8 vectors allocated - 100b: 16 vectors allocated - 101b: 32 vectors allocated - 110b: Reserved - 111b: Reserved22200x0R/WPCI_MSI_64_BIT_ADDR_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr191764 bit address capable. - If set, the function is capable of sending a 64-bit message address. - If clear, the function is not capable of sending a 64-bit message address.This bit must be set if the function is a PCI Express Endpoint.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.23230x1RPCI_PVM_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1930Per-Vector Masking Capable. - If set, the function supports MSI Per-Vector Masking. - If clear, the function does not support MSI Per-Vector Masking.This bit must be set if the function is a PF or VF within an SR-IOV Device.24240x1RPCI_MSI_EXT_DATA_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1947Extended Message Data Capable. - If set, the function is capable of providing Extended Message Data. - If clear, the function does not support providing Extended Message Data.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.25250x1RPCI_MSI_EXT_DATA_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1964Extended Message Data Enable. - If set, the function is enabled to provide Extended Message Data. - If clear, the function is not enabled to provide Extended Message Data.Note: The access attributes of this field are as follows: - Wire: PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_MSI_EXT_DATA_CAP ? RW : RO - Dbi: PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_MSI_EXT_DATA_CAP ? RW : RO 26260x0R/WRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1972Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_04H_REGMSI_CAP_OFF_04H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr20010x4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_04H_REGMessage Address Register for MSI (Offset 04h).falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr1984Reserved for future use.100x0RPCI_MSI_CAP_OFF_04HPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2000Message Address - System-specified message address.If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG register) is set, the contents of this field specify the DWORD-aligned address (Address[31:02]) for the MSI transaction. Address[1:0] are set to 00b.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3120x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_08H_REGMSI_CAP_OFF_08H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr20810x8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_08H_REGFor a function that supports a 32-bit message address, - bits[31:16] of this register represent the Extended Message Data, and - bits[15:0] of this register represent the Message DataFor a function that supports a 64-bit message address (bit 23 in PCI_MSI_CAP_ID_NEXT_CTRL_REG register set), this register represents the Message Upper Address Register for MSI (Offset 08h). It specifies the Message Upper Address (System-specified message upper address). This register is required for PCI Express Endpoints and is optional for other function types. If the Message Enable bit (bit 0 of the Message Control register) is set, the contents of this register (if non-zero) specify the upper 32-bits of a 64-bit message address (Address[63:32]). If the contents of this register are zero, the Function uses the 32 bit address specified by the Message Address register.falsefalsefalsefalsePCI_MSI_CAP_OFF_08HPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2051For a function that supports a 32-bit message address, this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set, the function sends a DWORD Memory Write transaction using Message Data for the lower 16 bits. All 4 Byte Enables are set. The Multiple Message Enable field (bits 22:20 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) defines the number of low order message data bits the function is permitted to modify to generate its system software allocated vectors. For example, a Multiple Message Enable encoding of 010b indicates the function has been allocated four vectors and is permitted to modify message data bits 1 and 0 (a function modifies the lower message data bits to generate the allocated number of vectors). If the Multiple Message Enable field is 000b, the Function is not permitted to modify the message data.For a function that supports a 64-bit message address, it contains lower 16 bits of the Message Upper Address.Note: The access attributes of this field are as follows: - Wire: PCI_MSI_64_BIT_ADDR_CAP ? R/W : R - Dbi: PCI_MSI_64_BIT_ADDR_CAP ? R/W : R 1500x0000R/WPCI_MSI_CAP_OFF_0AHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2080For a function that supports a 32-bit message address, this field contains Extended Message Data (System-specified message data). For the MSI Capability structures without per-vector masking, it must be implemented if the Extended Message Data Capable bit is set; otherwise, it is outside the MSI Capability structure and undefined. For the MSI Capability structures with Per-vector Masking, it must be implemented if the Extended Message Data Capable bit is set; otherwise, it is RsvdP. If the Extended Message Data Enable bit (bit 26 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set, the DWORD Memory Write transaction uses Extended Message Data for the upper 16 bits; otherwise, it uses 0000h for the upper 16 bits.For a function that supports a 64-bit message address, it contains upper 16 bits of the Message Upper Address.Note: The access attributes of this field are as follows: - Wire: PCI_MSI_64_BIT_ADDR_CAP || `DEFAULT_EXT_MSI_DATA_CAPABLE ? R/W : R - Dbi: PCI_MSI_64_BIT_ADDR_CAP || `DEFAULT_EXT_MSI_DATA_CAPABLE ? R/W : R 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_0CH_REGMSI_CAP_OFF_0CH_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr21460xCR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REGFor a function that supports a 32-bit message address, this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message address, this register contains Message Data.falsefalsefalsefalsePCI_MSI_CAP_OFF_0CHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2124For a function that supports a 32-bit message address, this field contains the lower Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set.For a function that supports a 64-bit message address, this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set, the function sends a DWORD Memory Write transaction using Message Data for the lower 16 bits. All 4 Byte Enables are set. The Multiple Message Enable field (bits 22:20 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) defines the number of low order message data bits the function is permitted to modify to generate its system software allocated vectors. For example, a Multiple Message Enable encoding of 010b indicates the function has been allocated four vectors and is permitted to modify message data bits 1 and 0 (a function modifies the lower message data bits to generate the allocated number of vectors). If the Multiple Message Enable field is 000b, the Function is not permitted to modify the message data.Note: The access attributes of this field are as follows: - Wire: PCI_MSI_64_BIT_ADDR_CAP || MSI_PVM_EN ? R/W : R - Dbi: PCI_MSI_64_BIT_ADDR_CAP || MSI_PVM_EN ? R/W : R 1500x0000R/WPCI_MSI_CAP_OFF_0EHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2145For a function that supports a 32-bit message address, this field contains the upper Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set.For a function that supports a 64-bit message address, this field contains Message Data (System-specified message data).Note: The access attributes of this field are as follows: - Wire: (!MSI_64_EN && MSI_PVM_EN_VALUE) ? RW: MSI_64_EN && DEFAULT_EXT_MSI_DATA_CAPABLE ? RW : RO - Dbi: (!MSI_64_EN && MSI_PVM_EN_VALUE) ? RW: MSI_64_EN && DEFAULT_EXT_MSI_DATA_CAPABLE ? RW : RO 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_10H_REGMSI_CAP_OFF_10H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr21750x10R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_10H_REGFor a function that supports a 32-bit message address, this register contains the Pending Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message address, this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set.falsefalsefalsefalsePCI_MSI_CAP_OFF_10HPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2174Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For 32-bit contains Pending Bits. For 64-bit, contains Mask Bits.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: PCI_MSI_64_BIT_ADDR_CAP && MSI_PVM_EN ? R/W : R - Dbi: PCI_MSI_64_BIT_ADDR_CAP && MSI_PVM_EN ? R/W : R 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_14H_REGMSI_CAP_OFF_14H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr21910x14R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_14H_REGPending Bits Register for MSI. This register is used for a function that supports a 64-bit message address when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set.falsefalsefalsefalsePCI_MSI_CAP_OFF_14HPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2190Pending Bits. For each pending bit that is set, the function has a pending associated message.3100x00000000RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAPPF0_PCIE_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr49720x70R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAPPF PCI Express Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL_DEVICE_STATUSregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.LINK_CONTROL_LINK_STATUS_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL2_DEVICE_STATUS2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.LINK_CONTROL2_LINK_STATUS2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGPCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr23490x0R0x0002b010PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGPCI Express Capabilities, ID, Next Pointer Register.falsefalsefalsefalsePCIE_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2210Capability ID. Indicates the PCI Express Capability structure. This field must return a Capability ID of 10h indicating that this is a PCI Express Capability structure.700x10RPCIE_CAP_NEXT_PTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2225Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580xb0RPCIE_CAP_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2249Capability Version. Indicates PCI-SIG defined PCI Express Capability structure version number.A version of the specification that changes the PCI Express Capability structure in a way that is not otherwise identifiable (for example, through a new Capability field) is permitted to increment this field. All such changes to the PCI Express Capability structure must be software-compatible. Software must check for Capability Version numbers that are greater than or equal to the highest number defined when the software is written, as functions reporting any such Capability Version numbers will contain a PCI Express Capability structure that is compatible with that piece of software.The controller hardwires this field to 2h for functions compliant to PCI Express Base Specification, Revision 4.0, Version 1.0.Note: This register field is sticky.19160x2RPCIE_DEV_PORT_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2276Device/Port Type. Indicates the specific type of this PCI Express function.Note: Different functions in a Multi-Function Device can generally be of different types.Defined encodings for functions that implement a Type 00h PCI Configuration Space header are: - 0000b PCI Express Endpoint - 0001b Legacy PCI Express EndpointDefined encodings for functions that implement a Type 01h PCI Configuration Space header are: - 0100b Root Port of PCI Express Root Complex - 0101b Upstream Port of PCI Express Switch - 0110b Downstream Port of PCI Express SwitchAll other encodings are Reserved.Note: Different Endpoint types have notably different requirements in Section 1.3.2 of PCI Express Base Specification regarding I/O resources, Extended Configuration Space, and other capabilities.2320RPCIE_SLOT_IMPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2292Slot Implemented. When set, this bit indicates that the Link associated with this Port is connected to a slot (as compared to being connected to a system-integrated device or being disabled). This bit is valid for Downstream Ports. This bit is undefined for Upstream Ports.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 24240x0RPCIE_INT_MSG_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2334PCIE Interrupt Message Number.For a description of this standard PCIe register field, see the PCI Express Base Specification.Interrupt Message Number. This field indicates which MSI/MSI-X vector is used for the interrupt message generated in association with any of the status bits of this Capability structure.For MSI, the value in this field indicates the offset between the base Message Data and the interrupt message that is generated. Hardware is required to update this field so that it is correct if the number of MSI Messages assigned to the Function changes when software writes to the Multiple Message Enable field in the MSI Message Control register.For MSI-X, the value in this field indicates which MSI-X Table entry is used to generate the interrupt message. The entry must be one of the first 32 entries even if the Function implements more than 32 entries. For a given MSI-X implementation, the entry must remain constant.If both MSI and MSI-X are implemented, they are permitted to use different vectors, though software is permitted to enable only one mechanism at a time. If MSI-X is enabled, the value in this field must indicate the vector for MSI-X. If MSI is enabled or neither is enabled, the value in this field must indicate the vector for MSI. If software enables both MSI and MSI-X at the same time, the value in this field is undefined.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.29250x00RRSVDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2341Reserved.30300x0RRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2348Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES_REGDEVICE_CAPABILITIES_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr26390x4R0x00008fe1PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REGDevice Capabilities Register.The Device Capabilities register identifies PCI Express device function specific capabilities.falsefalsefalsefalsePCIE_CAP_MAX_PAYLOAD_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2381Max_Payload_Size Supported.This field indicates the maximum payload size that the function can support for TLPs.Defined encodings are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max payload size - 011b: 1024 bytes max payload size - 100b: 2048 bytes max payload size - 101b: 4096 bytes max payload size - 110b: Reserved - 111b: ReservedThe functions of a Multi-Function Device are permitted to report different values for this field.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.200x1RPCIE_CAP_PHANTOM_FUNC_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2435Phantom Functions Supported.This field indicates the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called Phantom Functions) with the Tag identifier (see Section 2.2.6.2 of PCI Express Base Specification for a description of Tag Extensions).With every Function in an ARI Device, the Phantom Functions Supported field must be set to 00b. The remainder of this field description applies only to non-ARI Multi-Function Devices.This field indicates the number of most significant bits of the Function Number portion of Requester ID that are logically combined with the Tag identifier.Defined encodings are: - 00b: No Function Number bits are used for Phantom Functions. Multi-Function Devices are permitted to implement up to 8 independent functions. - 01b: The most significant bit of the Function number in Requester ID is used for Phantom Functions; a Multi-Function Device is permitted to implement Functions 0-3. Functions 0, 1, 2, and 3 are permitted to use Function Numbers 4, 5, 6, and 7 respectively as Phantom Functions. - 10b: The two most significant bits of Function Number in Requester ID are used for Phantom Functions; a Multi-Function Device is permitted to implement Functions 0-1. Function 0 is permitted to use Function Numbers 2, 4, and 6 for Phantom Functions. Function 1 is permitted to use Function Numbers 3, 5, and 7 as Phantom Functions. - 11b: All 3 bits of Function Number in Requester ID used for Phantom Functions. The device must have a single Function 0 that is permitted to use all other Function Numbers as Phantom Functions.Note: Phantom Function support for the function must be enabled by the Phantom Functions Enable field in the Device Control register before the Function is permitted to use the Function Number field in the Requester ID for Phantom Functions.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.430x0RPCIE_CAP_EXT_TAG_SUPPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2462Extended Tag Field Supported.This bit, in combination with the 10-Bit Tag Requester Supported bit in the Device Capabilities 2 register, indicates the maximum supported size of the Tag field as a Requester. This bit must be set if the 10-Bit Tag Requester Supported bit is set.Defined encodings are: - 0b: 5-bit Tag field supported - 1b: 8-bit Tag field supportedNote: 8-bit Tag field generation must be enabled by the Extended Tag Field Enable bit in the Device Control register of the Requester Function before 8-bit Tags can be generated by the Requester. See Section 2.2.6.2 of PCI Express Base Specificationfor interactions with enabling the use of 10-Bit Tags.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.550x1RPCIE_CAP_EP_L0S_ACCPT_LATENCYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2497Endpoint L0s Acceptable Latency. This field indicates the acceptable total latency that an Endpoint can withstand due to the transition from L0s state to the L0 state. It is essentially an indirect measure of the Endpoint’s internal buffering.Power management software uses the reported L0s Acceptable Latency number to compare against the L0s exit latencies reported by all components comprising the data path from this Endpoint to the Root Complex Root Port to determine whether ASPM L0s entry can be used with no loss of performance.Defined encodings are: - 000b: Maximum of 64 ns - 001b: Maximum of 128 ns - 010b: Maximum of 256 ns - 011b: Maximum of 512 ns - 100b: Maximum of 1 us - 101b: Maximum of 2 us - 110b: Maximum of 4 us - 111b: No limitFor functions other than Endpoints, this field is Reserved and the controller hardwires it to 000b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.860x7RPCIE_CAP_EP_L1_ACCPT_LATENCYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2532Endpoint L1 Acceptable Latency. This field indicates the acceptable latency that an Endpoint can withstand due to the transition from L1 state to the L0 state. It is essentially an indirect measure of the Endpoint’s internal buffering.Power management software uses the reported L1 Acceptable Latency number to compare against the L1 Exit Latencies reported (see below) by all components comprising the data path from this Endpoint to the Root Complex Root Port to determine whether ASPM L1 entry can be used with no loss of performance.Defined encodings are: - 000b: Maximum of 1 us - 001b Maximum of 2 us - 010b Maximum of 4 us - 011b Maximum of 8 us - 100b Maximum of 16 us - 101b Maximum of 32 us - 110b Maximum of 64 us - 111b No limitFor functions other than Endpoints, this field is Reserved and the controller hardwires it to 000b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W (Sticky) else R(Sticky) Note: This register field is sticky.1190x7RRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2539Reserved for future use.14120x0RPCIE_CAP_ROLE_BASED_ERR_REPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2559Role-Based Error Reporting. When set, this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification, Revision 1.0a, and later incorporated into PCI Express Base Specification, Revision 1.1. This bit must be set by all functions conforming to the ECN, PCI Express Base Specification, Revision 1.1., or subsequent PCI Express Base Specification revisions.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.15150x1RRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2566Reserved for future use.17160x0RPCIE_CAP_CAP_SLOT_PWR_LMT_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2592Captured Slot Power Limit Value.For a description of this standard PCIe register field, see the PCI Express Base Specification.Captured Slot Power Limit Value (Upstream Ports only). In combination with the Captured Slot Power Limit Scale value, specifies the upper limit on power available to the adapter.Power limit (in Watts) is calculated by multiplying the value in this field by the value in the Captured Slot Power Limit Scale field except when the Captured Slot Power Limit Scale field equals 00b (1.0x) and the Captured Slot Power Limit Value exceeds EFh, then alternative encodings are used (for more details, see section 7.5.3.9 of PCI Express Base Specification).This value is set by the Set_Slot_Power_Limit Message or hardwired to 00h (for more details, see section 6.9 of PCI Express Base Specification).2518RPCIE_CAP_CAP_SLOT_PWR_LMT_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2612Captured Slot Power Limit Scale.For a description of this standard PCIe register field, see the PCI Express Base Specification.Captured Slot Power Limit Scale (Upstream Ports only). Specifies the scale used for the Slot Power Limit Value.Range of Values: - 00b: 1.0x - 01b: 0.1x - 10b: 0.01x - 11b: 0.001xThis value is set by the Set_Slot_Power_Limit Message or hardwired to 00b (for more details, see section 6.9 of PCI Express Base Specification).2726RPCIE_CAP_FLR_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2631Function Level Reset Capability. A value of 1b indicates the function supports the optional Function Level Reset mechanism described in section 6.6.2 of of PCI Express Base Specification.This bit applies to Endpoints only. For all other function types the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.28280x0RRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2638Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL_DEVICE_STATUSDEVICE_CONTROL_DEVICE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr29880x8R/W0x00002010PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUSDevice Control and Device Status Register.This register controls PCI Express device specific parameters and provides information about PCI Express device (function) specific parameters.falsefalsefalsefalsePCIE_CAP_CORR_ERR_REPORT_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2662Correctable Error Reporting Enable.This bit, in conjunction with other bits, controls sending ERR_COR Messages (for more details, see section 6.2.5, section 6.2.6, and section 6.2.10.2 of PCI Express Base Specification). For a Multi-Function device, this bit controls error reporting for each function from point-of-view of the respective function.For a Root Port, the reporting of correctable errors is internal to the root. No external ERR_COR Message is generated.000x0R/WPCIE_CAP_NON_FATAL_ERR_REPORT_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2679Non-Fatal Error Reporting Enable.This bit, in conjunction with other bits, controls sending ERR_NONFATAL Messages (for more details, see section 6.2.5 and Section 6.2.6 of PCI Express Base Specification). For a Multi-Function Device, this bit controls error reporting for each function from point-of-view of the respective Function.For a Root Port, the reporting of Non-fatal errors is internal to the root. No external ERR_NONFATAL Message is generated.110x0R/WPCIE_CAP_FATAL_ERR_REPORT_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2695Fatal Error Reporting Enable.This bit, in conjunction with other bits, controls sending ERR_FATAL Messages (for more details, see section 6.2.5 and section 6.2.6 of of PCI Express Base Specification). For a Multi-Function device, this bit controls error reporting for each function from point-of-view of the respective function.For a Root Port, the reporting of Fatal errors is internal to the root. No external ERR_FATAL Message is generated.220x0R/WPCIE_CAP_UNSUPPORT_REQ_REP_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2709Unsupported Request Reporting Enable.This bit, in conjunction with other bits, controls the signaling of Unsupported Request Errors by sending error Messages (for more details, see section 6.2.5 and section 6.2.6 of PCI Express Base Specification). For a Multi-Function Device, this bit controls error reporting for each Function from point-of-view of the respective Function.330x0R/WPCIE_CAP_EN_REL_ORDERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2729Enable Relaxed Ordering.If this bit is set, the function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering (for more details, see section 2.2.6.4 and section 2.4 of PCI Express Base Specification).For a function that never sets the Relaxed Ordering attribute in transactions it initiates as a Requester, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x1R/WPCIE_CAP_MAX_PAYLOAD_SIZE_CSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2766Max_Payload_Size.This field sets maximum TLP payload size for the Function. As a Receiver, the Function must handle TLPs as large as the set value. As a Transmitter, the Function must not generate TLPs exceeding the set value. Permissible values that can be programmed are indicated by the Max_Payload_Size Supported field (PCIE_CAP_MAX_PAYLOAD_SIZE) in the Device Capabilities (DEVICE_CAPABILITIES_REG) register (for more details, see section 7.5.3.3 of PCI Express Base Specification).Defined encodings for this field are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max payload size - 011b: 1024 bytes max payload size - 100b: 2048 bytes max payload size - 101b: 4096 bytes max payload size - 110b: Reserved - 111b: ReservedFor Functions that support only the 128-byte max payload size, the controller hardwires this field to 000b.System software is not required to program the same value for this field for all the Functions of a Multi-Function device (for more details, see section 2.2.2 of PCI Express Base Specification).For ARI Devices, Max_Payload_Size is determined solely by the setting in Function0. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component.750x0R/WPCIE_CAP_EXT_TAG_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2799Extended Tag Field Enable.This bit, in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register, determines how many Tag field bits a Requester is permitted to use.When the 10-Bit Tag Requester Enable bit is clear, - If the Extended Tag Field Enable bit is set, the function is permitted to use an 8-bit Tag field as a Requester - If the Extended Tag Field Enable bit is clear, the Function is restricted to a 5-bit Tag fieldSee section 2.2.6.2 of PCI Express Base Specification for required behavior when the 10-Bit Tag Requester Enable bit is set.If software changes the value of the Extended Tag Field Enable bit while the function has outstanding Non-Posted Requests, the result is undefined.For functions that do not implement this capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: DEVICE_CAPABILITIES_REG.PCIE_CAP_EXT_TAG_SUPP ? RW : RO - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_EXT_TAG_SUPP ? RW : RO 88R/WPCIE_CAP_PHANTOM_FUNC_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2835Phantom Functions Enable.This bit, in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register, determines how many Tag field bits a Requester is permitted to use.When the 10-Bit Tag Requester Enable bit is clear, - If this bit is set, it enables a function to use unclaimed functions as Phantom functions to extend the number of outstanding transaction identifiers - If this bit is clear, the function is not allowed to use Phantom functionsFor more details, see section 2.2.6.2 of PCI Express Base Specification.Software should not change the value of this bit while the function has outstanding Non-Posted Requests; otherwise, the result is undefined.For functions that do not implement this capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: DEVICE_CAPABILITIES_REG.PCIE_CAP_PHANTOM_FUNC_SUPPORT ? RW : RO - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_PHANTOM_FUNC_SUPPORT ? RW : RO 99RPCIE_CAP_AUX_POWER_PM_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2862Aux Power PM Enable.This bit is derived by sampling the sys_aux_pwr_det input.When set this bit, enables a function to draw Aux power independent of PME Aux power. Functions that require Aux power on legacy operating systems should continue to indicate PME Aux power requirements. Aux power is allocated as requested in the Aux_Current field of the Power Management Capabilities register (PMC), independent of the PME_En bit in the Power Management Control/Status register (PMCSR). For Multi-Function devices, a component is allowed to draw Aux power if at least one of the functions has this bit set.Note: Functions that consume Aux power must preserve the value of this sticky register when Aux power is available. In such functions, this bit is not modified by Conventional Reset.For functions that do not implement this capability, the controller hardwires this bit to 0b.Note: This register field is sticky.1010R/WPCIE_CAP_EN_NO_SNOOPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2889Enable No Snoop.If this bit is set, the function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency (see section 2.2.6.5 in PCI Express Base Specification).Note: Setting this bit to 1b should not cause a function to set the No Snoop attribute on all transactions that it initiates. Even when this bit is set, a function is only permitted to set the No Snoop attribute on a transaction when it can guarantee that the address of the transaction is not stored in any cache in the system.The controller hardwires this bit 0b if a function would never set the No Snoop attribute in transactions it initiates.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 11110x0RPCIE_CAP_MAX_READ_REQ_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2912Max_Read_Request_Size.This field sets the maximum Read Request size for the function as a Requester. The function must not generate Read Requests with a size exceeding the set value. Defined encodings for this field are: - 000b: 128 bytes maximum Read Request size - 001b: 256 bytes maximum Read Request size - 010b: 512 bytes maximum Read Request size - 011b: 1024 bytes maximum Read Request size - 100b: 2048 bytes maximum Read Request size - 101b: 4096 bytes maximum Read Request size - 110b: Reserved - 111b: ReservedFor functions that do not generate Read Requests larger than 128 bytes and functions that do not generate Read Requests on their own behalf, the controller implements this field as Read Only (RO) with a value of 000b.14120x2R/W--16150x0rPCIE_CAP_NON_FATAL_ERR_DETECTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2930Non-Fatal Error Detected. This bit indicates status of Non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function device, each function indicates status of errors as perceived by the respective Function.For functions supporting Advanced Error Handling, errors are logged in this register regardless of the settings of the Uncorrectable Error Mask register.17170x0R/W1C--18180x0rPCIE_CAP_UNSUPPORTED_REQ_DETECTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2945Unsupported Request Detected.This bit indicates that the function received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function Device, each function indicates status of errors as perceived by the respective function.19190x0R/W1CPCIE_CAP_AUX_POWER_DETECTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2958AUX Power Detected.Functions that require Aux power report this bit as set if Aux power is detected by the function.This bit is derived by sampling the sys_aux_pwr_det input.2020RPCIE_CAP_TRANS_PENDINGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2979Transactions Pending.Endpoints:When set, this bit indicates that the function has issued Non-Posted Requests that have not been completed. A Function reports this bit cleared only when all outstanding Non-Posted Requests have completed or have been terminated by the Completion Timeout mechanism. This bit must also be cleared upon the completion of an FLR.Root and Switch Ports:The controller hardwires this bit to 0b.2121RRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_SETDWC_pcie_dbi_cpcie_usp_4x8.csr2987Reserved for future use.31220x000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES_REGLINK_CAPABILITIES_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr33390xCR0x00400c84PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_LINK_CAPABILITIES_REGLink Capabilities Register.The Link Capabilities register identifies PCI Express Link specific capabilities.falsefalsefalsefalsePCIE_CAP_MAX_LINK_SPEEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3028Max Link Speed.This field indicates the maximum Link speed of the associated Port.The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the maximum Link speed.Defined encodings are: - 0001b: Supported Link Speeds Vector field bit 0 - 0010b: Supported Link Speeds Vector field bit 1 - 0011b: Supported Link Speeds Vector field bit 2 - 0100b: Supported Link Speeds Vector field bit 3 - 0101b: Supported Link Speeds Vector field bit 4 - 0110b: Supported Link Speeds Vector field bit 5 - 0111b: Supported Link Speeds Vector field bit 6All other encodings are reserved.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.In M-PCIe mode, the reset and dynamic values of this field are calculated by the controller.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.300x4RPCIE_CAP_MAX_LINK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3064Maximum Link Width.This field indicates the maximum Link width (xN – corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port), adapter connector (Upstream Port), or in the case of component-to-component connections, the actual wired connection width.Defined encodings are: - 00 0001b x1 - 00 0010b x2 - 00 0100b x4 - 00 1000b x8 - 00 1100b x12 - 01 0000b x16 - 10 0000b x32All other encodings are Reserved.Multi-Function devices associated with an Upstream Port must report the same value in this field for all functions.For a description of this standard PCIe register field, see the PCI Express Base Specification.In M-PCIe mode, the reset and dynamic values of this field are calculated by the controller.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.940x08RPCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3089Active State Power Management (ASPM) Support. This field indicates the level of ASPM supported on the given PCI Express Link. For more details on ASPM support requirements, see section 5.4.1 of PCI Express Base Specification.Defined encodings are: - 00b: No ASPM Support - 01b: L0s Supported - 10b: L1 Supported - 11b: L0s and L1 SupportedMulti-Function devices associated with an Upstream Port must report the same value in this field for all functions.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.11100x3RPCIE_CAP_L0S_EXIT_LATENCYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3147L0s Exit Latency.This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. If L0s is not supported, the value is undefined; however, see the Implementation Note "Potential Issues With Legacy Software When L0s is Not Supported" in section 5.4.1.1 of PCI Express Base Specification for the recommended value.Defined encodings are: - 000b: Less than 64 ns - 001b: 64 ns to less than 128 ns - 010b: 128 ns to less than 256 ns - 011b: 256 ns to less than 512 ns - 100b: 512 ns to less than 1 us - 101b: 1 us to less than 2 us - 110b: 2 us to 4 us - 111b: More than 4 usNote: Exit latencies may be influenced by PCI Express reference clock configuration depending upon whether a component uses a common or separate reference clock.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.There are two each of these register fields, this one and a shadow one at the same address.The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the controller and which one is accessed by a read request.Common Clock operation is supported (possible) in the controller when one or more of the following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCYCommon Clock operation is enabled in the controller when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG).The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1412RPCIE_CAP_L1_EXIT_LATENCYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3201L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from ASPM L1 to L0. If ASPM L1 is not supported, the value is undefined.Defined encodings are: - 000b: Less than 1us - 001b: 1 us to less than 2 us - 010b: 2 us to less than 4 us - 011b: 4 us to less than 8 us - 100b: 8 us to less than 16 us - 101b: 16 us to less than 32 us - 110b: 32 us to 64 us - 111b: More than 64 μsNote: Exit latencies may be influenced by PCI Express reference clock configuration depending upon whether a component uses a common or separate reference clock.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.There are two each of these register fields, this one and a shadow one at the same address.The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the controller and which one is accessed by a read request.Common Clock operation is supported (possible) in the controller when one or more of the following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCYCommon Clock operation is enabled in the controller when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG).The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1715RPCIE_CAP_CLOCK_POWER_MANPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3239Clock Power Management. For Upstream Ports, a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) via the "clock request" (CLKREQ#) mechanism when the Link is in the L1 and L2/L3 Ready Link states. A value of 0b indicates the component does not have this capability and that reference clock(s) must not be removed in these Link states.L1 PM Substates defines other semantics for the CLKREQ# signal, which are managed independently of Clock Power Management.This Capability is applicable only in form factors that support "clock request" (CLKREQ#) capability.For a Multi-Function device associated with an Upstream Port, each Function indicates its capability independently. Power Management configuration software must only permit reference clock removal if all functions of the Multi-Function device indicate a 1b in this bit. For ARI Devices, all Functions must indicate the same value in this bit.For Downstream Ports, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0RPCIE_CAP_SURPRISE_DOWN_ERR_REP_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3255Surprise Down Error Reporting Capable. For a Downstream Port, this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition.For Upstream Ports and components that do not support this optional capability, the controller hardwires this bit to 0b.Note: This register field is sticky.19190x0RPCIE_CAP_DLL_ACTIVE_REP_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3274Data Link Layer Link Active Reporting Capable. For a Downstream Port, the controller hardwires this bit to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine. For a hot-plug capable Downstream Port (as indicated by the Hot-Plug Capable bit of the Slot Capabilities register) or a Downstream Port that supports Link speeds greater than 5.0 GT/s, the controller hardwires this bit to 1b.For Upstream Ports and components that do not support this optional capability, the controller hardwires this bit to 0b.20200x0RPCIE_CAP_LINK_BW_NOT_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3296Link Bandwidth Notification Capability. A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting Links wider than x1 and/or multiple Link speeds.This field is not applicable and is Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability the controller hardwires this bit to 0b.Note: This register field is sticky.21210x0RPCIE_CAP_ASPM_OPT_COMPLIANCEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3315ASPM Optionality Compliance. This bit must be set to 1b in all functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b.Software is permitted to use the value of this bit to help determine whether to enable ASPM or whether to run ASPM compliance tests.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 22220x1RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3322Reserved for future use.23230x0RPCIE_CAP_PORT_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3338Port Number. This field indicates the PCI Express Port number for the given PCI Express Link.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.LINK_CONTROL_LINK_STATUS_REGLINK_CONTROL_LINK_STATUS_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr38910x10R/W0x10000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REGLink Control and Link Status Register.This register controls and provides information about PCI Express Link specific parameters.falsefalsefalsefalsePCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3389Active State Power Management (ASPM) Control.This field controls the level of ASPM enabled on the given PCI Express Link. See section 5.4.1.3 of PCI Express Base Specification for requirements on when and how to enable ASPM.Defined encodings are: - 00b: Disabled - 01b: L0s Entry Enabled - 10b: L1 Entry Enabled - 11b: L0s and L1 Entry EnabledNote: "L0s Entry Enabled" enables the Transmitter to enter L0s. If L0s is supported, the Receiver must be capable of entering L0s even when the Transmitter is disabled from entering L0s (00b or 10b).ASPM L1 must be enabled by software in the Upstream component on a Link prior to enabling ASPM L1 in the Downstream component on that Link. When disabling ASPM L1, software must disable ASPM L1 in the Downstream component on a Link prior to disabling ASPM L1 in the Upstream component on that Link. ASPM L1 must only be enabled on the Downstream component if both components on a Link support ASPM L1.For Multi-Function Devices (including ARI Devices), it is recommended that software program the same value for this field in all Functions. For non-ARI Multi-Function Devices, only capabilities enabled in all Functions are enabled for the component as a whole.For ARI Devices, ASPM Control is determined solely by the setting in Function0, regardless of Function 0's D-state. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component.Software must not enable L0s in either direction on a given Link unless components on both sides of the Link each support L0s; otherwise, the result is undefined.100x0R/WRSVDP_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3397Reserved for future use.220x0RPCIE_CAP_RCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3437Read Completion Boundary (RCB).Root Ports:Indicates the RCB value for the Root Port. Refer to section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB.Defined encodings are: - 0b: 64 byte - 1b: 128 byteThe controller hardwires this bit for a Root Port and returns its RCB support capabilities.Endpoints and Bridges:Optionally set by configuration software to indicate the RCB value of the Root Port Upstream from the Endpoint or Bridge. Refer to Section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB.Defined encodings are: - 0b 64 byte - 1b 128 byteConfiguration software must only set this bit if the Root Port Upstream from the Endpoint or Bridge reports an RCB value of 128 bytes (a value of 1b in the Read Completion Boundary bit).For functions that do not implement this feature, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WPCIE_CAP_LINK_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3467Link Disable.This bit disables the Link by directing the LTSSM to the Disabled state when set; this bit is Reserved on Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.Writes to this bit are immediately reflected in the value read from the bit, regardless of actual Link state.After clearing this bit, software must honor timing requirements defined in Section 6.6.1 with respect to the first Configuration Read following a Conventional Reset.In a DSP that supports crosslink, the controller gates the write value with the CROSS_LINK_EN field in PORT_LINK_CTRL_OFF.Note: The access attributes of this field are as follows: - Wire: CX_CROSSLINK_ENABLE=1 && PORT_LINK_CTRL_OFF.CROSS_LINK_EN=1||CX_CROSSLINK_ENABLE=0 && dsp=1 ? RW : RO - Dbi: CX_CROSSLINK_ENABLE=1 && PORT_LINK_CTRL_OFF.CROSS_LINK_EN=1||CX_CROSSLINK_ENABLE=0 && dsp=1? RW : RO 44R/WPCIE_CAP_RETRAIN_LINKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3498Retrain Link.A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration, re-entering Recovery is permitted but not required. If the Port is in DPC when a write of 1b to this bit occurs, the result is undefined. Reads of this bit always return 0b.It is permitted to write 1b to this bit while simultaneously writing modified values to other fields in this register. If the LTSSM is not already in Recovery or Configuration, the resulting Link training must use the modified values. If the LTSSM is already in Recovery or Configuration, the modified values are not required to affect the Link training that's already in progress.This bit is not applicable and is Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.This bit always returns 0b when read.Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description 55R/WPCIE_CAP_COMMON_CLK_CONFIGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3533Common Clock Configuration. When set, this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock.A value of 0b indicates that this component and the component at the opposite end of this Link are operating with asynchronous reference clock.For non-ARI Multi-Function Devices, software must program the same value for this bit in all Functions. If not all Functions are Set, then the component must as a whole assume that its reference clock is not common with the Upstream component.For ARI Devices, Common Clock Configuration is determined solely by the setting in Function 0. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component.Components utilize this common clock configuration information to report the correct L0s and L1 Exit Latencies.After changing the value in this bit in both components on a Link, software must trigger the Link to retrain by writing a 1b to the Retrain Link bit of the Downstream Port.660x0R/WPCIE_CAP_EXTENDED_SYNCHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3552Extended Synch. When set, this bit forces the transmission of additional Ordered Sets when exiting the L0s state (see section 4.2.4.5 of PCI Express Base Specification) and when in the Recovery state (see section 4.2.6.4.1 of PCI Express Base Specification). This mode provides external devices (for example, logic analyzers) monitoring the Link time to achieve bit and Symbol lock before the Link enters the L0 state and resumes communication.For Multi-Function devices if any function has this bit set, then the component must transmit the additional Ordered Sets when exiting L0s or when in Recovery.770x0R/WPCIE_CAP_EN_CLK_POWER_MANPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3597Enable Clock Power Management.Applicable only for Upstream Ports and with form factors that support a "Clock Request" (CLKREQ#) mechanism, this bit operates as follows: - 0b: Clock power management is disabled and device must hold CLKREQ# signal low. - 1b: When this bit is set, the device is permitted to use CLKREQ# signal to power manage Link clock according to protocol defined in appropriate form factor specification.For a non-ARI Multi-Function Device, power-management-configuration software must only Set this bit if all Functions of the Multi-Function Device indicate a 1b in the Clock Power Management bit of the Link Capabilities register. The component is permitted to use the CLKREQ# signal to power manage Link clock only if this bit is Set for all Functions.For ARI Devices, Clock Power Management is enabled solely by the setting in Function 0. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component.The CLKREQ# signal may also be controlled via the L1 PM Substates mechanism. Such control is not affected by the setting of this bit.For Downstream Ports and components that do not support Clock Power Management (as indicated by a 0b value in the Clock Power Management bit of the Link Capabilities register), the controller hardwires this bit to 0b.The write value is gated with the PCIE_CAP_CLOCK_POWER_MAN field in LINK_CAPABILITIES_REG.Note: The access attributes of this field are as follows: - Wire: LINK_CAPABILITIES_REG.PCIE_CAP_CLOCK_POWER_MAN ? RWS : ROS - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_CLOCK_POWER_MAN ? RWS : ROS Note: This register field is sticky.88R/WPCIE_CAP_HW_AUTO_WIDTH_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3620Hardware Autonomous Width Disable.When set, this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RW, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is of type RsvdP.For components that do not implement the ability autonomously to change Link width, the ciontroller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WPCIE_CAP_LINK_BW_MAN_INT_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3645Link Bandwidth Management Interrupt Enable. When set, this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO 1010R/WPCIE_CAP_LINK_AUTO_BW_INT_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3670Link Autonomous Bandwidth Management Interrupt Enable.When set, this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO 1111R/WRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3678Reserved for future use.13120x0RPCIE_CAP_DRS_SIGNALING_CONTROLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3713DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are: - 00b: DRS not ReportedIf DRS Supported is set, receiving a DRS Message will set DRS Message Received in the Link Status 2 Register but will otherwise have no effect - 01b: DRS Interrupt EnabledIf the DRS Message Received bit in the Link Status 2 Register transitions from 0 to 1, and either MSI or MSI-X is enabled, an MSI or MSI-X interrupt is generated using the vector in Interrupt Message Number (section 7.5.3.2) - 10b: DRS to FRS Signaling EnabledIf the DRS Message Received bit in the Link Status 2 Register transitions from 0 to 1, the Port must send an FRS Message Upstream with the FRS Reason field set to DRS Message Received.Behavior is undefined if this field is set to 10b and the FRS Supported bit in the Device Capabilities 2 Register is Clear.Behavior is undefined if this field is set to 11b.For Downstream Ports with the DRS Supported bit clear in the Link Capabilities 2 register, the controller hardwires this field to 00b.This field is Reserved for Upstream Ports.15140x0RPCIE_CAP_LINK_SPEEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3738Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link.The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the current Link speed.Defined encodings are: - 0001b: Supported Link Speeds Vector field bit 0 - 0010b: Supported Link Speeds Vector field bit 1 - 0011b: Supported Link Speeds Vector field bit 2 - 0100b: Supported Link Speeds Vector field bit 3 - 0101b: Supported Link Speeds Vector field bit 4 - 0110b: Supported Link Speeds Vector field bit 5 - 0111b: Supported Link Speeds Vector field bit 6All other encodings are Reserved.The value in this field is undefined when the Link is not up.1916RPCIE_CAP_NEGO_LINK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3758Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link.Defined encodings are: -00 0001b: x1 -00 0010b: x2 -00 0100b: x4 -00 1000b: x8 -00 1100b: x12 -01 0000b: x16 -10 0000b: x32All other encodings are Reserved. The value in this field is undefined when the Link is not up.2520RRSVDP_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3766Reserved for future use.26260x0RPCIE_CAP_LINK_TRAININGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3787Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state, or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when the LTSSM exits the Configuration/Recovery state.This bit is not applicable and Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches, and the controller hardwires it to 0b.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: R 2727RPCIE_CAP_SLOT_CLK_CONFIGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3807Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a reference clock on the connector, this bit must be clear.For a Multi-Function Device, each Function must report the same value for this bit.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 28280x1RPCIE_CAP_DLL_ACTIVEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3822Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state, 0b otherwise.This bit must be implemented if the Data Link Layer Link Active Reporting Capable bit is 1b. Otherwise, the controller hardwires it to 0b.29290x0RPCIE_CAP_LINK_BW_MAN_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3859Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: - A Link retraining has completed following a write of 1b to the Retrain Link bit.Note: This bit is set following any write of 1b to the Retrain Link bit, including when the Link is in the process of retraining for some other reason. - Hardware has changed Link speed or width to attempt to correct unreliable Link operation, either through an LTSSM timeout or a higher level process.This bit must be set if the Physical Layer reports a speed or width change was initiated by the Downstream component that was not indicated as an autonomous change.This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.The default value of this bit is 0b.The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: R 30300x0RPCIE_CAP_LINK_AUTO_BW_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3890Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width, without the Port transitioning through DL_Down status, for reasons other than to attempt to correct unreliable Link operation.This bit must be set if the Physical Layer reports a speed or width change was initiated by the Downstream component that was indicated as an autonomous change.The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: R 31310x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES2_REGDEVICE_CAPABILITIES2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr41490x24R0x8001181fPE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REGDevice Capabilities 2 Register.falsefalsefalsefalsePCIE_CAP_CPL_TIMEOUT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3930Completion Timeout Ranges Supported. This field indicates device Function support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value.This field is applicable only to Root Ports, Endpoints that issue Requests on their own behalf, and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued on PCI Express. For all other Functions this field is Reserved and must be hardwired to 0000b.Four time value ranges are defined: - Range A: 50 us to 10 ms - Range B: 10 ms to 250 ms - Range C: 250 ms to 4 s - Range D: 4 s to 64 sBits are set according to the list below to show timeout value ranges supported. - 0000b Completion Timeout programming not supported – the Function must implement a timeout value in the range 50 μs to 50 ms. - 0001b Range A - 0010b Range B - 0011b Ranges A and B - 0110b Ranges B and C - 0111b Ranges A, B, and C - 1110b Ranges B, C, and D - 1111b Ranges A, B, C, and DAll other values are Reserved.It is strongly recommended that the Completion Timeout mechanism not expire in less than 10 ms.300xfRPCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3948Completion Timeout Disable Supported. A value of 1b indicates support for the Completion Timeout Disable mechanism.The Completion Timeout Disable mechanism is required for Endpoints that issue Requests on their own behalf and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued on PCI Express.This mechanism is optional for Root Ports.For all other Functions this field is Reserved and the controller hardwires this bit to 0b.440x1RPCIE_CAP_ARI_FORWARD_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3960ARI Forwarding Supported. Applicable only to Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability. For more details, see section 6.13 of PCI Express Base Specification.550x0RPCIE_CAP_ATOMIC_ROUTING_SUPPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr3972AtomicOp Routing Supported. Applicable only to Switch Upstream Ports, Switch Downstream Ports, and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. For more details, see section 6.15 of PCI Express Base Specification.660x0RPCIE_CAP_32_ATOMIC_CPL_SUPPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr398532-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd, Swap, and CAS AtomicOps. This bit must be set to 1b if the Function supports this optional capability. For more details on additional RC requirements, see section 6.15.3.1 of PCI Express Base Specification.770x0RPCIE_CAP_64_ATOMIC_CPL_SUPPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr399864-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd, Swap, and CAS AtomicOps. This bit must be set to 1b if the Function supports this optional capability. For more details on additional RC requirements, see section 6.15.3.1 of PCI Express Base Specification.880x0RPCIE_CAP_128_CAS_CPL_SUPPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4009128-bit CAS Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. This bit must be set to 1b if the Function supports this optional capability. For more details, see section 6.15 of PCI Express Base Specification.990x0RPCIE_CAP_NO_RO_EN_PR2PR_PARPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4027No RO-enabled PR-PR Passing. If this bit is set, the routing element never carries out the passing permitted by Table 2-39 of PCI Express Base Specification entry A2b that is associated with the Relaxed Ordering Attribute field being Set.This bit applies only for Switches and RCs that support peer-to-peer traffic between Root Ports. This bit applies only to Posted Requests being forwarded through the Switch or RC and does not apply to traffic originating or terminating within the Switch or RC itself. All Ports on a Switch or RC must report the same value for this bit.For all other functions, this bit must be 0b.10100x0RPCIE_CAP_LTR_SUPPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4050LTR Mechanism Supported. A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism.Root Ports, Switches and Endpoints are permitted to implement this capability.For a Multi-Function Device associated with an Upstream Port, each Function must report the same value for this bit.For Bridges and other Functions that do not implement this capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(Sticky) else R(Sticky) Note: This register field is sticky.11110x1RPCIE_CAP_TPH_CMPLT_SUPPORT_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4069TPH Completer Supported Bit 0. Value of this bit along with TPH Completer Supported Bit 1 indicates Completer support for TPH or Extended TPH. Applicable only to Root Ports and Endpoints. For all other Functions, this field is Reserved.Defined Encodings are: - 00b: TPH and Extended TPH Completer not supported. - 01b: TPH Completer supported; Extended TPH Completer not supported. - 10b: Reserved. - 11b: Both TPH and Extended TPH Completer supported.For more details, see section 6.17 of PCI Express Base Specification.12120x1RPCIE_CAP_TPH_CMPLT_SUPPORT_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4076TPH Completer Supported Bit 1.13130x0RPCIE_CAP2_LN_SYS_CLSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4093LN System CLS. Applicable only to Root Ports and RCRBs; must be 00b for all other Function types. This field indicates if the Root Port or RCRB supports LN protocol as an LN Completer, and if so, what cacheline size is in effect.Encodings are: - 00b LN Completer either not supported or not in effect - 01b LN Completer with 64-byte cachelines in effect - 10b LN Completer with 128-byte cachelines in effect - 11b ReservedNote: This register field is sticky.15140x0RPCIE_CAP2_10_BIT_TAG_COMP_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr410310-Bit Tag Completer Supported. If this bit is set, the Function supports 10-Bit Tag Completer capability; otherwise, the Function does not. For more details, see section 2.2.6.2. of PCI Express Base Specification.16160x1RPCIE_CAP2_10_BIT_TAG_REQ_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr412110-Bit Tag Requester Supported. If this bit is set, the Function supports 10-Bit Tag Requester capability; otherwise, the Function does not.This bit must not be set if the 10-Bit Tag Completer Supported bit is clear.Note: 10-Bit Tag field generation must be enabled by the 10-Bit Tag Requester Enable bit in the Device Control 2 register of the Requester Function before 10-Bit Tags can be generated by the Requester. For more details, see section 2.2.6.2. of PCI Express Base Specification.17170x0R--23180x0rRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4128Reserved for future use.30240x00RPCIE_CAP_FRS_SUPPORTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4148FRS Supported. When set, indicates support for the optional Function Readiness Status (FRS) capability.Must be set for all Functions that support generation or reception capabilities of FRS Messages.Must not be set by Switch Functions that do not generate FRS Messages on their own behalf.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 31310x1RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL2_DEVICE_STATUS2_REGDEVICE_CONTROL2_DEVICE_STATUS2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr42790x28R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REGDevice Control 2 and Status 2 Register.falsefalsefalsefalsePCIE_CAP_CPL_TIMEOUT_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4207Completion Timeout Value. In device Functions that support Completion Timeout programmability, this field allows system software to modify the Completion Timeout value. This field is applicable to Root Ports, Endpoints that issue Requests on their own behalf, and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued on PCI Express. For all other Functions this field is Reserved and controller hardwires it to 0000b.A Function that does not support this optional capability must hardwire this field to 0000b and is required to implement a timeout value in the range 50 μs to 50 ms. Functions that support Completion Timeout programmability must support the values given below corresponding to the programmability ranges indicated in the Completion Timeout Ranges Supported field.Defined encodings: - 0000b Default range: 50 μs to 50 msIt is strongly recommended that the Completion Timeout mechanism not expire in less than 10 ms.Values available if Range A (50 μs to 10 ms) programmability range is supported: - 0001b: 50 μs to 100 μs - 0010b: 1 ms to 10 msValues available if Range B (10 ms to 250 ms) programmability range is supported: - 0101b 16 ms to 55 ms - 0110b 65 ms to 210 msValues available if Range C (250 ms to 4 s) programmability range is supported: - 1001b 260 ms to 900 ms - 1010b 1 s to 3.5 sValues available if the Range D (4 s to 64 s) programmability range is supported: - 1101b 4 s to 13 s - 1110b 17 s to 64 sValues not defined above are Reserved.Software is permitted to change the value in this field at any time. For Requests already pending when the Completion Timeout Value is changed, hardware is permitted to use either the new or the old value for the outstanding Requests, and is permitted to base the start time for each Request either on when this value was changed or on when each request was issued.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 300x0R/WPCIE_CAP_CPL_TIMEOUT_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4228Completion Timeout Disable. When set, this bit disables the Completion Timeout mechanism.This bit is required for all Functions that support the Completion Timeout Disable Capability. Functions that do not support this optional capability are permitted to hardwire this bit to 0bSoftware is permitted to set or clear this bit at any time. When set, the Completion Timeout detection mechanism is disabled. If there are outstanding Requests when the bit is cleared, it is permitted but not required for hardware to apply the completion timeout mechanism to the outstanding Requests. If this is done, it is permitted to base the start time for each Request on either the time this bit was cleared or the time each Request was issued.440x0R/WPCIE_CAP_ARI_FORWARD_SUPPORT_CSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4242ARI Forwarding Enable. When set, the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request, permitting access to Extended Functions in an ARI Device immediately below the Port. For more details, see Section 6.13 of PCI Express Base Specification.550x0R--960x0rPCIE_CAP_LTR_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4278LTR Mechanism Enable. When set to 1b, this bit enables Upstream Ports to send LTR messages and Downstream Ports to process LTR Messages.For a Multi-Function Device associated with an Upstream Port of a device that implements LTR, the bit in Function 0 is RW, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is RsvdP.Functions that do not implement the LTR mechanism are permitted to hardwire this bit to 0b.For Downstream Ports, this bit must be reset to the default value if the Port goes to DL_Down status.The write value is gated with the PCIE_CAP_LTR_SUPP field of DEVICE_CAPABILITIES2_REG.Note: RW for function #0 and RsdvP for all other functions.Note: The access attributes of this field are as follows: - Wire: if (pf=0 && DEVICE_CAPABILITIES2_REG.PCIE_CAP_LTR_SUPP) then R/W else R - Dbi: if (pf=0 && DEVICE_CAPABILITIES2_REG.PCIE_CAP_LTR_SUPP) then R/W else R 10100x0R/W--31110x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES2_REGLINK_CAPABILITIES2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr44450x2CR/W0x81800000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_LINK_CAPABILITIES2_REGLink Capabilities 2 Register.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4290Reserved for future use.000x0RPCIE_CAP_SUPPORT_LINK_SPEED_VECTORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4321Supported Link Speeds Vector. This field indicates the supported Link speed(s) of the associated Port. For each bit, a value of 1b indicates that the corresponding Link speed is supported; otherwise, the Link speed is not supported. For more details, see section 8.2.1 of PCI Express Base Specification.Bit definitions within this field are: - Bit 0 2.5 GT/s - Bit 1 5.0 GT/s - Bit 2 8.0 GT/s - Bit 3 16.0 GT/s - Bit 4 32.0 GT/s - Bits 6:5 RsvdPMulti-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.This field has a default of (PCIE_CAP_MAX_LINK_SPEED == 0101) ? 0011111 : (PCIE_CAP_MAX_LINK_SPEED == 0100) ? 0001111 : (PCIE_CAP_MAX_LINK_SPEED == 0011) ? 0000111 : (PCIE_CAP_MAX_LINK_SPEED == 0010) ? 0000011 : 0000001 where PCIE_CAP_MAX_LINK_SPEED is a field in the LINK_CAPABILITIES_REG register.71RPCIE_CAP_CROSS_LINK_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4350Crosslink Supported. When set to 1b, this bit indicates that the associated Port supports crosslinks (for more details, see section 4.2.6.3.1 of PCI Express Base Specification). When set to 0b on a Port that supports Link speeds of 8.0 GT/s or higher, this bit indicates that the associated Port does not support crosslinks. When set to 0b on a Port that only supports Link speeds of 2.5 GT/s or 5.0 GT/s, this bit provides no information regarding the Port’s level of crosslink support.It is recommended that this bit be Set in any Port that supports crosslinks even though doing so is only required for Ports that also support operating at 8.0 GT/s or higher Link speeds.Note: Software should use this bit when referencing fields whose definition depends on whether or not the Port supports crosslinks (for more details, see section 7.7.3.4 of PCI Express Base Specification).Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.880x0RRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4358Reserved for future use.2290x0000RPCIE_CAP_RETIMER_PRE_DET_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4384Retimer Presence Detect Supported. When set to 1b, this bit indicates that the associated Port supports detection and reporting of Retimer presence.This bit must be set to 1b in a Port when the Supported Link Speeds Vector of the Link Capabilities 2 register indicates support for a Link speed of 16.0 GT/s or higher.It is permitted to be set to 1b regardless of the supported Link speeds.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 23230x1RPCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4410Two Retimers Presence Detect Supported. When set to 1b, this bit indicates that the associated Port supports detection and reporting of two Retimers presence.This bit must be set to 1b in a Port when the Supported Link Speeds Vector of the Link Capabilities 2 register indicates support for a Link speed of 16.0 GT/s or higher.It is permitted to be set to 1b regardless of the supported Link speeds if the Retimer Presence Detect Supported bit is also set to 1b.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 24240x1R/WRSVDP_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4418Reserved for future use.30250x00RDRS_SUPPORTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4444DRS Supported. When set, indicates support for the optional Device Readiness Status (DRS) capability.Must be Set in Downstream Ports that support DRS.Must be Set in Downstream Ports that support FRS.For Upstream Ports that support DRS, it is strongly recommended that this bit be Set in Function 0. For all other Functions associated with an Upstream Port, this bit must be Clear.127Must be Clear in Functions that are not associated with a Port.RsvdP in all other Functions.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 31310x1RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.LINK_CONTROL2_LINK_STATUS2_REGLINK_CONTROL2_LINK_STATUS2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr49710x30R/W0x00010000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REGLink Control 2 and Status 2 Register.falsefalsefalsefalsePCIE_CAP_TARGET_LINK_SPEEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4509Target Link Speed. For Downstream Ports, this field sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences.The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the desired target Link speed.Defined encodings are: - 0001b: Supported Link Speeds Vector field bit 0 - 0010b: Supported Link Speeds Vector field bit 1 - 0011b: Supported Link Speeds Vector field bit 2 - 0100b: Supported Link Speeds Vector field bit 3 - 0101b: Supported Link Speeds Vector field bit 4 - 0110b: Supported Link Speeds Vector field bit 5 - 0111b: Supported Link Speeds Vector field bit 6All other encodings are Reserved.If a value is written to this field that does not correspond to a supported speed (as indicated by the Supported Link Speeds Vector), the result is undefined.If either of the Enter Compliance or Enter Modified Compliance bits are implemented, then this field must also be implemented.The default value of this field is the highest Link speed supported by the component (as reported in the Max Link Speed field of the Link Capabilities register) unless the corresponding platform/form factor requires a different default value.For both Upstream and Downstream Ports, this field is used to set the target compliance mode speed when software is using the Enter Compliance bit to force a Link into compliance mode.For Upstream Ports, if the Enter Compliance bit is Clear, this field is permitted to have no effect.For a Multi-Function Device associated with an Upstream Port, the field in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other Functions of that device, this field is of type RsvdP.Components that support only the 2.5 GT/s speed are permitted to hardwire this field to 0000b.For a description of this standard PCIe register field, see the PCI Express Base Specification. In M-PCIe mode, the contents of this field are derived from other registers.Note: This register field is sticky.30R/WPCIE_CAP_ENTER_COMPLIANCEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4542Enter Compliance. Software is permitted to force a Link to enter Compliance mode (at the speed indicated in the Target Link Speed field and the de-emphasis/preset level indicated by the Compliance Preset/De-emphasis field) by setting this bit to 1b in both components on a Link and then initiating a hot reset on the Link.Default value of this bit following Fundamental Reset is 0b.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other Functions of that device, this bit is of type RsvdP.Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.This bit is intended for debug, compliance testing purposes only. System firmware and software is allowed to modify this bit only during debug or compliance testing. In all other cases, the system must ensure that this bit is set to the default value.Note: This register field is sticky.440x0R/WPCIE_CAP_HW_AUTO_SPEED_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4567Hardware Autonomous Speed Disable. When set, this bit disables hardware from changing the Link speed for device-specific reasons other than attempting to correct unreliable Link operation by reducing Link speed. Initial transition to the highest supported common link speed is not blocked by this bit.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is of type RsvdP.Functions that do not implement the associated mechanism are permitted to hardwire this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.550x0R/WPCIE_CAP_SEL_DEEMPHASISPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4592Selectable De-emphasis. When the Link is operating at 5.0 GT/s speed, this bit is used to control the transmit de-emphasis of the link in specific situations. For more details, see section 4.2.6 of PCI Express Base Specification.Encodings: - 1b: -3.5 dB - 0b: -6 dBWhen the Link is not operating at 5.0 GT/s speed, the setting of this bit has no effect. Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.This bit is not applicable and Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.Note: This register field is sticky.660x0RPCIE_CAP_TX_MARGINPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4626Transmit Margin – This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate (see Chapter 4 of PCI Express Base Specification for details of how the Transmitter voltage level is determined in various states).Encodings: - 000b: Normal operating range - 001b-111b: As defined in Section 8.3.4 not all encodings are required to be implemented.For a Multi-Function Device associated with an Upstream Port, the field in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other Functions of that device, this field is of type RsvdP.For components that support only the 2.5 GT/s speed, the controller hardwires this bit to 000b.This field is intended for debug, compliance testing purposes only. System firmware and software is allowed to modify this field only during debug or compliance testing. In all other cases, the system must ensure that this field is set to the default value.Note: This register field is sticky.970x0R/WPCIE_CAP_ENTER_MODIFIED_COMPLIANCEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4653Enter Modified Compliance. When this bit is set to 1b, the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate.Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is of type RsvdP.This bit is intended for debug, compliance testing purposes only. System firmware and software is allowed to modify this bit only during debug or compliance testing. In all other cases, the system must ensure that this bit is set to the default value.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.10100x0R/WPCIE_CAP_COMPLIANCE_SOSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4680Compliance SOS. When set to 1b, the LTSSM is required to send SKP Ordered Sets between sequences when sending the Compliance Pattern or Modified Compliance Pattern.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other Functions of that device, this bit is of type RsvdP.This bit is applicable when the Link is operating at 2.5 GT/s or 5.0 GT/s data rates only.For components that support only the 2.5 GT/s speed, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.11110x0R/WPCIE_CAP_COMPLIANCE_PRESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4722Compliance Preset/De-emphasis.For 8.0 GT/s and higher Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The encodings are defined in section 4.2.3.2 of PCI Express Base Specification . Results are undefined if a reserved preset encoding is used when entering Polling.Compliance in this way.For 5.0 GT/s Data Rate: This field sets the de-emphasis level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b.Defined Encodings are: - 0001b: -3.5 dB - 0000b: -6 dBWhen the Link is operating at 2.5 GT/s, the setting of this field has no effect. Components that support only 2.5 GT/s speed are permitted to hardwire this field to 0000b.For a Multi-Function Device associated with an Upstream Port, the field in Function 0 is of type RWS, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this field is of type RsvdP.This field is intended for debug and compliance testing purposes. System firmware and software is allowed to modify this field only during debug or compliance testing. In all other cases, the system must ensure that this field is set to the default value.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.15120x0R/WPCIE_CAP_CURR_DEEMPHASISPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4748Current De-emphasis Level. When the Link is operating at 5.0 GT/s speed, this bit reflects the level of de-emphasis.Encodings: - 1b: -3.5 dB - 0b: -6 dBThe value in this bit is undefined when the Link is not operating at 5.0 GT/s speed.Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.For components that support speeds greater than 2.5 GT/s, Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions of the Port. In M-PCIe mode this register is always 0x0. In C-PCIe mode, its contents are derived by sampling the PIPE.16160x1RPCIE_CAP_EQ_CPLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4770Equalization 8.0 GT/s Complete. When set to 1b, this bit indicates that the Transmitter Equalization procedure at the 8.0 GT/s data rate has completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.Note: This register field is sticky.17170x0RPCIE_CAP_EQ_CPL_P1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4792Equalization 8.0 GT/s Phase 1 Successful. When set to 1b, this bit indicates that Phase 1 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.Note: This register field is sticky.18180x0RPCIE_CAP_EQ_CPL_P2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4814Equalization 8.0 GT/s Phase 2 Successful. When set to 1b, this bit indicates that Phase 2 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.Note: This register field is sticky.19190x0RPCIE_CAP_EQ_CPL_P3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4836EEqualization 8.0 GT/s Phase 3 Successful. When set to 1b, this bit indicates that Phase 3 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.Note: This register field is sticky.20200x0RPCIE_CAP_LINK_EQ_REQPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4854Link Equalization Request 8.0 GT/s. This bit is set by hardware to request the 8.0 GT/s Link equalization process to be performed on the Link. For more details, see sections 4.2.3 and 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.21210x0R/W1CPCIE_CAP_RETIMER_PRE_DETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4880Retimer Presence Detected. When set to 1b, this bit indicates that a Retimer was present during the most recent Link negotiation. For more details, see section 4.2.6.3.5.1 of PCI Express Base Specification.This bit is required for Ports that have the Retimer Presence Detect Supported bit of the Link Capabilities 2 register set to 1b.For Ports that have the Retimer Presence Detect Supported bit set to 0b, the controller hardwires this bit to 0b.For Multi-Function Devices associated with an Upstream Port, this bit must be implemented in Function 0 and is RsvdZ in all other Functions.Note: This register field is sticky.22220x0RPCIE_CAP_TWO_RETIMERS_PRE_DETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4906Two Retimers Presence Detected. When set to 1b, this bit indicates that two Retimers were present during the most recent Link negotiation. For more details, see section 4.2.6.3.5.1 of PCI Express Base Specification.This bit is required for Ports that have the Two Retimers Presence Detect Supported bit of the Link Capabilities 2 register set to 1b.Ports that have the Two Retimers Presence Detect Supported bit set to 0b are permitted to hardwire this bit to 0b.For Multi-Function Devices associated with an Upstream Port, this bit must be implemented in Function 0 and RsvdZ in all other Functions.Note: This register field is sticky.23230x0R--25240x0rRSVDP_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4914Reserved for future use.27260x0RDOWNSTREAM_COMPO_PRESENCEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4954Downstream Component Presence. This field indicates the presence and DRS status for the Downstream Component, if any, connected to the Link; defined values are: - 000b: Link Down – Presence Not Determined - 001b: Link Down – Component Not Present indicates the Downstream Port (DP) has determined that a Downstream Component is not present - 010b: Link Down – Component Present indicates the DP has determined that a Downstream Component is present, but the Data Link Layer is not active - 011b: Reserved - 100b: Link Up – Component Presentindicates the DP has determined that a Downstream Component is present, but no DRS Message has been received since the Data Link Layer became active - 101b: Link Up – Component Present and DRS Received indicates the DP has received a DRS Message since the Data Link Layer became active - 110b: Reserved - 111b: ReservedComponent Presence state must be determined by the logical "OR" of the Physical Layer in-band presence detect mechanism and, if present, any out-of-band presence detect mechanism implemented for the Link. If no out-of-band presence detect mechanism is implemented, then Component Presence state must be determined solely by the Physical Layer in-band presence detect mechanism.This field must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities 2 register.This field is RsvdZ for all other Functions.30280x0RDRS_MESSAGE_RECEIVEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4970DRS Message Received. This bit must be set whenever the Port receives a DRS Message.This bit must be cleared in DL_Down.This bit must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities 2 register.This bit is RsvdZ for all other Functions.31310x0RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAPPF0_MSIX_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr51740xB0R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_MSIX_CAPPF MSI-X Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP.PCI_MSIX_CAP_ID_NEXT_CTRL_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP.MSIX_TABLE_OFFSET_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP.MSIX_PBA_OFFSET_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP.PCI_MSIX_CAP_ID_NEXT_CTRL_REGPCI_MSIX_CAP_ID_NEXT_CTRL_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr50630x0R/W0x00800011PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REGMSI-X Capability ID, Next Pointer, Control Registers.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCI_MSIX_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr4991MSI-X Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x11RPCI_MSIX_CAP_NEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5007MSI-X Next Capability Pointer.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580x00RPCI_MSIX_TABLE_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5032MSI-X Table Size.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PCI_MSIX_TABLE_SIZE field in SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_TABLE_SIZE field in the PF PCI_MSIX_CAP_ID_NEXT_CTRL_REG register.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.26160x080RRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5040Reserved for future use.29270x0RPCI_MSIX_FUNCTION_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5053Function Mask.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30300x0R/WPCI_MSIX_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5062MSI-X Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP.MSIX_TABLE_OFFSET_REGMSIX_TABLE_OFFSET_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr51180x4R0x00000004PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REGMSI-X Table Offset and BIR Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCI_MSIX_BIRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5093MSI-X Table BAR Indicator Register Field.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table BAR Indicator Register" (PCI_MSIX_BIR field in SHADOW_MSIX_TABLE_OFFSET_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_BIR field in the PF MSIX_TABLE_OFFSET_REG register.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.200x4RPCI_MSIX_TABLE_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5117MSI-X Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Offset" (PCI_MSIX_TABLE_OFFSET field in SHADOW_MSIX_TABLE_OFFSET_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_TABLE_OFFSET field in the PF MSIX_TABLE_OFFSET_REG register.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.3130x00000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP.MSIX_PBA_OFFSET_REGMSIX_PBA_OFFSET_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr51730x8R0x00008004PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REGMSI-X PBA Offset and BIR Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCI_MSIX_PBA_BIRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5148MSI-X PBA BIR.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X PBA BIR" (PCI_MSIX_PBA_BIR field in SHADOW_MSIX_PBA_OFFSET_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_PBA_BIR field in the PF MSIX_PBA_OFFSET_REG register.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.200x4RPCI_MSIX_PBA_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5172MSI-X PBA Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X PBA Offset" (PCI_MSIX_PBA_OFFSET field in SHADOW_MSIX_PBA_OFFSET_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_PBA_OFFSET field in the PF MSIX_PBA_OFFSET_REG register.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.3130x00001000RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAPPF0_AER_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr65950x100R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAPPF Advanced Error Reporting Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.AER_EXT_CAP_HDR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.UNCORR_ERR_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.UNCORR_ERR_MASK_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.UNCORR_ERR_SEV_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.CORR_ERR_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.CORR_ERR_MASK_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.ADV_ERR_CAP_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.HDR_LOG_0_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.HDR_LOG_1_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.HDR_LOG_2_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.HDR_LOG_3_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_1_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_2_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_3_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_4_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.AER_EXT_CAP_HDR_OFFAER_EXT_CAP_HDR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr52330x0R0x14820001PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_AER_EXT_CAP_HDR_OFFAdvanced Error Reporting Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5200AER Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0001RCAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5216Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x2RNEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5232Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x148RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.UNCORR_ERR_STATUS_OFFUNCORR_ERR_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr54090x4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_UNCORR_ERR_STATUS_OFFUncorrectable Error Status Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5246Reserved for future use.300x0RDL_PROTOCOL_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5256Data Link Protocol Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.44R/W1CSURPRISE_DOWN_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5266Surprise Down Error Status (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.55R/W1CRSVDP_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5274Reserved for future use.1160x00RPOIS_TLP_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5285Poisoned TLP Status.For a description of this standard PCIe register field, see the PCI Express Specification.12120x0R/W1CFC_PROTOCOL_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5295Flow Control Protocol Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.1313R/W1CCMPLT_TIMEOUT_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5306Completion Timeout Status.For a description of this standard PCIe register field, see the PCI Express Specification.14140x0R/W1CCMPLT_ABORT_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5317Completer Abort Status.For a description of this standard PCIe register field, see the PCI Express Specification.15150x0R/W1CUNEXP_CMPLT_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5328Unexpected Completion Status.For a description of this standard PCIe register field, see the PCI Express Specification.16160x0R/W1CREC_OVERFLOW_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5338Receiver Overflow Status.For a description of this standard PCIe register field, see the PCI Express Specification.1717R/W1CMALF_TLP_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5348Malformed TLP Status.For a description of this standard PCIe register field, see the PCI Express Specification.1818R/W1CECRC_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5362ECRC Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.Note:If CX_ECRC_ENABLE=0 the register field always reads 0.19190x0R/W1CUNSUPPORTED_REQ_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5373Unsupported Request Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.20200x0R/W1C--21210x0rINTERNAL_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5392Uncorrectable Internal Error Status.For a description of this standard PCIe register field, see the PCI Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when it detects internal uncorrectable internal errors such as parity and ECC failures. You should use the outputs from these errors to drive the app_err_bus[9] input. For more details, see the "Data Integrity (Wire, Datapath, and RAM Protection)" section in the Databook.22220x0R/W1CRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5400Reserved for future use.23230x0R--26240x0rRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5408Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.UNCORR_ERR_MASK_OFFUNCORR_ERR_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr56180x8R/W0x00400000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_UNCORR_ERR_MASK_OFFUncorrectable Error Mask Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5422Reserved for future use.300x0RDL_PROTOCOL_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5433Data Link Protocol Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.440x0R/WSURPRISE_DOWN_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5445Surprise Down Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.550x0RRSVDP_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5453Reserved for future use.1160x00RPOIS_TLP_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5464Poisoned TLP Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.12120x0R/WFC_PROTOCOL_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5475Flow Control Protocol Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.13130x0R/WCMPLT_TIMEOUT_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5486Completion Timeout Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.14140x0R/WCMPLT_ABORT_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5497Completer Abort Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.15150x0R/WUNEXP_CMPLT_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5508Unexpected Completion Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.16160x0R/WREC_OVERFLOW_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5519Receiver Overflow Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.17170x0R/WMALF_TLP_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5530Malformed TLP Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.18180x0R/WECRC_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5544ECRC Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.19190x0R/WUNSUPPORTED_REQ_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5555Unsupported Request Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.20200x0R/WACS_VIOLATION_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5578ACS Violation Mask.Setting the ACS Violation Mask bit disables error logging and signaling for ACS Violation errors.The bit is Read-Only Zero for upstream ports, when ACS P2P Egress Control Enable is not set.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: if (acs_viol_svrity_mask_wr_en == 1) then R/W (Sticky) else R(Sticky) - Dbi: if (acs_viol_svrity_mask_wr_en == 1) then R/W (Sticky) else R(Sticky) Note: This register field is sticky.21210x0RINTERNAL_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5589Uncorrectable Internal Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.22220x1R/WRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5597Reserved for future use.23230x0RATOMIC_EGRESS_BLOCKED_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5609AtomicOp Egress Block Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.24240x0R--26250x0rRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5617Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.UNCORR_ERR_SEV_OFFUNCORR_ERR_SEV_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr58070xCR/W0x00462030PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_UNCORR_ERR_SEV_OFFUncorrectable Error Severity Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5631Reserved for future use.300x0RDL_PROTOCOL_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5642Data Link Protocol Error Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.440x1R/WSURPRISE_DOWN_ERR_SVRITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5654Surprise Down Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.550x1RRSVDP_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5662Reserved for future use.1160x00RPOIS_TLP_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5673Poisoned TLP Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.12120x0R/WFC_PROTOCOL_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5684Flow Control Protocol Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.13130x1R/WCMPLT_TIMEOUT_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5695Completion Timeout Error Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.14140x0R/WCMPLT_ABORT_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5706Completer Abort Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.15150x0R/WUNEXP_CMPLT_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5717Unexpected Completion Error Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.16160x0R/WREC_OVERFLOW_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5728Receiver Overflow Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.17170x1R/WMALF_TLP_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5739Malformed TLP Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.18180x1R/WECRC_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5753ECRC Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.19190x0R/WUNSUPPORTED_REQ_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5764Unsupported Request Error Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.20200x0R/W--21210x0rINTERNAL_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5775Uncorrectable Internal Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.22220x1R/WRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5783Reserved for future use.23230x0RATOMIC_EGRESS_BLOCKED_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5798AtomicOp Egress Blocked Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.24240x0R--26250x0rRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5806Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.CORR_ERR_STATUS_OFFCORR_ERR_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr59250x10R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_CORR_ERR_STATUS_OFFCorrectable Error Status Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRX_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5823Receiver Error Status (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.000x0R/W1CRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5831Reserved for future use.510x00RBAD_TLP_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5842Bad TLP Status.For a description of this standard PCIe register field, see the PCI Express Specification.660x0R/W1CBAD_DLLP_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5853Bad DLLP Status.For a description of this standard PCIe register field, see the PCI Express Specification.770x0R/W1CREPLAY_NO_ROLEOVER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5864REPLAY_NUM Rollover Status.For a description of this standard PCIe register field, see the PCI Express Specification.880x0R/W1CRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5872Reserved for future use.1190x0RRPL_TIMER_TIMEOUT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5883Replay Timer Timeout Status.For a description of this standard PCIe register field, see the PCI Express Specification.12120x0R/W1CADVISORY_NON_FATAL_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5894Advisory Non-Fatal Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.13130x0R/W1CCORRECTED_INT_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5905Corrected Internal Error Status (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.14140x0R/W1CHEADER_LOG_OVERFLOW_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5916Header Log Overflow Error Status (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.15150x0R/W1CRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5924Reserved for future use.31160x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.CORR_ERR_MASK_OFFCORR_ERR_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr60430x14R/W0x0000e000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_CORR_ERR_MASK_OFFCorrectable Error Mask Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRX_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5941Receiver Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5949Reserved for future use.510x00RBAD_TLP_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5960Bad TLP Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.660x0R/WBAD_DLLP_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5971Bad DLLP Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.770x0R/WREPLAY_NO_ROLEOVER_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5982REPLAY_NUM Rollover Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5990Reserved for future use.1190x0RRPL_TIMER_TIMEOUT_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6001Replay Timer Timeout Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.12120x0R/WADVISORY_NON_FATAL_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6012Advisory Non-Fatal Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.13130x1R/WCORRECTED_INT_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6023Corrected Internal Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.14140x1R/WHEADER_LOG_OVERFLOW_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6034Header Log Overflow Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.15150x1R/WRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6042Reserved for future use.31160x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.ADV_ERR_CAP_CTRL_OFFADV_ERR_CAP_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr61540x18R/W0x000000a0PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFFAdvanced Error Capabilities and Control Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseFIRST_ERR_POINTERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6062First Error Pointer.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.400x00RECRC_GEN_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6074ECRC Generation Capable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.550x1RECRC_GEN_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6085ECRC Generation Enable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.660x0R/WECRC_CHECK_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6097ECRC Check Capable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.770x1RECRC_CHECK_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6108ECRC Check Enable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.880x0R/WMULTIPLE_HEADER_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6120Multiple Header Recording Capable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.990x0RMULTIPLE_HEADER_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6135Multiple Header Recording Enable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.10100x0R--11110x0rCTO_PRFX_HDR_LOG_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6145TLP Prefix Log Present.For a description of this standard PCIe register field, see the PCI Express Specification.12120x0RRSVDP_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6153Reserved for future use.31130x00000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.HDR_LOG_0_OFFHDR_LOG_0_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr62130x1CR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_HDR_LOG_0_OFFHeader Log Register 0.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseFIRST_DWORD_FIRST_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6173Byte 0 of Header log register of First 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RFIRST_DWORD_SECOND_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6186Byte 1 of Header log register of First 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RFIRST_DWORD_THIRD_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6199Byte 2 of Header log register of First 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RFIRST_DWORD_FOURTH_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6212Byte 3 of Header log register of First 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.HDR_LOG_1_OFFHDR_LOG_1_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr62720x20R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_HDR_LOG_1_OFFHeader Log Register 1.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseSECOND_DWORD_FIRST_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6232Byte 0 of Header log register of Second 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RSECOND_DWORD_SECOND_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6245Byte 1 of Header log register of Second 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RSECOND_DWORD_THIRD_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6258Byte 2 of Header log register of Second 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RSECOND_DWORD_FOURTH_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6271Byte 3 of Header log register of Second 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.HDR_LOG_2_OFFHDR_LOG_2_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr63310x24R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_HDR_LOG_2_OFFHeader Log Register 2.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseTHIRD_DWORD_FIRST_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6291Byte 0 of Header log register of Third 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RTHIRD_DWORD_SECOND_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6304Byte 1 of Header log register of Third 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RTHIRD_DWORD_THIRD_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6317Byte 2 of Header log register of Third 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RTHIRD_DWORD_FOURTH_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6330Byte 3 of Header log register of Third 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.HDR_LOG_3_OFFHDR_LOG_3_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr63900x28R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_HDR_LOG_3_OFFHeader Log Register 3.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseFOURTH_DWORD_FIRST_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6350Byte 0 of Header log register of Fourth 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RFOURTH_DWORD_SECOND_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6363Byte 1 of Header log register of Fourth 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RFOURTH_DWORD_THIRD_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6376Byte 2 of Header log register of Fourth 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RFOURTH_DWORD_FOURTH_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6389Byte 3 of Header log register of Fourth 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_1_OFFTLP_PREFIX_LOG_1_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr64410x38R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFFTLP Prefix Log Register 1.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCFG_TLP_PFX_LOG_1_FIRST_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6407Byte 0 of Error TLP Prefix Log 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RCFG_TLP_PFX_LOG_1_SECOND_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6418Byte 1 of Error TLP Prefix Log 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RCFG_TLP_PFX_LOG_1_THIRD_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6429Byte 2 of Error TLP Prefix Log 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RCFG_TLP_PFX_LOG_1_FOURTH_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6440Byte 3 of Error TLP Prefix Log 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_2_OFFTLP_PREFIX_LOG_2_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr64920x3CR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFFTLP Prefix Log Register 2.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCFG_TLP_PFX_LOG_2_FIRST_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6458Byte 0 Error TLP Prefix Log 2.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RCFG_TLP_PFX_LOG_2_SECOND_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6469Byte 1 Error TLP Prefix Log 2.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RCFG_TLP_PFX_LOG_2_THIRD_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6480Byte 2 Error TLP Prefix Log 2.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RCFG_TLP_PFX_LOG_2_FOURTH_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6491Byte 3 Error TLP Prefix Log 2.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_3_OFFTLP_PREFIX_LOG_3_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr65430x40R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFFTLP Prefix Log Register 3.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCFG_TLP_PFX_LOG_3_FIRST_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6509Byte 0 Error TLP Prefix Log 3.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RCFG_TLP_PFX_LOG_3_SECOND_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6520Byte 1 Error TLP Prefix Log 3.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RCFG_TLP_PFX_LOG_3_THIRD_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6531Byte 2 Error TLP Prefix Log 3.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RCFG_TLP_PFX_LOG_3_FOURTH_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6542Byte 3 Error TLP Prefix Log 3.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_4_OFFTLP_PREFIX_LOG_4_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr65940x44R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFFTLP Prefix Log Register 4.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCFG_TLP_PFX_LOG_4_FIRST_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6560Byte 0 Error TLP Prefix Log 4.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RCFG_TLP_PFX_LOG_4_SECOND_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6571Byte 1 Error TLP Prefix Log 4.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RCFG_TLP_PFX_LOG_4_THIRD_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6582Byte 2 Error TLP Prefix Log 4.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RCFG_TLP_PFX_LOG_4_FOURTH_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6593Byte 3 Error TLP Prefix Log 4.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAPPF0_VC_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr75870x148R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAPVirtual Channel Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.VC_BASEregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.VC_STATUS_CONTROL_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.VC_BASEVC_BASEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr66540x0R0x19810002PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_VC_BASEVC Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PCIE_EXTENDED_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6621VC Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0002RVC_CAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6637Capability Version.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RVC_NEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6653Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x198RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_1VC_CAPABILITIES_REG_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr67240x4R0x00000003PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_VC_CAPABILITIES_REG_1Port VC Capability Register 1.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_EXT_VC_CNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6669Extended VC Count.For a description of this standard PCIe register field, see the PCI Express Base Specification.200x3RRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6676Reserved for future use.330x0RVC_LOW_PRI_EXT_VC_CNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6691Low Priority Extended VC Count.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.640x0RRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6698Reserved for future use.770x0RVC_REFERENCE_CLOCKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6707Reference Clock.For a description of this standard PCIe register field, see the PCI Express Base Specification.980x0RVC_PORT_ARBI_TBL_ENTRY_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6716Port Arbitration Table Entry Size.For a description of this standard PCIe register field, see the PCI Express Base Specification.11100x0RRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6723Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_2VC_CAPABILITIES_REG_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr67620x8R0x00000001PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_VC_CAPABILITIES_REG_2Port VC Capability Register 2.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_ARBI_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6745VC Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.300x1RRSVDP_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6752Reserved for future use.2340x00000RVC_ARBI_TABLE_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6761VC Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.VC_STATUS_CONTROL_REGVC_STATUS_CONTROL_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr68130xCR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_VC_STATUS_CONTROL_REGPort VC Control and Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_LOAD_VC_ARBI_TABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6777Requests Hardware to Load VC Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x0RVC_ARBI_SELECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6786VC Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.310x0R/WRSVDP_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6794Reserved for future use.1540x000RVC_ARBI_TABLE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6804VC Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RRSVDP_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6812Reserved for future use.31170x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC0RESOURCE_CAP_REG_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr68780x10R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_CAP_REG_VC0VC Resource Capability Register (0).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PORT_ARBI_CAP_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6828Port Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x00RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6835Reserved for future use.1480x00RVC_REJECT_SNOOP_TRANS_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6848Reject Snoop Transactions.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 15150x0RVC_MAX_TIME_SLOT_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6861Maximum Time Slots-1 supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 21160x00RRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6868Reserved for future use.23220x0RVC_PORT_ARBI_TABLE_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6877Port Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC0RESOURCE_CON_REG_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr69670x14R/W0x800000ffPE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_CON_REG_VC0VC Resource Control Register (0).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_TC_MAP_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6893Bit 0 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x1RVC_TC_MAP_VC0_BIT1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6902Bits 7:1 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.710x7fR/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6910Reserved for future use.1580x00RVC_LOAD_PORT_ARBI_TABLE_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6920Load Port Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0WVC_PORT_ARBI_SELECT_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6930Port Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.17170x0RRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6938Reserved for future use.23180x00RVC_ID_VCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6948VC ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.26240x0RRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6956Reserved for future use.30270x0RVC_ENABLE_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6966VC Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x1RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC0RESOURCE_STATUS_REG_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr70070x18R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0VC Resource Status Register (0).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6980Reserved for future use.1500x0000RVC_PORT_ARBI_TABLE_STATUS_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6989Port Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RVC_NEGO_PENDING_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6999VC Negotiation Pending.For a description of this standard PCIe register field, see the PCI Express Base Specification.1717RRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7006Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC1RESOURCE_CAP_REG_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr70720x1CR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_CAP_REG_VC1VC Resource Capability Register (1).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PORT_ARBI_CAP_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7022VC1 Port Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x00RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7029Reserved for future use.1480x00RVC_REJECT_SNOOP_TRANS_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7042VC1 Reject Snoop Transactions.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 15150x0RVC_MAX_TIME_SLOT_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7055VC1 Maximum Time Slots-1 supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 21160x00RRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7062Reserved for future use.23220x0RVC_PORT_ARBI_TABLE_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7071VC1 Port Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC1RESOURCE_CON_REG_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr71600x20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_CON_REG_VC1VC Resource Control Register (1).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_TC_MAP_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7087VC1 Bit 0 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x0RVC_TC_MAP_VC1_BIT1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7096VC1 Bits 7:1 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.710x00R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7104Reserved for future use.1580x00RVC_LOAD_PORT_ARBI_TABLE_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7114VC1 Load Port Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0WVC_PORT_ARBI_SELECT_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7124VC1 Port Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.19170x0RRSVDP_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7132Reserved for future use.23200x0RVC_ID_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7142VC1 VC ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.26240x0R/WRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7150Reserved for future use.30270x0RVC_ENABLE_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7159VC1 VC Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC1RESOURCE_STATUS_REG_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr72000x24R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1VC Resource Status Register (1).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7173Reserved for future use.1500x0000RVC_PORT_ARBI_TABLE_STATUS_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7182VC1 Port Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RVC_NEGO_PENDING_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7192VC1 VC Negotiation Pending.For a description of this standard PCIe register field, see the PCI Express Base Specification.1717RRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7199Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC2RESOURCE_CAP_REG_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr72650x28R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_CAP_REG_VC2VC Resource Capability Register (2).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PORT_ARBI_CAP_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7215VC2 Port Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x00RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7222Reserved for future use.1480x00RVC_REJECT_SNOOP_TRANS_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7235VC2 Reject Snoop Transactions.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 15150x0RVC_MAX_TIME_SLOT_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7248VC2 Maximum Time Slots-1 supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 21160x00RRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7255Reserved for future use.23220x0RVC_PORT_ARBI_TABLE_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7264VC2 Port Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC2RESOURCE_CON_REG_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr73530x2CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_CON_REG_VC2VC Resource Control Register (2).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_TC_MAP_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7280VC2 Bit 0 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x0RVC_TC_MAP_VC2_BIT1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7289VC2 Bits 7:1 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.710x00R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7297Reserved for future use.1580x00RVC_LOAD_PORT_ARBI_TABLE_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7307VC2 Load Port Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0WVC_PORT_ARBI_SELECT_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7317VC2 Port Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.19170x0RRSVDP_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7325Reserved for future use.23200x0RVC_ID_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7335VC2 VC ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.26240x0R/WRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7343Reserved for future use.30270x0RVC_ENABLE_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7352VC2 VC Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC2RESOURCE_STATUS_REG_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr73930x30R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2VC Resource Status Register (2).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7366Reserved for future use.1500x0000RVC_PORT_ARBI_TABLE_STATUS_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7375VC2 Port Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RVC_NEGO_PENDING_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7385VC2 VC Negotiation Pending.For a description of this standard PCIe register field, see the PCI Express Base Specification.1717RRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7392Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC3RESOURCE_CAP_REG_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr74580x34R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_CAP_REG_VC3VC Resource Capability Register (3).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PORT_ARBI_CAP_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7408VC3 Port Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x00RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7415Reserved for future use.1480x00RVC_REJECT_SNOOP_TRANS_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7428VC3 Reject Snoop Transactions.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 15150x0RVC_MAX_TIME_SLOT_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7441VC3 Maximum Time Slots-1 supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 21160x00RRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7448Reserved for future use.23220x0RVC_PORT_ARBI_TABLE_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7457VC3 Port Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC3RESOURCE_CON_REG_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr75460x38R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_CON_REG_VC3VC Resource Control Register (3).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_TC_MAP_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7473VC3 Bit 0 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x0RVC_TC_MAP_VC3_BIT1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7482VC3 Bits 7:1 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.710x00R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7490Reserved for future use.1580x00RVC_LOAD_PORT_ARBI_TABLE_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7500VC3 Load Port Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0WVC_PORT_ARBI_SELECT_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7510VC3 Port Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.19170x0RRSVDP_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7518Reserved for future use.23200x0RVC_ID_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7528VC3 VC ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.26240x0R/WRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7536Reserved for future use.30270x0RVC_ENABLE_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7545VC3 VC Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC3RESOURCE_STATUS_REG_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr75860x3CR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3VC Resource Status Register (3).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7559Reserved for future use.1500x0000RVC_PORT_ARBI_TABLE_STATUS_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7568VC3 Port Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RVC_NEGO_PENDING_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7578VC3 VC Negotiation Pending.For a description of this standard PCIe register field, see the PCI Express Base Specification.1717RRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7585Reserved for future use.31180x0000RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAPPF0_SPCIE_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr82840x198R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_SPCIE_CAPSecondary PCI Express Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_HEADER_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.LINK_CONTROL3_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.LANE_ERR_STATUS_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_0CH_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_10H_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_14H_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_18H_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_HEADER_REGSPCIE_CAP_HEADER_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr76460x0R0x1b810019PE0_DWC_pcie_ctl_AXI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REGSPCIE Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseEXTENDED_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7613Secondary PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0019RCAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7629Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7645Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x1b8RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.LINK_CONTROL3_REGLINK_CONTROL3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr76870x4R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_SPCIE_CAP_LINK_CONTROL3_REGLink Control 3 Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalsePERFORM_EQPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7666Perform Equalization.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: RSVDP 00REQ_REQ_INT_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7679Link Equalization Request Interrupt Enable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: RSVDP 110x0RRSVDP_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7686Reserved for future use.3120x00000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.LANE_ERR_STATUS_REGLANE_ERR_STATUS_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr77120x8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_SPCIE_CAP_LANE_ERR_STATUS_REGLane Error Status Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseLANE_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7703Lane Error Status Bits per Lane.For a description of this standard PCIe register field, see the PCI Express Specification.700x00R/W1CRSVDP_LANE_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7711Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_0CH_REGSPCIE_CAP_OFF_0CH_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr78510xCR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REGLane Equalization Control Register for lanes 1 and 0.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseDSP_TX_PRESET0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7728Downstream Port 8.0 GT/s Transmitter Preset 0.For a description of this standard PCIe register field, see the PCI Express Specification.300x0RDSP_RX_PRESET_HINT0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7738Downstream Port 8.0 GT/s Receiver Preset Hint 0.For a description of this standard PCIe register field, see the PCI Express Specification.640x0RRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7745Reserved for future use.770x0RUSP_TX_PRESET0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7761Upstream Port 8.0 GT/s Transmitter Preset 0.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.118RUSP_RX_PRESET_HINT0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7777Upstream Port 8.0 GT/s Receiver Preset Hint 0.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1412RRSVDP_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7784Reserved for future use.15150x0RDSP_TX_PRESET1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7794Downstream Port 8.0 GT/s Transmitter Preset 1.For a description of this standard PCIe register field, see the PCI Express Specification.19160x0RDSP_RX_PRESET_HINT1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7804Downstream Port 8.0 GT/s Receiver Preset Hint 1.For a description of this standard PCIe register field, see the PCI Express Specification.22200x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7811Reserved for future use.23230x0RUSP_TX_PRESET1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7827Upstream Port 8.0 GT/s Transmitter Preset 1.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.2724RUSP_RX_PRESET_HINT1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7843Upstream Port 8.0 GT/s Receiver Preset Hint 1.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.3028RRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7850Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_10H_REGSPCIE_CAP_OFF_10H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr79950x10R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REGLane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #2.The function of this register is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_NL. - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseDSP_TX_PRESET2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7872Downstream Port 8.0 GT/s Transmitter Preset2.For a description of this standard PCIe register, see the PCI Express Specification.300x0RDSP_RX_PRESET_HINT2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7882Downstream Port 8.0 GT/s Receiver Preset Hint2.For a description of this standard PCIe register, see the PCI Express Specification.640x0RRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7889Reserved for future use.770x0RUSP_TX_PRESET2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7905Upstream Port 8.0 GT/s Transmitter Preset2.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.118RUSP_RX_PRESET_HINT2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7921Upstream Port 8.0 GT/s Receiver Preset Hint2.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.1412RRSVDP_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7928Reserved for future use.15150x0RDSP_TX_PRESET3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7938Downstream Port 8.0 GT/s Transmitter Preset3.For a description of this standard PCIe register, see the PCI Express Specification.19160x0RDSP_RX_PRESET_HINT3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7948Downstream Port 8.0 GT/s Receiver Preset Hint3.For a description of this standard PCIe register, see the PCI Express Specification.22200x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7955Reserved for future use.23230x0RUSP_TX_PRESET3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7971Upstream Port 8.0 GT/s Transmitter Preset3.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.2724RUSP_RX_PRESET_HINT3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7987Upstream Port 8.0 GT/s Receiver Preset Hint3.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.3028RRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_SETDWC_pcie_dbi_cpcie_usp_4x8.csr7994Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_14H_REGSPCIE_CAP_OFF_14H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr81390x14R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REGLane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #4.The function of this register is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_NL. - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseDSP_TX_PRESET4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8016Downstream Port 8.0 GT/s Transmitter Preset4.For a description of this standard PCIe register, see the PCI Express Specification.300x0RDSP_RX_PRESET_HINT4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8026Downstream Port 8.0 GT/s Receiver Preset Hint4.For a description of this standard PCIe register, see the PCI Express Specification.640x0RRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8033Reserved for future use.770x0RUSP_TX_PRESET4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8049Upstream Port 8.0 GT/s Transmitter Preset4.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.118RUSP_RX_PRESET_HINT4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8065Upstream Port 8.0 GT/s Receiver Preset Hint4.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.1412RRSVDP_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8072Reserved for future use.15150x0RDSP_TX_PRESET5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8082Downstream Port 8.0 GT/s Transmitter Preset5.For a description of this standard PCIe register, see the PCI Express Specification.19160x0RDSP_RX_PRESET_HINT5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8092Downstream Port 8.0 GT/s Receiver Preset Hint5.For a description of this standard PCIe register, see the PCI Express Specification.22200x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8099Reserved for future use.23230x0RUSP_TX_PRESET5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8115Upstream Port 8.0 GT/s Transmitter Preset5.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.2724RUSP_RX_PRESET_HINT5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8131Upstream Port 8.0 GT/s Receiver Preset Hint5.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.3028RRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8138Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_18H_REGSPCIE_CAP_OFF_18H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr82830x18R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REGLane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #6.The function of this register is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_NL. - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseDSP_TX_PRESET6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8160Downstream Port 8.0 GT/s Transmitter Preset6.For a description of this standard PCIe register, see the PCI Express Specification.300x0RDSP_RX_PRESET_HINT6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8170Downstream Port 8.0 GT/s Receiver Preset Hint6.For a description of this standard PCIe register, see the PCI Express Specification.640x0RRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8177Reserved for future use.770x0RUSP_TX_PRESET6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8193Upstream Port 8.0 GT/s Transmitter Preset6.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.118RUSP_RX_PRESET_HINT6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8209Upstream Port 8.0 GT/s Receiver Preset Hint6.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.1412RRSVDP_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8216Reserved for future use.15150x0RDSP_TX_PRESET7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8226Downstream Port 8.0 GT/s Transmitter Preset7.For a description of this standard PCIe register, see the PCI Express Specification.19160x0RDSP_RX_PRESET_HINT7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8236Downstream Port 8.0 GT/s Receiver Preset Hint7.For a description of this standard PCIe register, see the PCI Express Specification.22200x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8243Reserved for future use.23230x0RUSP_TX_PRESET7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8259Upstream Port 8.0 GT/s Transmitter Preset7.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.2724RUSP_RX_PRESET_HINT7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8275Upstream Port 8.0 GT/s Receiver Preset Hint7.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.3028RRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8282Reserved for future use.31310x0RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAPPF0_PL16G_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr87030x1B8R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAPPhysical Layer 16.0 GT/s Extended Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_EXT_CAP_HDR_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_CAPABILITY_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_CONTROL_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_STATUS_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_LC_DPAR_STATUS_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_FIRST_RETIMER_DPAR_STATUS_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_SECOND_RETIMER_DPAR_STATUS_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_20H_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_24H_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_EXT_CAP_HDR_REGPL16G_EXT_CAP_HDR_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr83430x0R0x1e010026PE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REGPhysical Layer 16.0 GT/s Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseEXTENDED_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8310PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0026RCAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8326Capability Version.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8342Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x1e0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_CAPABILITY_REGPL16G_CAPABILITY_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr83570x4R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_CAPABILITY_REG16.0 GT/s Capabilities Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8356Reserved for future use.3100x00000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_CONTROL_REGPL16G_CONTROL_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr83710x8R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_CONTROL_REG16.0 GT/s Control Register .For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8370Reserved for future use.3100x00000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_STATUS_REGPL16G_STATUS_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr84520xCR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_STATUS_REG16.0 GT/s Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseEQ_16G_CPLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8390Equalization 16.0GT/s Complete.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: This register field is sticky.000x0REQ_16G_CPL_P1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8404Equalization 16.0GT/s Phase 1 Successful.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: This register field is sticky.110x0REQ_16G_CPL_P2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8418Equalization 16.0GT/s Phase 2 Successful.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: This register field is sticky.220x0REQ_16G_CPL_P3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8432Equalization 16.0GT/s Phase 3 Successful.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: This register field is sticky.330x0RLINK_EQ_16G_REQPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8443Link Equalization Request 16.0GT/s.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.440x0R/W1CRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8451Reserved for future use.3150x0000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_LC_DPAR_STATUS_REGPL16G_LC_DPAR_STATUS_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr84770x10R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG16.0 GT/s Local Data Parity Mismatch Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseLC_DPAR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8468Local Data Parity Mismatch Status.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.700x00R/W1CRSVDP_LC_DPAR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8476Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_FIRST_RETIMER_DPAR_STATUS_REGPL16G_FIRST_RETIMER_DPAR_STATUS_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr85020x14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG16.0 GT/s First Retimer Data Parity Mismatch Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseFIRST_RETIMER_DPAR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8493First Retimer Data Parity Mismatch Status.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.700x00R/W1CRSVDP_FIRST_RETIMER_DPAR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8501Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_SECOND_RETIMER_DPAR_STATUS_REGPL16G_SECOND_RETIMER_DPAR_STATUS_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr85280x18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG16.0 GT/s Second Retimer Data Parity Mismatch Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseSECOND_RETIMER_DPAR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8519Second Retimer Data Parity Mismatch Status .For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.700x00R/W1CRSVDP_SECOND_RETIMER_DPAR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8527Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_20H_REGPL16G_CAP_OFF_20H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr86150x20R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG16.0 GT/s Lane Equalization Control Register for Lane 0-3.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseDSP_16G_TX_PRESET0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8544Downstream Port 16.0 GT/s Transmitter Preset0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.300x0RUSP_16G_TX_PRESET0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8554Upstream Port 16.0 GT/s Transmitter Preset0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.740x0RDSP_16G_TX_PRESET1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8564Downstream Port 16.0 GT/s Transmitter Preset1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1180x0RUSP_16G_TX_PRESET1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8574Upstream Port 16.0 GT/s Transmitter Preset1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.15120x0RDSP_16G_TX_PRESET2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8584Downstream Port 16.0 GT/s Transmitter Preset2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.19160x0RUSP_16G_TX_PRESET2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8594Upstream Port 16.0 GT/s Transmitter Preset2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.23200x0RDSP_16G_TX_PRESET3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8604Downstream Port 16.0 GT/s Transmitter Preset3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.27240x0RUSP_16G_TX_PRESET3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8614Upstream Port 16.0 GT/s Transmitter Preset3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31280x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_24H_REGPL16G_CAP_OFF_24H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr87020x24R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG16.0 GT/s Lane Equalization Control Register for Lane 4-7.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseDSP_16G_TX_PRESET4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8631Downstream Port 16.0 GT/s Transmitter Preset4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.300x0RUSP_16G_TX_PRESET4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8641Upstream Port 16.0 GT/s Transmitter Preset4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.740x0RDSP_16G_TX_PRESET5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8651Downstream Port 16.0 GT/s Transmitter Preset5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1180x0RUSP_16G_TX_PRESET5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8661Upstream Port 16.0 GT/s Transmitter Preset5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.15120x0RDSP_16G_TX_PRESET6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8671Downstream Port 16.0 GT/s Transmitter Preset6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.19160x0RUSP_16G_TX_PRESET6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8681Upstream Port 16.0 GT/s Transmitter Preset6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.23200x0RDSP_16G_TX_PRESET7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8691Downstream Port 16.0 GT/s Transmitter Preset7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.27240x0RUSP_16G_TX_PRESET7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8701Upstream Port 16.0 GT/s Transmitter Preset7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31280x0RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAPPF0_MARGIN_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr96920x1E0R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAPMargining Extended Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_EXT_CAP_HDR_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_PORT_CAPABILITIES_STATUS_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS0_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS1_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS3_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS4_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS5_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS6_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS7_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_EXT_CAP_HDR_REGMARGIN_EXT_CAP_HDR_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr87620x0R0x20810027PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REGMargining Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseEXTENDED_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8729PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0027RCAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8745Capability Version.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8761Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x208RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_PORT_CAPABILITIES_STATUS_REGMARGIN_PORT_CAPABILITIES_STATUS_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr88190x4R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REGMargining Port Capabilities and Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseMARGINING_USES_DRIVER_SOFTWAREPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8784Margining uses Driver Software.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.000x0RRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8791Reserved for future use.1510x0000RMARGINING_READYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8801Margining Ready.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.1616RMARGINING_SOFTWARE_READYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8811Margining Software Ready.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.1717RRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8818Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS0_REGMARGIN_LANE_CNTRL_STATUS0_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr89280x8R/W0x00009c38PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REGMargining Lane Control and Status Register for Lane 0.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8833Receiver Number for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8843Margin Type for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8853Usage Model for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8861Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8871Margin Payload for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8883Receiver Number(Status) for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8895Margin Type(Status) for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8907Usage Model(Status) for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8915Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8927Margin Payload(Status) for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS1_REGMARGIN_LANE_CNTRL_STATUS1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr90370xCR/W0x00009c38PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REGMargining Lane Control and Status Register for Lane 1.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8942Receiver Number for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8952Margin Type for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8962Usage Model for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8970Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8980Margin Payload for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr8992Receiver Number(Status) for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9004Margin Type(Status) for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9016Usage Model(Status) for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9024Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9036Margin Payload(Status) for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS2_REGMARGIN_LANE_CNTRL_STATUS2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr91460x10R/W0x00009c38PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REGMargining Lane Control and Status Register for Lane 2.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9051Receiver Number for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9061Margin Type for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9071Usage Model for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9079Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9089Margin Payload for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9101Receiver Number(Status) for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9113Margin Type(Status) for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9125Usage Model(Status) for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9133Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9145Margin Payload(Status) for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS3_REGMARGIN_LANE_CNTRL_STATUS3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr92550x14R/W0x00009c38PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REGMargining Lane Control and Status Register for Lane 3.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9160Receiver Number for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9170Margin Type for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9180Usage Model for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9188Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9198Margin Payload for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9210Receiver Number(Status) for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9222Margin Type(Status) for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9234Usage Model(Status) for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9242Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9254Margin Payload(Status) for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS4_REGMARGIN_LANE_CNTRL_STATUS4_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr93640x18R/W0x00009c38PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REGMargining Lane Control and Status Register for Lane 4.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9269Receiver Number for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9279Margin Type for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9289Usage Model for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9297Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9307Margin Payload for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9319Receiver Number(Status) for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9331Margin Type(Status) for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9343Usage Model(Status) for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9351Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9363Margin Payload(Status) for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS5_REGMARGIN_LANE_CNTRL_STATUS5_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr94730x1CR/W0x00009c38PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REGMargining Lane Control and Status Register for Lane 5.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9378Receiver Number for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9388Margin Type for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9398Usage Model for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9406Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9416Margin Payload for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9428Receiver Number(Status) for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9440Margin Type(Status) for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9452Usage Model(Status) for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9460Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9472Margin Payload(Status) for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS6_REGMARGIN_LANE_CNTRL_STATUS6_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr95820x20R/W0x00009c38PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REGMargining Lane Control and Status Register for Lane 6.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9487Receiver Number for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9497Margin Type for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9507Usage Model for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9515Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9525Margin Payload for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9537Receiver Number(Status) for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9549Margin Type(Status) for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9561Usage Model(Status) for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9569Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9581Margin Payload(Status) for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS7_REGMARGIN_LANE_CNTRL_STATUS7_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr96910x24R/W0x00009c38PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REGMargining Lane Control and Status Register for Lane 7.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9596Receiver Number for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9606Margin Type for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9616Usage Model for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9624Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9634Margin Payload for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9646Receiver Number(Status) for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9658Margin Type(Status) for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9670Usage Model(Status) for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9678Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9690Margin Payload(Status) for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAPPF0_TPH_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr99750x208R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_TPH_CAPPF TLP Processing Hints Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP.TPH_EXT_CAP_HDR_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP.TPH_REQ_CAP_REG_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP.TPH_REQ_CONTROL_REG_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP.TPH_ST_TABLE_REG_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP.TPH_EXT_CAP_HDR_REGTPH_EXT_CAP_HDR_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr97510x0R0x29410017PE0_DWC_pcie_ctl_AXI_Slave_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REGTPH Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCIE_EXT_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9718TPH Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0017RTPH_REQ_CAP_VERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9734Capability Version.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RTPH_REQ_NEXT_PTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9750Next Capability Pointer.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x294RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP.TPH_REQ_CAP_REG_REGTPH_REQ_CAP_REG_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr98900x4R0x00000001PE0_DWC_pcie_ctl_AXI_Slave_PF0_TPH_CAP_TPH_REQ_CAP_REG_REGTPH Requestor Capability Register.For a description of this standard PCIe register, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same values for VF_TPH_REQ_CAP_REG_REG. To write this common register, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PF TPH_REQ_CAP_REG_REG register.falsefalsefalsefalseTPH_REQ_NO_ST_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9773No ST Mode Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x1RTPH_REQ_CAP_INT_VECPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9789Interrupt Vector Mode Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.110x0RTPH_REQ_DEVICE_SPECPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9805Device Specific Mode Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.220x0RRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9812Reserved for future use.730x00RTPH_REQ_EXTENDED_TPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9828Extended TPH Requester Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.880x0RTPH_REQ_CAP_ST_TABLE_LOC_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9844ST Table Location Bit 0.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.990x0RTPH_REQ_CAP_ST_TABLE_LOC_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9860ST Table Location Bit 1.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.10100x0RRSVDP_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9867Reserved for future use.15110x00RTPH_REQ_CAP_ST_TABLE_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9882ST Table Size.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.26160x000RRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9889Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP.TPH_REQ_CONTROL_REG_REGTPH_REQ_CONTROL_REG_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr99350x8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REGTPH Requestor Control Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseTPH_REQ_ST_MODE_SELECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9909ST Mode Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 200x0RRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9917Reserved for future use.730x00RTPH_REQ_CTRL_REQ_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9926TPH Requester Enable Bit.For a description of this standard PCIe register field, see the PCI Express Base Specification.980x0R/WRSVDP_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9934Reserved for future use.31100x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP.TPH_ST_TABLE_REG_0TPH_ST_TABLE_REG_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr99740xCR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TPH_CAP_TPH_ST_TABLE_REG_0TPH ST Table Register 0.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseTPH_REQ_ST_TABLE_LOWER_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9956ST Table 0 Lower Byte.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: this field is RW or Tie to 0 by table size configure - Dbi: this field is RW or Tie to 0 by table size configure 700x00R/WTPH_REQ_ST_TABLE_HIGHER_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr9973ST Table 0 Upper Byte.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: this field is RW or Tie to 0 by table size configure - Dbi: this field is RW or Tie to 0 by table size configure 1580x00R--31160x0rgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_LTR_CAPPF0_LTR_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr101270x294R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_LTR_CAPPF Latency Tolerance Reporting Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_LTR_CAP.LTR_CAP_HDR_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_LTR_CAP.LTR_LATENCY_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_LTR_CAP.LTR_CAP_HDR_REGLTR_CAP_HDR_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr10041This register provides capbility ID, capability version and next offset value for LTR(Latency Tolerance Reporting).0x0R0x29c10018PE0_DWC_pcie_ctl_AXI_Slave_PF0_LTR_CAP_LTR_CAP_HDR_REGLTR Extended Capability Header.This register provides capbility ID, capability version and next offset value for LTR(Latency Tolerance Reporting).falsefalsefalsefalseCAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10006LTR Extended Capacity ID.This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability.PCI Express Extended Capability for the LTR Extended Capability is 0018h.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0018RCAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10023Capability Version.This field is a PCI-SIG defined version number that indicates the version of the Capability structure present.This field is depends on version of the specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10040Next Capability Offset.This field contains the offset to the next PCI Express Extended Capability structure or 000h if no other items exist in the linked list of Capabilities.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x29cRregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_LTR_CAP.LTR_LATENCY_REGLTR_LATENCY_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr10126This register indicates Latency scale and vlaue for Max Snoop and No-Snoop.0x4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_LTR_CAP_LTR_LATENCY_REGLTR Max Snoop and No-Snoop Latency Register.This register indicates Latency scale and vlaue for Max Snoop and No-Snoop.falsefalsefalsefalseMAX_SNOOP_LATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10064Max Snoop Latency Value.Along with the Max Snoop LatencyScale field,this register specifies the maximum snoop latency that a device is permitted to request. Software should set this to the platform’s maximum supported latency or less.It is strongly recommended that any updates to this field are reflected in LTR Message(s) sent by the device within 1 ms.The default value for this field is 00 0000 0000b.900x000R/WMAX_SNOOP_LAT_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10079Max Snoop Latency Scale.This register provides a scale for the value contained within the Max Snoop LatencyValue field. Encoding is the same as the LatencyScale fields in the LTR Message.It is strongly recommended that any updates to this field are reflected in LTR Message(s) sent by the device within 1 ms.The default value for this field is 000b.Hardware operation is undefined if software writes a Not Permitted value to this field.12100x0R/WRSVDP_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10087Reserved for future use.15130x0RMAX_NO_SNOOP_LATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10102Max No-Snoop Latency Value.Along with the Max No-Snoop LatencyScale field, this register specifies the maximum no-snoop latency that a device is permitted to request. Software should set this to the platform’s maximum supported latency or less.It is strongly recommended that any updates to this field are reflected in LTR Message(s) sent by the device within 1 ms.The default value for this field is 00 0000 0000b.25160x000R/WMAX_NO_SNOOP_LAT_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10117Max No-Snoop Latency Scale.This register provides a scale for the value contained within the Max No-Snoop LatencyValue field. Encoding is the same as the LatencyScale fields in the LTR Message.It is strongly recommended that any updates to this field are reflected in LTR Message(s) sent by the device within 1 ms.The default value for this field is 000b.Hardware operation is undefined if software writes a Not Permitted value to this field.28260x0R/WRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10125Reserved for future use.31290x0RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAPPF0_L1SUB_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr105730x29CR/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_L1SUB_CAPL1 Substates Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAP.L1SUB_CAP_HEADER_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAP.L1SUB_CAPABILITY_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL1_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAP.L1SUB_CAP_HEADER_REGL1SUB_CAP_HEADER_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr10201L1 Substates Extended Capability Header provides capbility ID, capability version and next offset value for L1 Substates.0x0R0x2bc1001ePE0_DWC_pcie_ctl_AXI_Slave_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REGL1 Substates Extended Capability Header.This register provides capbility ID, capability version and next offset value for L1 Substates.falsefalsefalsefalseEXTENDED_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10158L1SUB Extended Capability ID.This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability.Extended Capability ID for L1 PM Substates is 001Eh.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x001eRCAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10175Capability Version.This field is a PCI-SIG defined version number that indicates the version of the Capability structure present.This field is depends on version of the specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10200Next Capability Offset.This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities.For Extended Capabilities implemented in Configuration Space, this offset is relative to the beginning of PCI-compatible Configuration Space and thus must always be either 000h (for terminating list of Capabilities) or greater than 0FFh.The bottom 2 bits of this offset are Reserved and must be implemented as 00b although software must mask them to allow for future uses of these bits.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x2bcRregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAP.L1SUB_CAPABILITY_REGL1SUB_CAPABILITY_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr10366This register provides extended capability of L1 Substates.0x4R/W0x00380a1fPE0_DWC_pcie_ctl_AXI_Slave_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REGL1 Substates Capability Register.This register provides extended capability of L1 Substates.falsefalsefalsefalseL1_2_PCIPM_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10219PCI-PM L12 Supported.When Set this bit indicates that PCI-PM L1.2 is supported.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R/W (sticky) 000x1R/WL1_1_PCIPM_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10232PCI-PM L11 Supported.When Set this bit indicates that PCI-PM L1.1 is supported, and must be Set by all Ports implementing L1 PM Substates.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R/W (sticky) 110x1R/WL1_2_ASPM_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10244ASPM L12 Supported.When Set this bit indicates that ASPM L1.2 is supported.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R/W (sticky) 220x1R/WL1_1_ASPM_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10256ASPM L11 Supported.When Set this bit indicates that ASPM L1.1 is supported.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R/W (sticky) 330x1R/WL1_PMSUB_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10269L1 PM Substates ECN Supported.When Set this bit indicates that this Port supports L1 PM Substates.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R/W (sticky) 440x1R/WRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10277Reserved for future use.750x0RCOMM_MODE_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10296Port Common Mode Restore Time.Time (in us) required for this Port to re-establish common mode.Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set, ASPM L1.2 Supported bit is Set, or both are Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 1580x0aR/WPWR_ON_SCALE_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10323Port T Power On Scale.Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register.Range of values are given below.Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set, ASPM L1.2 Supported bit is Set, or both are Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 17160x0R/WfalsetruefalseReserved0x3Reserved.RSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10331Reserved for future use.18180x0RPWR_ON_VALUE_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10357Port T Power On Value.Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time (in us) that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.The value of Port T_POWER_ON is calculated by multiplying the value in this field by the scale value in the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register. Default value is 00101b.Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set, ASPM L1.2 Supported bit is Set, or both are Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 23190x07R/WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10365Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL1_REGL1SUB_CONTROL1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr10488This register provides Controls to extended capability.0x8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_L1SUB_CAP_L1SUB_CONTROL1_REGL1 Substates Control 1 Register.This register provides Controls to extended capability.falsefalsefalsefalseL1_2_PCIPM_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10382PCI-PM L12 Enable.When Set this bit enables PCI-PM L1.2.For Ports for which the PCI-PM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b.000x0R/WL1_1_PCIPM_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10391PCI-PM L11 Enable.When Set this bit enables PCI-PM L1.1. Default value is 0b.110x0R/WL1_2_ASPM_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10401ASPM L12 Enable.When Set this bit enables ASPM L1.2.For Ports for which the ASPM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b.220x0R/WL1_1_ASPM_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10411ASPM L11 Enable.When Set this bit enables ASPM L1.1.For Ports for which the ASPM L1.1 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b.330x0R/WRSVDP_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10419Reserved for future use.740x0RT_COMMON_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10438Common Mode Restore Time.Sets value of TCOMMONMODE (in μs), which must be used by the Downstream Ports for timing the re-establishment of common mode.This field is of type RsvdP for Upstream Ports.Default value is implementation specific.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RW : RSVDP 1580x00R/WL1_2_TH_VALPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10458LTR L12 Threshold Value.Along with the LTR_L1.2_THRESHOLD_Scale, this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 (if enabled) or L1.2 (if enabled). The default value for this field is 00 0000 0000b.Required for all Ports for which the ASPM L12 Supported bit is Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT ? RW : RSVDP - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT ? RW : RSVDP 25160x000R/WRSVDP_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10466Reserved for future use.28260x0RL1_2_TH_SCAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10487LTR L12 Threshold Scale.This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.The default value for this field is 000b.Hardware operation is undefined if software writes a Not-Permitted value to this field.Required for all Ports Ports for which the ASPM L12 Supported bit is Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT ? RW : RSVDP - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT ? RW : RSVDP 31290x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL2_REGL1SUB_CONTROL2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr10572This register provides Controls to extended capability.0xCR/W0x00000028PE0_DWC_pcie_ctl_AXI_Slave_PF0_L1SUB_CAP_L1SUB_CONTROL2_REGL1 Substates Control 2 Register.This register provides Controls to extended capability.falsefalsefalsefalseT_POWER_ON_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10526T Power On Scale.Specifies the scale used for T_POWER_ON Value.Range of values are given below.Required for all Ports that support L1.2, otherwise this field is of type RsvdP. This field must only be modified when the ASPM L1.2 Enable and PCI-PM L1.2 Enable bits are both Clear.The Port behavior is undefined if this field is modified when either the ASPM L1.2 Enable and/or PCI-PM L1.2 Enable bit(s) are Set.Note: The access attributes of this field are as follows: - Wire: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 100x0R/WfalsetruefalseReserved0x3Reserved.RSVDP_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10534Reserved for future use.220x0RT_POWER_ON_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10563T Power On Value.Along with the T_POWER_ON Scale sets the minimum amount of time (in μs) that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.Default value is 00101b.T_POWER_ON is calculated by multiplying the value in this field by the value in the T_POWER_ON Scale field.Required for all Ports that support L1.2, otherwise this field is of type RsvdP.This field must only be modified when the ASPM L1.2 Enable and PCI-PM L1.2 Enable bits are both Clear.The Port behavior is undefined if this field is modified when either the ASPM L1.2 Enable and/or PCI-PM L1.2 Enable bit(s) are Set.Note: The access attributes of this field are as follows: - Wire: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 730x05R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10571Reserved for future use.3180x000000RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_LNR_CAPPF0_LNR_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr107490x2BCR/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_LNR_CAPPF LNR Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_LNR_CAP.LNR_EXT_CAP_HDR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_LNR_CAP.LNR_CAP_CONTROL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_LNR_CAP.LNR_EXT_CAP_HDR_OFFLNR_EXT_CAP_HDR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr106320x0R0x2c41001cPE0_DWC_pcie_ctl_AXI_Slave_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFFLNR Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseLNR_EXT_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10599PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x001cRLNR_CAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10615Capability Verison.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RLNR_NEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10631Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x2c4RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_LNR_CAP.LNR_CAP_CONTROL_OFFLNR_CAP_CONTROL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr107480x4R/W0x1f000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_LNR_CAP_LNR_CAP_CONTROL_OFFLNR Control Register and Capability Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseLNR_64_SUPPORTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10654LNR-64 Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.000x0RLNR_128_SUPPORTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10671LNR-128 Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.110x0RRSVDP_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10679Reserved for future use.720x00RLNR_REGISTRATION_MAXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10696LNR Registration Max.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10704Reserved for future use.15130x0RLNR_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10713LNR Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0R/WLNR_CLSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10722LNR CLS.For a description of this standard PCIe register field, see the PCI Express Base Specification.17170x0R/WRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10730Reserved for future use.23180x00RLNR_REGISTRATION_LIMITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10739LNR Registration Limit.For a description of this standard PCIe register field, see the PCI Express Base Specification.28240x1fR/WRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10747Reserved for future use.31290x0RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAPPF0_RAS_DES_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr139890x2C4R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAPRAS D.E.S. Capability Structure (VSEC)registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.RAS_DES_CAP_HEADER_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.VENDOR_SPECIFIC_HEADER_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_CONTROL_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_DATA_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_CONTROL_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_63_32_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ_ENABLE_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ0_CRC_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ1_SEQNUM_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ2_DLLP_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ3_SYMBOL_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ4_FC_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ5_SP_TLP_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H0_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H1_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H3_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H0_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H1_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H3_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H0_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H1_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H3_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H0_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H1_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H3_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_TLP_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_CONTROL1_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_CONTROL2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LANE_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LTSSM_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_PM_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3FC_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL1_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL3_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS1_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS3_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.RAS_DES_CAP_HEADER_REGRAS_DES_CAP_HEADER_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr108080x0R0x3c41000bPE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REGVendor-Specific Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseEXTENDED_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10775PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x000bRCAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10791Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10807Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x3c4RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.VENDOR_SPECIFIC_HEADER_REGVENDOR_SPECIFIC_HEADER_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr108420x4R0x10040002PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REGVendor-Specific Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVSEC_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10823VSEC ID.For a description of this standard PCIe register field, see the PCI Express Specification.1500x0002RVSEC_REVPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10832VSEC Rev.For a description of this standard PCIe register field, see the PCI Express Specification.19160x4RVSEC_LENGTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10841VSEC Length.For a description of this standard PCIe register field, see the PCI Express Specification.31200x100RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_CONTROL_REGEVENT_COUNTER_CONTROL_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr109890x8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REGEvent Counter Control.This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG viewport register. - Setting the EVENT_COUNTER_ENABLE field in this register enables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. - Setting the EVENT_COUNTER_CLEAR field in this register clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. - Reading the EVENT_COUNTER_STATUS field in this register returns the Enable status of the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.falsefalsefalsefalseEVENT_COUNTER_CLEARPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10883Event Counter Clear.Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.You can clear the value of a specific Event Counter by writing the 'per clear' code and you can clear all event counters at once by writing the 'all clear' code.The read value is always '0'. - 00: no change - 01: per clear - 10: no change - 11: all clear - Other: reserved100x0WEVENT_COUNTER_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10909Event Counter Enable.Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.By default, all event counters are disabled.You can enable/disable a specific Event Counter by writing the 'per event off' or 'per event on' codes.You can enable/disable all event counters by writing the 'all on' or 'all off' codes.The read value is always '0'. - 000: no change - 001: per event off - 010: no change - 011: per event on - 100: no change - 101: all off - 110: no change - 111: all on420x0WRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10917Reserved for future use.650x0REVENT_COUNTER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10932Event Counter Status.This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECTNote: This register field is sticky.770x0REVENT_COUNTER_LANE_SELECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10949Event Counter Lane Select.This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15Note: This register field is sticky.1180x0R/WRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10957Reserved for future use.15120x0REVENT_COUNTER_EVENT_SELECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10980Event Counter Data Select.This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event number(8-bit: 0..0x13) within the GroupFor example: - 0x000: Ebuf Overflow - 0x001: Ebuf Underrun - .. - 0x700: Tx Memory Write - 0x713: Rx Message TLPFor detailed definitions of Group number and Event number, see the RAS DES chapter in the Databook.Note: This register field is sticky.27160x000R/WRSVDP_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_SETDWC_pcie_dbi_cpcie_usp_4x8.csr10988Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_DATA_REGEVENT_COUNTER_DATA_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr110140xCR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REGEvent Counter Data.This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REGFor more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEVENT_COUNTER_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11013Event Counter Data.This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REGNote: This register field is sticky.3100x00000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_CONTROL_REGTIME_BASED_ANALYSIS_CONTROL_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr111300x10R/W0x00000100PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REGTime-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseTIMER_STARTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11038Timer Start. - 1: Start/Restart - 0: StopThis bit will be cleared automatically when the measurement is finished.Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop.Note: This register field is sticky.000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11046Reserved for future use.710x00RTIME_BASED_DURATION_SELECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11068Time-based Duration Select.Selects the duration of time-based analysis.When "manual control" is selected and TIMER_START is set to '1', this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1: 1ms - 0x2: 10ms - 0x3: 100ms - 0x4: 1s - 0x5: 2s - 0x6: 4s - 0xff: 4us (Debug purpose) - Else: ReservedNote: This register field is sticky.1580x01R/WRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11076Reserved for future use.23160x00RTIME_BASED_REPORT_SELECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11129Time-based Report Select.Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT), and returned in TIME_BASED_ANALYSIS_DATA.Each type of data is measured using one of three types of units: - Core_clk Cycles for 2.5GT/s, 5.0GT/s, 8.0GT/s, 16.0GT/s, 32GT/s. Total time in ps is [Value of TIME_BASED_ANALYSIS_DATA returned when TIME_BASED_REPORT_SELECT=0x00] * TIME_BASED_ANALYSIS_DATA - Aux_clk Cycles. Total time in ps is [Period of platform specific clock] * TIME_BASED_ANALYSIS_DATA - Core_clk Cycles for 20GT/s, 25GT/s (CCIX ESM data rate). Total time in ps is [Value of TIME_BASED_ANALYSIS_DATA returned when TIME_BASED_REPORT_SELECT=0x10] * TIME_BASED_ANALYSIS_DATA - Data Bytes. Actual amount of bytes is 16 * TIME_BASED_ANALYSIS_DATACore_clk Cycles for 2.5GT/s, 5.0GT/s, 8.0GT/s, 16.0GT/s, 32GT/s - 0x00: Duration of 1 cycle - 0x01: TxL0s - 0x02: RxL0s - 0x03: L0 - 0x04: L1 - 0x07: Configuration/Recovery - 0x08: TxL0s and RxL0sAux_clk Cycles - 0x05: L1.1 - 0x06: L1.2 - 0x09: L1 auxCore_clk Cycles for 20GT/s, 25GT/s (CCIX ESM data rate) - 0x10: Duration of 1 cycle - 0x11: TxL0s - 0x12: RxL0s - 0x13: L0 - 0x14: L1 - 0x17: Configuration/Recovery - 0x18: TxL0s and RxL0sData Bytes - 0x20: Tx PCIe TLP data payload Bytes - 0x21: Rx PCIe TLP data payload Bytes - 0x22: Tx CCIX TLP data payload Bytes - 0x23: Rx CCIX TLP data payload Bytes - Else: RsvdNote: This register field is sticky.31240x00R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_REGTIME_BASED_ANALYSIS_DATA_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr111570x14R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REGTime-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state.This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseTIME_BASED_ANALYSIS_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11156Time Based Analysis Data.This register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG.The results are cleared when next measurement starts.Note: This register field is sticky.3100x00000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_63_32_REGTIME_BASED_ANALYSIS_DATA_63_32_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr111780x18R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REGUpper 32 bits of Time-based Analysis Data. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseTIME_BASED_ANALYSIS_DATA_63_32PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11177Upper 32 bits of Time Based Analysis Data.Note: This register field is sticky.3100x00000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ_ENABLE_REGEINJ_ENABLE_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr113150x30R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ_ENABLE_REGError Injection Enable.Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1: Sequence Number Error: EINJ1_SEQNUM_REG - 2: DLLP Error: EINJ2_DLLP_REG - 3: Symbol DataK Mask Error or Sync Header Error: EINJ3_SYMBOL_REG - 4: FC Credit Update Error: EINJ4_FC_REG - 5: TLP Duplicate/Nullify Error: EINJ5_SP_TLP_REG - 6: Specific TLP Error: EINJ6_COMPARE_*_REG/EINJ6_CHANGE_*_REG/EINJ6_TLP_REGAfter the errors have been inserted by controller, it will clear each bit here.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseERROR_INJECTION0_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11211Error Injection0 Enable (CRC Error).Enables insertion of errors into various CRC.For more details, see the EINJ0_CRC_REG register.Note: This register field is sticky.000x0R/WERROR_INJECTION1_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11225Error Injection1 Enable (Sequence Number Error).Enables insertion of errors into sequence numbers.For more details, see the EINJ1_SEQNUM_REG register.Note: This register field is sticky.110x0R/WERROR_INJECTION2_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11239Error Injection2 Enable (DLLP Error).Enables insertion of DLLP errors.For more details, see the EINJ2_DLLP_REG register.Note: This register field is sticky.220x0R/WERROR_INJECTION3_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11255Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error).Enables DataK masking of special symbols or the breaking of the sync header.For more details, see the EINJ3_SYMBOL_REG register.Note: This register field is sticky.330x0R/WERROR_INJECTION4_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11269Error Injection4 Enable (FC Credit Update Error).Enables insertion of errors into UpdateFCs.For more details, see the EINJ4_FC_REG register.Note: This register field is sticky.440x0R/WERROR_INJECTION5_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11283Error Injection5 Enable (TLP Duplicate/Nullify Error).Enables insertion of duplicate/nullified TLPs.For more details, see the EINJ5_SP_TLP_REG register.Note: This register field is sticky.550x0R/WERROR_INJECTION6_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11306Error Injection6 Enable (Specific TLP Error).Enables insertion of errors into the packets that you select.You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT =0.You can set this bit to '1' when you have disabled the address translation by setting ADDR_TRANSLATION_SUPPORT_EN=0.For more details, see the EINJ6_COMPARE_*_REG/EINJ6_CHANGE_*_REG/EINJ6_TLP_REG registers.Note: This register field is sticky.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11314Reserved for future use.3170x0000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ0_CRC_REGEINJ0_CRC_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr113850x34R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ0_CRC_REGError Injection Control 0 (CRC Error).Controls the insertion of errors into the CRC, and parity of ordered sets for the selected type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with NAK DLLP; Data Link Retry starts. - 16-bit CRC of ACK/NAK DLLPs. Bad DLLP occurs at the receiver side; Replay NUM Rollover occurs. - 16-bit CRC of UpdateFC DLLPs. Error insertion continues for the specific time; LTSSM transitions to the Recovery state because of the UpdateFC timeout (if the timeout is implemented at the receiver of the UpdateFCs). - ECRC. If ECRC check is enabled, ECRC error is detected at the receiver side. - FCRC. Framing error will be detected, TLP is discarded, and the LTSSM transitions to Recovery state. - Parity of TSOS. Error insertion continues for the specific time; LTSSM Recovery/Configuration timeout will occur. - Parity of SKPOS. Lane error will be detected at the receiver side.falsefalsefalsefalseEINJ0_COUNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11353Error injection count.Indicates the number of errors.This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the counter value is 0x00 and ERROR_INJECTION0_ENABLE=1, the errors are inserted until ERROR_INJECTION0_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ0_CRC_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11376Error injection type.Selects the type of CRC error to be inserted.Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC error injection - 0100b: TLP's FCRC error injection (128b/130b) - 0101b: Parity error of TSOS (128b/130b) - 0110b: Parity error of SKPOS (128b/130b)Rx Path - 1000b: LCRC error injection - 1011b: ECRC error injection - Others: ReservedNote: This register field is sticky.1180x0R/WRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11384Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ1_SEQNUM_REGEINJ1_SEQNUM_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr114830x38R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REGError Injection Control 1 (Sequence Number Error).Controls the sequence number of the specific TLPs and ACK/NAK DLLPs.Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true: - ((NEXT_TRANSMIT_SEQ -1) - AckNak_Seq_Num) mod 4096 > 2048 - (AckNak_Seq_Num - ACKD_SEQ) mod 4096 >= 2048TLP is treated as Duplicate TLP at the Rx side when all these conditions are true: - Sequence Number != NEXT_RCV_SEQ - (NEXT_RCV_SEQ - Sequence Number) mod 4096 <= 2048TLP is treated as Bad TLP at the Rx side when all these conditions are true: - Sequence Number != NEXT_RCV_SEQ and - (NEXT_RCV_SEQ - Sequence Number) mod 4096 > 2048falsefalsefalsefalseEINJ1_COUNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11420Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION1_ENABLE=1, the errors are inserted until ERROR_INJECTION1_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ1_SEQNUM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11432Sequence number type.Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# ErrorNote: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11440Reserved for future use.1590x00REINJ1_BAD_SEQNUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11474Bad sequence number.Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. - 0x1001: -4095For example: - Set Type, SEQ# and Count -- EINJ1_SEQNUM_TYPE =0 (Insert errors into new TLPs) -- EINJ1_BAD_SEQNUM =0x1FFD (represents -3) -- EINJ1_COUNT =1 - Enable Error Injection -- ERROR_INJECTION1_ENABLE =1 - Send a TLP From the Core's Application Interface -- Assume SEQ#5 is given to the TLP. - The SEQ# is Changed to #2 by the Error Injection Function in Layer2. -- 5 + (-3) = 2 - The TLP with SEQ#2 is Transmitted to PCIe Link.Note: This register field is sticky.28160x0000R/WRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11482Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ2_DLLP_REGEINJ2_DLLP_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr115430x3CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ2_DLLP_REGError Injection Control 2 (DLLP Error).Controls the transmission of DLLPs and inserts the following errors: - If "ACK/NAK DLLP's transmission block" is selected, replay timeout error will occur at the transmitter of the TLPs and then Data Link Retry will occur. - If "Update FC DLLP's transmission block" is selected, LTSSM will transition to the Recovery state because of the UpdateFC timeout (if the timeout is implemented at the receiver of the UpdateFCs). - If "Always Transmission for NAK DLLP" is selected, Data Link Retry will occur at the transmitter of the TLPs. Furthermore, Replay NUM Rollover will occur when the transmitter has been requested four times to send the TLP with the same sequence number.falsefalsefalsefalseEINJ2_COUNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11520Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted, ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION2_ENABLE =1, the errors are inserted until ERROR_INJECTION2_ENABLE is set to '0'.This register is affected only when EINJ2_DLLP_TYPE =2'10b.Note: This register field is sticky.700x00R/WEINJ2_DLLP_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11534DLLP Type.Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: ReservedNote: This register field is sticky.980x0R/WRSVDP_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11542Reserved for future use.31100x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ3_SYMBOL_REGEINJ3_SYMBOL_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr116030x40R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REGError Injection Control 3 (Symbol Error).When 8b/10b encoding is used, this register controls error insertion into the special (K code) symbols. - If TS1/TS2/FTS/E-Idle/SKP is selected, it affects whole of the ordered set. It might cause timeout of the LTSSM. - If END/EDB/STP/SDP is selected, TLP/DLLP will be discarded at the receiver side.When 128b/130b encoding is used, this register controls error insertion into the sync-header.falsefalsefalsefalseEINJ3_COUNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11571Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION3_ENABLE =1, the errors are inserted until ERROR_INJECTION3_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ3_SYMBOL_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11594Error Type.8b/10b encoding - Mask K symbol. It is not supported to insert errors into the first ordered-set after exiting from TxElecIdle when CX_FREQ_STEP_EN has been enabled. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b: COM/PAD(TS2 Order set) - 011b: COM/FTS(FTS Order set) - 100b: COM/IDL(E-Idle Order set) - 101b: END/EDB Symbol - 110b: STP/SDP Symbol - 111b: COM/SKP(SKP Order set)128b/130b encoding - Change sync header. - 000b: Invert sync header - Others: ReservedNote: This register field is sticky.1080x0R/WRSVDP_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11602Reserved for future use.31110x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ4_FC_REGEINJ4_FC_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr117080x44R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ4_FC_REGError Injection Control 4 (FC Credit Error).Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit - Completion TLP Header credit - Posted TLP Data credit - Non-Posted TLP Data credit - Completion TLP Data creditThese errors are not correctable while error insertion is enabled. Receiver buffer overflow error might occur.falsefalsefalsefalseEINJ4_COUNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11634Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION4_ENABLE =1, the errors are inserted until ERROR_INJECTION4_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ4_UPDFC_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11652Update-FC type.Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit value control - 101b: Non-Posted TLP Data Credit value control - 110b: Completion TLP Data Credit value control - 111b: ReservedNote: This register field is sticky.1080x0R/WRSVDP_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11660Reserved for future use.11110x0REINJ4_VC_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11671VC Number.Indicates target VC Number.Note: This register field is sticky.14120x0R/WRSVDP_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11679Reserved for future use.15150x0REINJ4_BAD_UPDFC_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11699Bad update-FC credit value.Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. - 0x1001: -4095Note: This register field is sticky.28160x0000R/WRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11707Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ5_SP_TLP_REGEINJ5_SP_TLP_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr117650x48R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REGError Injection Control 5 (Specific TLP Error).Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For Duplicate TLP, the controller initiates Data Link Retry by handling ACK DLLP as NAK DLLP. These TLPs will be duplicate TLPs at the receiver side. - For Nullified TLP, the TLPs that the controller transmits are changed into nullified TLPs and the original TLPs are stored in the retry buffer. The receiver of these TLPs will detect the lack of seq# and send NAK DLLP at the next TLP. Then the original TLPs are sent from retry buffer and the data controls are recovered. For 128 bit controller or more than 128 bit, the controller inserts errors the number of times of EINJ5_COUNT but doesn't ensure that the errors are continuously inserted into TLPs.falsefalsefalsefalseEINJ5_COUNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11742Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION5_ENABLE =1, the errors are inserted until ERROR_INJECTION5_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ5_SPECIFIED_TLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11756Specified TLP.Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer).Note: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11764Reserved for future use.3190x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H0_REGEINJ6_COMPARE_POINT_H0_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr118030x4CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REGError Injection Control 6 (Compare Point Header DWORD #0).Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_POINT_H0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11802Packet Compare Point: 1st DWORD.Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H1_REGEINJ6_COMPARE_POINT_H1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr118410x50R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REGError Injection Control 6 (Compare Point Header DWORD #1).Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_POINT_H1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11840Packet Compare Point: 2nd DWORD.Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H2_REGEINJ6_COMPARE_POINT_H2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr118770x54R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REGError Injection Control 6 (Compare Point Header DWORD #2).Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_POINT_H2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11876Packet Compare Point: 3rd DWORD.Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H3_REGEINJ6_COMPARE_POINT_H3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr119150x58R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REGError Injection Control 6 (Compare Point Header DWORD #3).Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_POINT_H3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11914Packet Compare Point: 4th DWORD.Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H0_REGEINJ6_COMPARE_VALUE_H0_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr119490x5CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REGError Injection Control 6 (Compare Value Header DWORD #0).Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_VALUE_H0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11948Packet Compare Value: 1st DWORD.Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H1_REGEINJ6_COMPARE_VALUE_H1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr119830x60R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REGError Injection Control 6 (Compare Value Header DWORD #1).Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_VALUE_H1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr11982Packet Compare Value: 2nd DWORD.Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H2_REGEINJ6_COMPARE_VALUE_H2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr120170x64R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REGError Injection Control 6 (Compare Value Header DWORD #2).Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_VALUE_H2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12016Packet Compare Value: 3rd DWORD.Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H3_REGEINJ6_COMPARE_VALUE_H3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr120510x68R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REGError Injection Control 6 (Compare Value Header DWORD #3).Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_VALUE_H3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12050Packet Compare Value: 4th DWORD.Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H0_REGEINJ6_CHANGE_POINT_H0_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr120830x6CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REGError Injection Control 6 (Change Point Header DWORD #0).Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_POINT_H0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12082Packet Change Point: 1st DWORD.Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H1_REGEINJ6_CHANGE_POINT_H1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr121150x70R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REGError Injection Control 6 (Change Point Header DWORD #1).Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_POINT_H1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12114Packet Change Point: 2nd DWORD.Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H2_REGEINJ6_CHANGE_POINT_H2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr121470x74R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REGError Injection Control 6 (Change Point Header DWORD #2).Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_POINT_H2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12146Packet Change Point: 3rd DWORD.Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H3_REGEINJ6_CHANGE_POINT_H3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr121790x78R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REGError Injection Control 6 (Change Point Header DWORD #3).Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_POINT_H3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12178Packet Change Point: 4th DWORD.Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H0_REGEINJ6_CHANGE_VALUE_H0_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr122140x7CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REGError Injection Control 6 (Change Value Header DWORD #0).Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_VALUE_H0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12213Packet Change Value: 1st DWORD.Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H1_REGEINJ6_CHANGE_VALUE_H1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr122490x80R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REGError Injection Control 6 (Change Value Header DWORD #1).Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_VALUE_H1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12248Packet Change Value: 2nd DWORD.Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H2_REGEINJ6_CHANGE_VALUE_H2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr122840x84R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REGError Injection Control 6 (Change Value Header DWORD #2).Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_VALUE_H2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12283Packet Change Value: 3rd DWORD.Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H3_REGEINJ6_CHANGE_VALUE_H3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr123190x88R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REGError Injection Control 6 (Change Value Header DWORD #3).Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_VALUE_H3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12318Packet Change Value: 4th DWORD.Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_TLP_REGEINJ6_TLP_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr124000x8CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_TLP_REGError Injection Control 6 (Packet Error).The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the this register.The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the this register.Only applies when EINJ6_INVERTED_CONTROL in this register =0.The TLP into that errors are injected will not arrive at the transaction layer of the remote device when all of the following conditions are true. - Using 128b/130b encoding - Injecting errors into TLP Length field / TLP digest bitfalsefalsefalsefalseEINJ6_COUNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12363Error Injection Count.Indicates the number of errors to insert.This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION6_ENABLE=1, errors are inserted until ERROR_INJECTION6_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ6_INVERTED_CONTROLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12376Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3].Note: This register field is sticky.880x0R/WEINJ6_PACKET_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12391Packet type.Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: ReservedNote: This register field is sticky.1190x0R/WRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12399Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_CONTROL1_REGSD_CONTROL1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr124970xA0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_CONTROL1_REGSilicon Debug Control 1.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseFORCE_DETECT_LANEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12423Force Detect Lane.When the FORCE_DETECT_LANE_EN field is set, the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15Note: This register field is sticky.1500x0000R/WFORCE_DETECT_LANE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12437Force Detect Lane Enable.When this bit is set, the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE.Note: This register field is sticky.16160x0R/WRSVDP_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12445Reserved for future use.19170x0RTX_EIOS_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12470Number of Tx EIOS.This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification.2.5GT/s, 8.0GT/s or higher: - 0x0: 1 - 0x1: 4 - 0x2: 8 - 0x3: 165.0GT/s: - 0x0: 2 - 0x1: 8 - 0x2: 16 - 0x3: 32Note: This register field is sticky.21200x0R/WLOW_POWER_INTERVALPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12488Low Power Entry Interval Time.Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to, RXELECIDLE assertion at the PHY. - 0x0: 40ns - 0x1: 160ns - 0x2: 320ns - 0x3: 640nsNote: This register field is sticky.23220x0R/WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12496Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_CONTROL2_REGSD_CONTROL2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr126200xA4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_CONTROL2_REGSilicon Debug Control 2.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseHOLD_LTSSMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12515Hold and Release LTSSM.For as long as this register is '1', the controller stays in the current LTSSM.Note: This register field is sticky.000x0R/WRECOVERY_REQUESTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12528Recovery Request.When this bit is set to '1' in L0 or L0s, the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization.110x0WNOACK_FORCE_LINKDOWNPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12542Force LinkDown.When this bit is set and the controller detects REPLY_NUM rolling over 4 times, the LTSSM transitions to Detect State.Note: This register field is sticky.220x0R/WRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12550Reserved for future use.730x00RDIRECT_RECIDLE_TO_CONFIGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12563Direct Recovery.Idle to Configuration.When this bit is set and the LTSSM is in Recovery Idle State, the LTSSM transitions to Configuration state.Note: This register field is sticky.880x0R/WDIRECT_POLCOMP_TO_DETECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12576Direct Polling.Compliance to Detect.When this bit is set and the LTSSM is in Polling Compliance State, the LTSSM transitions to Detect state.Note: This register field is sticky.990x0R/WDIRECT_LPBKSLV_TO_EXITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12590Direct Loopback Slave To Exit.When this bit is set and the LTSSM is in Loopback Slave Active State, the LTSSM transitions to Loopback Slave Exit state.Note: This register field is sticky.10100x0R/WRSVDP_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12598Reserved for future use.15110x00RFRAMING_ERR_RECOVERY_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12611Framing Error Recovery Disable.This bit disables a transition to Recovery state when a Framing Error is occurred.Note: This register field is sticky.16160x0R/WRSVDP_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12619Reserved for future use.31170x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LANE_REGSD_STATUS_L1LANE_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr127520xB0R/W0x00180000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REGSilicon Debug Status(Layer1 Per-lane).This viewport register returns the data selected by the following field: - LANE_SELECT in SD_STATUS_L1LANE_REGFor more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseLANE_SELECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12645Lane Select.Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15Note: This register field is sticky.300x0R/WRSVDP_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12653Reserved for future use.1540x000RPIPE_RXPOLARITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12668PIPE:RxPolarity.Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT).Note: This register field is sticky.16160x0RPIPE_DETECT_LANEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12683PIPE:Detect Lane.Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT).Note: This register field is sticky.17170x0RPIPE_RXVALIDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12698PIPE:RxValid.Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT).Note: This register field is sticky.18180x0RPIPE_RXELECIDLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12713PIPE:RxElecIdle.Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT).Note: This register field is sticky.19190x1RPIPE_TXELECIDLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12728PIPE:TxElecIdle.Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT).Note: This register field is sticky.20200x1RRSVDP_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12736Reserved for future use.23210x0RDESKEW_POINTERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12751Deskew Pointer.Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT).Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LTSSM_REGSD_STATUS_L1LTSSM_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr129010xB4R/W0x00000200PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REGSilicon Debug Status(Layer1 LTSSM).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseFRAMING_ERR_PTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12821First Framing Error Pointer.Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1.Received Unexpected Framing Token - 01h: When non- STP/SDP/IDL Token was received and it was not in TLP/DLLP reception - 02h: When current token was not a valid EDB token and previous token was an EDB. (128/256 bit controller only) - 03h: When SDP token was received but not expected. (128 bit & (x8 | x16) controller only) - 04h: When STP token was received but not expected. (128 bit & (x8 | x16) controller only) - 05h: When EDS token was expected but not received or whenever an EDS token was received but not expected. - 06h: When a framing error was detected in the deskew block while a packet has been in progress in token_finder.Received Unexpected STP Token - 11h: When Framing CRC in STP token did not match - 12h: When Framing Parity in STP token did not match. - 13h: When Framing TLP Length in STP token was smaller than 5 DWORDs.Received Unexpected Block - 21h: When Receiving an OS Block following SDS in Datastream state - 22h: When Data Block followed by OS Block different from SKP, EI, EIE in Datastream state - 23h: When Block with an undefined Block Type in Datastream state - 24h: When Data Stream without data over three cycles in Datastream state - 25h: When OS Block during Data Stream in Datastream state - 26h: When RxStatus Error was detected in Datastream state - 27h: When Not all active lanes receiving SKP OS starting at same cycle time in SKPOS state - 28h: When a 2-Block timeout occurs for SKP OS in SKPOS state - 29h: When Receiving consecutive OS Blocks within a Data Stream in SKPOS state - 2Ah: When Phy status error was detected in SKPOS state - 2Bh: When Not all active lanes receiving EIOS starting at same cycle time in EIOS state - 2Ch: When At least one Symbol from the first 4 Symbols is not EIOS Symbol in EIOS state (CX_NB=2 only) - 2Dh: When Not all active lanes receiving EIEOS starting at same cycle time in EIEOS state - 2Eh: When Not full 16 eieos symbols are received in EIEOS stateAll other values not listed above are Reserved.Note: This register field is sticky.600x00RFRAMING_ERRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12832Framing Error.Indicates Framing Error detection status.770x0R/W1CPIPE_POWER_DOWNPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12846PIPE:PowerDown.Indicates PIPE PowerDown signal.Note: This register field is sticky.1080x2RRSVDP_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12854Reserved for future use.14110x0RLANE_REVERSALPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12870Lane Reversal Operation.Receiver detected lane reversal.This field is only valid in the L0 LTSSM state.Note: This register field is sticky.15150x0RLTSSM_VARIABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12900LTSSM Variable.Indicates internal LTSSM variables defined in the PCI Express Base Specification.C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if both ports advertised the UpConfigure capability in the last Config.Complete. - 4: select_deemphasis - 5: start_equalization_w_preset - 6: equalization_done_8GT_data_rate - 7: equalization_done_16GT_data_rate - 15:8: idle_to_rlock_transitionedM-PCIe Mode: - 0: idle_to_recovery - 1: recovery_to_configurationNote: This register field is sticky.31160x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_PM_REGSD_STATUS_PM_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr130420xB8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_STATUS_PM_REGSilicon Debug Status(PM).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseINTERNAL_PM_MSTATEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12943Internal PM State(Master).Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah: L1_WAIT_LAST_TLP_ACK - 0Bh: L1_WAIT_PMDLLP_ACK - 0Ch: L1_LINK_ENTR_L1 - 0Dh: L1_EXIT - 0Fh: PREP_4L1 - 10h: L23_BLOCK_TLP - 11h: L23_WAIT_LAST_TLP_ACK - 12h: L23_WAIT_PMDLLP_ACK - 13h: L23_ENTR_L23 - 14h: L23RDY - 15h: PREP_4L23 - 16h: L23RDY_WAIT4ALIVE - 17h: L0S_BLOCK_TLP - 18h: WAIT_LAST_PMDLLP - 19h: WAIT_DSTATE_UPDATENote: This register field is sticky.400x00RRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12951Reserved for future use.750x0RINTERNAL_PM_SSTATEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12978Internal PM State(Slave).Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h: S_L1_EXIT - 8h: S_L23RDY - 9h: S_LINK_ENTR_L23 - Ah: S_L23RDY_WAIT4ALIVE - Bh: S_ACK_WAIT4IDLE - Ch: S_WAIT_LAST_PMDLLPNote: This register field is sticky.1180x0RPME_RESEND_FLAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr12992PME Re-send flag.When the DUT sends a PM_PME message TLP, the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%), the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent.12120x0R/W1CL1SUB_STATEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13018L1Sub State.Indicates internal state machine of L1Sub state. - 0h: S_L1_U : idle state - 1h: S_L1_0 : wait for aux_clk_active - 2h: S_L1_0_WAIT4_ACK : wait for pclkack - 3h: S_L1_0_WAIT4_CLKREQ : wait for clkreq - 4h: S_L1_N_ENTRY : check clkreq_in_n is de-asserted for t_power_off time (only for L1.2, reduces to one cycle for L1.1) - 5h: S_L1_N : L1 substate, turn off txcommonmode circuits (L1.2 only) and rx electrical idle detection circuits - 6h: S_L1_N_EXIT : locally/remotely initiated exit, assert pclkreq, wait for pclkack - 7h: S_L1_N_ABORT : wait for pclkack when aborting an attempt to enter L1_NNote: This register field is sticky.15130x0RLATCHED_NFTSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13033Latched N_FTS.Indicates the value of N_FTS in the received TS Ordered Sets from the Link PartnerNote: This register field is sticky.23160x00RRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13041Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L2_REGSD_STATUS_L2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr131230xBCR0x00fff000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L2_REGSilicon Debug Status(Layer2).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseTX_TLP_SEQ_NOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13061Tx Tlp Sequence Number.Indicates next transmit sequence number for transmit TLP.Note: This register field is sticky.1100x000RRX_ACK_SEQ_NOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13075Tx Ack Sequence Number.Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP.Note: This register field is sticky.23120xfffRDLCMSMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13090DLCMSM.Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVENote: This register field is sticky.25240x0RFC_INIT1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13103FC_INIT1.Indicates the controller is in FC_INIT1(VC0) state.Note: This register field is sticky.26260x0RFC_INIT2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13115FC_INIT2.Indicates the controller is in FC_INIT2(VC0) state.Note: This register field is sticky.27270x0RRSVDP_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13122Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3FC_REGSD_STATUS_L3FC_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr132470xC0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REGSilicon Debug Status(Layer3 FC).The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE - CREDIT_SEL_HDFor more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseCREDIT_SEL_VCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13154Credit Select(VC).This field in conjunction with the CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 - 0x1: VC1 - 0x2: VC2 - .. - 0x7: VC7Note: This register field is sticky.200x0R/WCREDIT_SEL_CREDIT_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13170Credit Select(Credit Type).This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Rx - 0x1: TxNote: This register field is sticky.330x0R/WCREDIT_SEL_TLP_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13187Credit Select(TLP Type).This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Posted - 0x1: Non-Posted - 0x2: CompletionNote: This register field is sticky.540x0R/WCREDIT_SEL_HDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13203Credit Select(HeaderData).This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Header Credit - 0x1: Data CreditNote: This register field is sticky.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13211Reserved for future use.770x0RCREDIT_DATA0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13228Credit Data0.Current FC credit data selected by the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed ValueNote: This register field is sticky.1980x000RCREDIT_DATA1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13246Credit Data1.Current FC credit data selected by the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when DLCMSM=0x3(DL_ACTIVE).Note: This register field is sticky.31200x000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3_REGSD_STATUS_L3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr133030xC4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L3_REGSilicon Debug Status(Layer3).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseMFTLP_POINTERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13283First Malformed TLP Error Pointer.Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length miss match - 05h: Max payload size - 06h: Message TLP without TC0 - 07h: Invalid TC - 08h: Unexpected route bit in Message TLP - 09h: Unexpected CRS status in Completion TLP - 0Ah: Byte enable - 0Bh: Memory Address 4KB boundary - 0Ch: TLP prefix rules - 0Dh: Translation request rules - 0Eh: Invalid TLP type - 0Fh: Completion rules - 7Fh: Application - Else: ReservedNote: This register field is sticky.600x00RMFTLP_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13294Malformed TLP Status.Indicates malformed TLP has occurred.770x0R/W1CRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13302Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL1_REGSD_EQ_CONTROL1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr134430xD0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REGSilicon Debug EQ Control 1.This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport registers.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEQ_LANE_SELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13331EQ Status Lane Select.Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15Note: This register field is sticky.300x0R/WEQ_RATE_SELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13348EQ Status Rate Select.Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed (include ESM data rate) - 0x1: 16.0GT/s Speed (include ESM data rate) - 0x2: 32.0GT/s SpeedNote: This register field is sticky.540x0R/WRSVDP_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13356Reserved for future use.760x0REXT_EQ_TIMEOUTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13380Extends EQ Phase2/3 Timeout.This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set, the value of EQ2/3 timeout is extended.EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10: 240ms (x10) - 11: No timeoutEQ Slave(DSP in EQ Phase2/USP in EQ Phase3). - 00: 32ms (default) - 01: 56ms (32ms+24ms) - 10: 248ms (32ms +9*24ms) - 11: No timeoutNote: This register field is sticky.980x0R/WRSVDP_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13388Reserved for future use.15100x00REVAL_INTERVAL_TIMEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13406Eval Interval Time.Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4usThis field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2).Note: This register field is sticky.17160x0R/WRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13414Reserved for future use.22180x00RFOM_TARGET_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13426FOM Target Enable.Enables the FOM_TARGET fields.Note: This register field is sticky.23230x0R/WFOM_TARGETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13442FOM Target.Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2).This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit).Note: This register field is sticky.31240x00R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL2_REGSD_EQ_CONTROL2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr135870xD4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REGSilicon Debug EQ Control 2.This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseFORCE_LOCAL_TX_PRE_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13465Force Local Transmitter Pre-cursor.Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner.Note: This register field is sticky.500x00R/WFORCE_LOCAL_TX_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13479Force Local Transmitter Cursor.Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner.Note: This register field is sticky.1160x00R/WFORCE_LOCAL_TX_POST_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13493Force Local Transmitter Post-Cursor.Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner.Note: This register field is sticky.17120x00R/WFORCE_LOCAL_RX_HINTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13510Force Local Receiver Preset Hint.Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of received or set value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed, this feature is not available.Note: This register field is sticky.20180x0R/WRSVDP_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13518Reserved for future use.23210x0RFORCE_LOCAL_TX_PRESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13534Force Local Transmitter Preset.Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed, this feature is not available.Note: This register field is sticky.27240x0R/WFORCE_LOCAL_TX_COEF_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13548Force Local Transmitter Coefficient Enable.Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSORNote: This register field is sticky.28280x0R/WFORCE_LOCAL_RX_HINT_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13563Force Local Receiver Preset Hint Enable.Enables the FORCE_LOCAL_RX_HINT field.If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed, this feature is not available.Note: This register field is sticky.29290x0R/WFORCE_LOCAL_TX_PRESET_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13578Force Local Transmitter Preset Enable.Enables the FORCE_LOCAL_TX_PRESET field.If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed, this feature is not available.Note: This register field is sticky.30300x0R/WRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13586Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL3_REGSD_EQ_CONTROL3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr136710xD8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REGSilicon Debug EQ Control 3.This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseFORCE_REMOTE_TX_PRE_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13609Force Remote Transmitter Pre-Cursor.Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from local phy in dirchange mode.Note: This register field is sticky.500x00R/WFORCE_REMOTE_TX_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13623Force Remote Transmitter Cursor.Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from local phy in dirchange mode.Note: This register field is sticky.1160x00R/WFORCE_REMOTE_TX_POST_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13637Force Remote Transmitter Post-Cursor.Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from local phy in dirchange mode.Note: This register field is sticky.17120x00R/WRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13645Reserved for future use.27180x000RFORCE_REMOTE_TX_COEF_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13662Force Remote Transmitter Coefficient Enable.Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSORThis function can only be used when GEN3_EQ_FB_MODE = 0000b(Direction Change)Note: This register field is sticky.28280x0R/WRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13670Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS1_REGSD_EQ_STATUS1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr138150xE0R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REGSilicon Debug EQ Status 1.This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.The following fields are available when Equalization finished unsuccessfully(EQ_CONVERGENCE_INFO=2). - EQ_RULEA_VIOLATION - EQ_RULEB_VIOLATION - EQ_RULEC_VIOLATION - EQ_REJECT_EVENTFor more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEQ_SEQUENCEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13701EQ Sequence.Indicates that the controller is starting the equalization sequence.Note: This register field is sticky.000x0REQ_CONVERGENCE_INFOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13720EQ Convergence Info.Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: ReservedThis bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.210x0RRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13727Reserved for future use.330x0REQ_RULEA_VIOLATIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13748EQ Rule A Violation.Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to the rules a) from section "Rules for Transmitter Coefficents" in the PCI Express Base Specification.This bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.440x0REQ_RULEB_VIOLATIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13769EQ Rule B Violation.Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to the rules b) from section "Rules for Transmitter Coefficents" in the PCI Express Base Specification.This bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.550x0REQ_RULEC_VIOLATIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13790EQ Rule C Violation.Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to the rules c) from section "Rules for Transmitter Coefficents" in the PCI Express Base Specification.This bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.660x0REQ_REJECT_EVENTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13807EQ Reject Event.Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2).This bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.770x0RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13814Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS2_REGSD_EQ_STATUS2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr139030xE4R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REGSilicon Debug EQ Status 2.This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.Each field is available when Equalization finished successfully(EQ_CONVERGENCE_INFO=1).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEQ_LOCAL_PRE_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13840EQ Local Pre-Cursor.Indicates Local pre cursor coefficient value.Note: This register field is sticky.500x00REQ_LOCAL_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13853EQ Local Cursor.Indicates Local cursor coefficient value.Note: This register field is sticky.1160x00REQ_LOCAL_POST_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13866EQ Local Post-Cursor.Indicates Local post cursor coefficient value.Note: This register field is sticky.17120x00REQ_LOCAL_RX_HINTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13882EQ Local Receiver Preset Hint.Indicates Local Receiver Preset Hint value.If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed, this feature is not available.Note: This register field is sticky.20180x0RRSVDP_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13889Reserved for future use.23210x0REQ_LOCAL_FOM_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13902EQ Local Figure of Merit.Indicates Local maximum Figure of Merit value.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS3_REGSD_EQ_STATUS3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr139880xE8R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REGSilicon Debug EQ Status 3.This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.Each field is available when Equalization finished successfully(EQ_CONVERGENCE_INFO=1).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEQ_REMOTE_PRE_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13928EQ Remote Pre-Cursor.Indicates Remote pre cursor coefficient value.Note: This register field is sticky.500x00REQ_REMOTE_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13941EQ Remote Cursor.Indicates Remote cursor coefficient value.Note: This register field is sticky.1160x00REQ_REMOTE_POST_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13954EQ Remote Post-Cursor.Indicates Remote post cursor coefficient value.Note: This register field is sticky.17120x00REQ_REMOTE_LFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13967EQ Remote LF.Indicates Remote LF value.Note: This register field is sticky.23180x00REQ_REMOTE_FSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13980EQ Remote FS.Indicates Remote FS value.Note: This register field is sticky.29240x00RRSVDP_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_SETDWC_pcie_dbi_cpcie_usp_4x8.csr13987Reserved for future use.31300x0RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAPPF0_VSECRAS_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr150420x3C4R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAPPF RAS Datapath Protection Capability Structure (VSEC)registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_EXT_CAP_HDR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_VENDOR_SPECIFIC_HDR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_PROT_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNTER_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNT_REPORT_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNTER_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNT_REPORT_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_INJ_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_ERROR_LOCATION_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_ERROR_LOCATION_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_CLEAR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_CORR_ERROR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_UNCORR_ERROR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_EXT_CAP_HDR_OFFRASDP_EXT_CAP_HDR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr140490x0R0x3fc1000bPE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFFPCIe Extended capability ID, Capability version and Next capability offset.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseIDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14016PCI Express Extended Capability ID.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x000bRCAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14032Capability Version.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14048Next Capability Offset.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x3fcRregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_VENDOR_SPECIFIC_HDR_OFFRASDP_VENDOR_SPECIFIC_HDR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr140920x4R0x03810001PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFFVendor Specific Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVSEC_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14067VSEC ID.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.1500x0001RVSEC_REVPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14079VSEC Rev.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.19160x1RVSEC_LENGTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14091VSEC Length.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.31200x038RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_PROT_CTRL_OFFRASDP_ERROR_PROT_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr14298ECC error correction control0x8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFFECC error correction control. Allows you to disable ECC error correction for RAMs and datapath.When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native controller clock (core_clk), you must not write this register while operations are in progress in the AXI master / slave interface.falsefalsefalsefalseERROR_PROT_DISABLE_TXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14116Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors.Note: This register field is sticky.000x0R/WERROR_PROT_DISABLE_AXI_BRIDGE_MASTERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14127Error correction disable for AXI bridge master completion buffer.Note: This register field is sticky.110x0R/WERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14138Error correction disable for AXI bridge outbound request path.Note: This register field is sticky.220x0R/WERROR_PROT_DISABLE_DMA_WRITEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14148Error correction disable for DMA write engine.Note: This register field is sticky.330x0R/WERROR_PROT_DISABLE_LAYER2_TXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14158Error correction disable for layer 2 Tx path.Note: This register field is sticky.440x0R/WERROR_PROT_DISABLE_LAYER3_TXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14168Error correction disable for layer 3 Tx path.Note: This register field is sticky.550x0R/WERROR_PROT_DISABLE_ADM_TXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14178Error correction disable for Adm Tx path.Note: This register field is sticky.660x0R/WERROR_PROT_DISABLE_CXS_TXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14188Error correction disable for CXS Rx path (PCIe Tx path).Note: This register field is sticky.770x0R/WERROR_PROT_DISABLE_DTIM_TXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14198Error correction disable for DTIM Tx path.Note: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14206Reserved for future use.1590x00RERROR_PROT_DISABLE_RXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14216Global error correction disable for all Rx layers.Note: This register field is sticky.16160x0R/WERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14228Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors.Note: This register field is sticky.17170x0R/WERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUESTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14239Error correction disable for AXI bridge inbound request path.Note: This register field is sticky.18180x0R/WERROR_PROT_DISABLE_DMA_READPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14249Error correction disable for DMA read engine.Note: This register field is sticky.19190x0R/WERROR_PROT_DISABLE_LAYER2_RXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14259Error correction disable for layer 2 Rx path.Note: This register field is sticky.20200x0R/WERROR_PROT_DISABLE_LAYER3_RXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14269Error correction disable for layer 3 Rx path.Note: This register field is sticky.21210x0R/WERROR_PROT_DISABLE_ADM_RXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14279Error correction disable for ADM Rx path.Note: This register field is sticky.22220x0R/WERROR_PROT_DISABLE_CXS_RXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14289Error correction disable for CXS Tx path (PCIe Rx path).Note: This register field is sticky.23230x0R/WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14297Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNTER_CTRL_OFFRASDP_CORR_COUNTER_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr143850xCR/W0x00000010PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFFCorrected error (1-bit ECC) counter selection and control.This is a viewport control register.Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned by the RASDP_CORR_COUNT_REPORT_OFF viewport data register.falsefalsefalsefalseCORR_CLEAR_COUNTERSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14315Clear all correctable error counters.000x0WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14323Reserved for future use.310x0RCORR_EN_COUNTERSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14335Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozenThe counters are enabled by default.440x1R/WRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14343Reserved for future use.1950x0000RCORR_COUNTER_SELECTION_REGIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14369Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200x0R/WCORR_COUNTER_SELECTIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14384Counter selection.This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf31240x00R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNT_REPORT_OFFRASDP_CORR_COUNT_REPORT_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr144470x10R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFFCorrected error (1-bit ECC) counter data.This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register.falsefalsefalsefalseCORR_COUNTERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14401Current corrected error count for the selected counter.700x00RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14408Reserved for future use.1980x000RCORR_COUNTER_SELECTED_REGIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14435Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200x0RCORR_COUNTER_SELECTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14446Counter selection.Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNTER_CTRL_OFFRASDP_UNCORR_COUNTER_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr145380x14R/W0x00000010PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFFUncorrected error (2-bit ECC and parity) counter selection and control.This is a viewport control register.Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the counter data returned by the RASDP_UNCORR_COUNT_REPORT_OFF viewport data register.falsefalsefalsefalseUNCORR_CLEAR_COUNTERSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14467Clear uncorrectable errors counters.When asserted causes all counters tracking the uncorrectable errors to be cleared.000x0WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14475Reserved for future use.310x0RUNCORR_EN_COUNTERSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14487Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozenThe counters are enabled by default.440x1R/WRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14495Reserved for future use.1950x0000RUNCORR_COUNTER_SELECTION_REGIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14521Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200x0R/WUNCORR_COUNTER_SELECTIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14537Counter selection.This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf31240x00R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNT_REPORT_OFFRASDP_UNCORR_COUNT_REPORT_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr146010x18R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFFUncorrected error (2-bit ECC and parity) counter data.This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF register.falsefalsefalsefalseUNCORR_COUNTERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14555Current uncorrected error count for the selected counter700x00RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14562Reserved for future use.1980x000RUNCORR_COUNTER_SELECTED_REGIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14589Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200x0RUNCORR_COUNTER_SELECTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14600Counter selection.Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_INJ_CTRL_OFFRASDP_ERROR_INJ_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr14681Error injection control0x1CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFFError injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occursfalsefalsefalsefalseERROR_INJ_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14619Error injection global enable.When set enables the error insertion logic.000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14627Reserved for future use.310x0RERROR_INJ_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14638Error injection type: - 0: none - 1: 1-bit - 2: 2-bit540x0R/WRSVDP_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14646Reserved for future use.760x0RERROR_INJ_COUNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14659Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected1580x00R/WERROR_INJ_LOCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14672Error injection location.Selects where error injection takes place.You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf23160x00R/WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14680Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_ERROR_LOCATION_OFFRASDP_CORR_ERROR_LOCATION_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr14788Corrected errors locations.0x20R0x00d000d0PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFFCorrected errors locations. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14696Reserved for future use.300x0RREG_FIRST_CORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14723Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved740xdRLOC_FIRST_CORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14738Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf1580x00RRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14745Reserved for future use.19160x0RREG_LAST_CORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14772Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200xdRLOC_LAST_CORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14787Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_ERROR_LOCATION_OFFRASDP_UNCORR_ERROR_LOCATION_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr14895Uncorrected errors locations.0x24R0x00d000d0PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFFUncorrected errors locations. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14803Reserved for future use.300x0RREG_FIRST_UNCORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14830Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved740xdRLOC_FIRST_UNCORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14845Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf1580x00RRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14852Reserved for future use.19160x0RREG_LAST_UNCORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14879Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200xdRLOC_LAST_UNCORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14894Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_EN_OFFRASDP_ERROR_MODE_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr14939RASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error.0x28R/W0x00000001PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFFRASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are forwarded to your application are not guaranteed to be correct; you must discard them.For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseERROR_MODE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14919Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error.Note: This register field is sticky.000x1R/WAUTO_LINK_DOWN_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14930Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode.Note: This register field is sticky.110x0R/WRSVDP_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14938Reserved for future use.3120x00000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_CLEAR_OFFRASDP_ERROR_MODE_CLEAR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr14967Exit RASDP error mode.0x2CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFFExit RASDP error mode. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseERROR_MODE_CLEARPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14958Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs.000x0WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14966Reserved for future use.3110x00000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_CORR_ERROR_OFFRASDP_RAM_ADDR_CORR_ERROR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr15004RAM Address where a corrected error (1-bit ECC) has been detected.0x30R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFFRAM Address where a corrected error (1-bit ECC) has been detected. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseRAM_ADDR_CORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14986RAM Address where a corrected error (1-bit ECC) has been detected.2600x0000000RRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr14993Reserved for future use.27270x0RRAM_INDEX_CORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15003RAM index where a corrected error (1-bit ECC) has been detected.31280x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_UNCORR_ERROR_OFFRASDP_RAM_ADDR_UNCORR_ERROR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr15041RAM Address where an uncorrected error (2-bit ECC) has been detected.0x34R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFFRAM Address where an uncorrected error (2-bit ECC) has been detected. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseRAM_ADDR_UNCORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15023RAM Address where an uncorrected error (2-bit ECC) has been detected.2600x0000000RRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15030Reserved for future use.27270x0RRAM_INDEX_UNCORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15040RAM index where an uncorrected error (2-bit ECC) has been detected.31280x0RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_DLINK_CAPPF0_DLINK_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr152220x3FCRPE0_DWC_pcie_ctl_AXI_Slave_PF0_DLINK_CAPPF DLINK Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_EXT_HDR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_CAP_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_EXT_HDR_OFFDATA_LINK_FEATURE_EXT_HDR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr15116This register provides capbility ID, capability version and next offset value.0x0R0x40810025PE0_DWC_pcie_ctl_AXI_Slave_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFFData Link Feature Extended Capability Header.This register provides capbility ID, capability version and next offset value.falsefalsefalsefalseDLINK_EXT_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15072Capability ID.This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability.Extended Capability ID for Data Link Feature is 0025h.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0025RDLINK_CAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15089Capability Version.This field is a PCI-SIG defined version number that indicates the version of the Capability structure present.This field is depends on version of the specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RDLINK_NEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15115Next Capability Offset.This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities.For Extended Capabilities implemented in Configuration Space, this offset is relative to the beginning of PCI-compatible Configuration Space and thus must always be either 000h (for terminating list of Capabilities) or greater than 0FFh.The bottom 2 bits of this offset are Reserved and must be implemented as 00b although software must mask them to allow for future uses of these bits.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x408RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_CAP_OFFDATA_LINK_FEATURE_CAP_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr15177This register provides description about extended feature.0x4R0x80000001PE0_DWC_pcie_ctl_AXI_Slave_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFFData Link Feature Capabilities.This register provides description about extended feature.falsefalsefalsefalseSCALED_FLOW_CNTL_SUPPORTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15140Local Scaled Flow Control Supported.Bit 0 – Local Scaled Flow Control Supported. Bit 22:1 – RsvdP.Bits associated with features that this Port is capable of supporting are HwInit, defaulting to 1b.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 000x1RFUTURE_FEATURE_SUPPORTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15154Local Future Data Link Feature Supported.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.2210x000000RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15161Reserved for future use.30230x00RDL_FEATURE_EXCHANGE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15176Data Link Feature Exchange Enable.If Set, this bit indicates that this Port will enter the DL_Feature negotiation state. Default is 1b.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 31310x1RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_STATUS_OFFDATA_LINK_FEATURE_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr15221This Registor privides status of the capability of data link feature.0x8R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFFData Link Feature Status Register.This Registor privides status of the capability of data link feature.falsefalsefalsefalseREMOTE_DATA_LINK_FEATURE_SUPPORTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15198Remote Data Link Feature SupportedFeatures Currently defined are: Bit 0 - Remote Scaled Flow Control Supported.Other Bits are undefined. Default value is 00 0000h.2200x000000RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15205Reserved for future use.30230x00RDATA_LINK_FEATURE_STATUS_VALIDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15220Remote Data Link Feature Supported Valid.This bit indicates that the Port has received a Data Link Feature DLLP in state DL_Feature (see Section 3.2.1) and that the Remote Data Link Feature Supported and Remote Data Link Feature Ack fields arefield is meaningful. This bit is Cleared on entry to state DL_Inactive.Default is 0b.31310x0RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_RESBAR_CAPPF0_RESBAR_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr160640x408R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_RESBAR_CAPResizable BAR Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_HDR_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_REG_0_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RESBAR_CAP.RESBAR_CTRL_REG_0_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_HDR_REGRESBAR_CAP_HDR_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr152810x0R0x44810015PE0_DWC_pcie_ctl_AXI_Slave_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REGResizable BAR Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRESBAR_EXT_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15248Resizable BAR Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0015RRESBAR_CAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15264Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RRESBAR_CAP_NEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15280Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x448RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_REG_0_REGRESBAR_CAP_REG_0_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr157430x4R/W0x00000010PE0_DWC_pcie_ctl_AXI_Slave_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REGResizable BAR0 Capability Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15294Reserved for future use.300x0RRESBAR_CAP_REG_0_1MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15310Up to 1MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.440x1R/WRESBAR_CAP_REG_0_2MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15326Up to 2MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.550x0R/WRESBAR_CAP_REG_0_4MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15342Up to 4MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.660x0R/WRESBAR_CAP_REG_0_8MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15358Up to 8MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.770x0R/WRESBAR_CAP_REG_0_16MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15374Up to 16MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.880x0R/WRESBAR_CAP_REG_0_32MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15390Up to 32MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.990x0R/WRESBAR_CAP_REG_0_64MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15406Up to 64MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.10100x0R/WRESBAR_CAP_REG_0_128MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15422Up to 128MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.11110x0R/WRESBAR_CAP_REG_0_256MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15438Up to 256MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.12120x0R/WRESBAR_CAP_REG_0_512MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15454Up to 512MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.13130x0R/WRESBAR_CAP_REG_0_1GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15470Up to 1GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.14140x0R/WRESBAR_CAP_REG_0_2GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15486Up to 2GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.15150x0R/WRESBAR_CAP_REG_0_4GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15502Up to 4GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0R/WRESBAR_CAP_REG_0_8GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15518Up to 8GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0R/WRESBAR_CAP_REG_0_16GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15534Up to 16GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0R/WRESBAR_CAP_REG_0_32GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15550Up to 32GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0R/WRESBAR_CAP_REG_0_64GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15566Up to 64GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0R/WRESBAR_CAP_REG_0_128GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15582Up to 128GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0R/WRESBAR_CAP_REG_0_256GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15598Up to 256GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0R/WRESBAR_CAP_REG_0_512GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15614Up to 512GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0R/WRESBAR_CAP_REG_0_1TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15630Up to 1TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0R/WRESBAR_CAP_REG_0_2TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15646Up to 2TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0R/WRESBAR_CAP_REG_0_4TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15662Up to 4TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0R/WRESBAR_CAP_REG_0_8TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15678Up to 8TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0R/WRESBAR_CAP_REG_0_16TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15694Up to 16TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0R/WRESBAR_CAP_REG_0_32TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15710Up to 32TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0R/WRESBAR_CAP_REG_0_64TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15726Up to 64TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0R/WRESBAR_CAP_REG_0_128TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15742Up to 128TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RESBAR_CAP.RESBAR_CTRL_REG_0_REGRESBAR_CTRL_REG_0_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr160630x8R/W0x00000020PE0_DWC_pcie_ctl_AXI_Slave_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REGResizable BAR0 Control Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRESBAR_CTRL_REG_IDX_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15762BAR Index.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.200x0RRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15770Reserved for future use.430x0RRESBAR_CTRL_REG_NUM_BARSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15784Number of Resizeable BARs.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.750x1RRESBAR_CTRL_REG_BAR_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15798BAR Size.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1380x00R/WRSVDP_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15806Reserved for future use.15140x0RRESBAR_CTRL_REG_0_256TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15822Up to 256TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0R/WRESBAR_CTRL_REG_0_512TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15838Up to 512TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0R/WRESBAR_CTRL_REG_0_1PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15854Up to 1PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0R/WRESBAR_CTRL_REG_0_2PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15870Up to 2PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0R/WRESBAR_CTRL_REG_0_4PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15886Up to 4PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0R/WRESBAR_CTRL_REG_0_8PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15902Up to 8PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0R/WRESBAR_CTRL_REG_0_16PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15918Up to 16PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0R/WRESBAR_CTRL_REG_0_32PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15934Up to 32PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0R/WRESBAR_CTRL_REG_0_64PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15950Up to 64PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0R/WRESBAR_CTRL_REG_0_128PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15966Up to 128PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0R/WRESBAR_CTRL_REG_0_256PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15982Up to 256PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0R/WRESBAR_CTRL_REG_0_512PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr15998Up to 512PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0R/WRESBAR_CTRL_REG_0_1EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16014Up to 1EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0R/WRESBAR_CTRL_REG_0_2EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16030Up to 2EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0R/WRESBAR_CTRL_REG_0_4EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16046Up to 4EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0R/WRESBAR_CTRL_REG_0_8EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16062Up to 8EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0R/WgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_VF_RESBAR_CAPPF0_VF_RESBAR_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr184700x448R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_VF_RESBAR_CAPVF Resizable BAR Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_HDR_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_0_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_0_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_1_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_1_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_HDR_REGVF_RESBAR_CAP_HDR_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr161230x0R0x00010024PE0_DWC_pcie_ctl_AXI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REGResizable BAR Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVF_RESBAR_EXT_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16090Resizable BAR Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0024RVF_RESBAR_CAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16106Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RVF_RESBAR_CAP_NEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16122Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_0_REGVF_RESBAR_CAP_REG_0_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr165850x4R/W0x00000010PE0_DWC_pcie_ctl_AXI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REGResizable BAR0 Capability Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16136Reserved for future use.300x0RVF_RESBAR_CAP_REG_0_1MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16152Up to 1MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.440x1R/WVF_RESBAR_CAP_REG_0_2MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16168Up to 2MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.550x0R/WVF_RESBAR_CAP_REG_0_4MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16184Up to 4MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.660x0R/WVF_RESBAR_CAP_REG_0_8MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16200Up to 8MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.770x0R/WVF_RESBAR_CAP_REG_0_16MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16216Up to 16MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.880x0R/WVF_RESBAR_CAP_REG_0_32MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16232Up to 32MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.990x0R/WVF_RESBAR_CAP_REG_0_64MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16248Up to 64MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.10100x0R/WVF_RESBAR_CAP_REG_0_128MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16264Up to 128MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.11110x0R/WVF_RESBAR_CAP_REG_0_256MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16280Up to 256MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.12120x0R/WVF_RESBAR_CAP_REG_0_512MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16296Up to 512MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.13130x0R/WVF_RESBAR_CAP_REG_0_1GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16312Up to 1GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.14140x0R/WVF_RESBAR_CAP_REG_0_2GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16328Up to 2GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.15150x0R/WVF_RESBAR_CAP_REG_0_4GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16344Up to 4GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0R/WVF_RESBAR_CAP_REG_0_8GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16360Up to 8GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0R/WVF_RESBAR_CAP_REG_0_16GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16376Up to 16GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0R/WVF_RESBAR_CAP_REG_0_32GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16392Up to 32GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0R/WVF_RESBAR_CAP_REG_0_64GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16408Up to 64GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0R/WVF_RESBAR_CAP_REG_0_128GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16424Up to 128GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0R/WVF_RESBAR_CAP_REG_0_256GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16440Up to 256GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0R/WVF_RESBAR_CAP_REG_0_512GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16456Up to 512GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0R/WVF_RESBAR_CAP_REG_0_1TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16472Up to 1TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0R/WVF_RESBAR_CAP_REG_0_2TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16488Up to 2TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0R/WVF_RESBAR_CAP_REG_0_4TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16504Up to 4TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0R/WVF_RESBAR_CAP_REG_0_8TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16520Up to 8TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0R/WVF_RESBAR_CAP_REG_0_16TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16536Up to 16TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0R/WVF_RESBAR_CAP_REG_0_32TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16552Up to 32TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0R/WVF_RESBAR_CAP_REG_0_64TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16568Up to 64TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0R/WVF_RESBAR_CAP_REG_0_128TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16584Up to 128TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_0_REGVF_RESBAR_CTRL_REG_0_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr169050x8R/W0x00000060PE0_DWC_pcie_ctl_AXI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REGResizable BAR0 Control Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVF_RESBAR_CTRL_REG_IDX_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16604BAR Index.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.200x0RRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16612Reserved for future use.430x0RVF_RESBAR_CTRL_REG_NUM_BARSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16626Number of Resizeable BARs.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.750x3RVF_RESBAR_CTRL_REG_BAR_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16640BAR Size.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1380x00R/WRSVDP_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16648Reserved for future use.15140x0RVF_RESBAR_CTRL_REG_0_256TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16664Up to 256TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0R/WVF_RESBAR_CTRL_REG_0_512TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16680Up to 512TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0R/WVF_RESBAR_CTRL_REG_0_1PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16696Up to 1PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0R/WVF_RESBAR_CTRL_REG_0_2PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16712Up to 2PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0R/WVF_RESBAR_CTRL_REG_0_4PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16728Up to 4PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0R/WVF_RESBAR_CTRL_REG_0_8PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16744Up to 8PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0R/WVF_RESBAR_CTRL_REG_0_16PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16760Up to 16PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0R/WVF_RESBAR_CTRL_REG_0_32PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16776Up to 32PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0R/WVF_RESBAR_CTRL_REG_0_64PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16792Up to 64PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0R/WVF_RESBAR_CTRL_REG_0_128PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16808Up to 128PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0R/WVF_RESBAR_CTRL_REG_0_256PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16824Up to 256PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0R/WVF_RESBAR_CTRL_REG_0_512PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16840Up to 512PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0R/WVF_RESBAR_CTRL_REG_0_1EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16856Up to 1EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0R/WVF_RESBAR_CTRL_REG_0_2EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16872Up to 2EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0R/WVF_RESBAR_CTRL_REG_0_4EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16888Up to 4EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0R/WVF_RESBAR_CTRL_REG_0_8EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16904Up to 8EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_1_REGVF_RESBAR_CAP_REG_1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr173670xCR/W0x00000010PE0_DWC_pcie_ctl_AXI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REGResizable BAR1 Capability Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16918Reserved for future use.300x0RVF_RESBAR_CAP_REG_1_1MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16934Up to 1MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.440x1R/WVF_RESBAR_CAP_REG_1_2MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16950Up to 2MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.550x0R/WVF_RESBAR_CAP_REG_1_4MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16966Up to 4MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.660x0R/WVF_RESBAR_CAP_REG_1_8MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16982Up to 8MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.770x0R/WVF_RESBAR_CAP_REG_1_16MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr16998Up to 16MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.880x0R/WVF_RESBAR_CAP_REG_1_32MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17014Up to 32MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.990x0R/WVF_RESBAR_CAP_REG_1_64MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17030Up to 64MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.10100x0R/WVF_RESBAR_CAP_REG_1_128MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17046Up to 128MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.11110x0R/WVF_RESBAR_CAP_REG_1_256MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17062Up to 256MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.12120x0R/WVF_RESBAR_CAP_REG_1_512MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17078Up to 512MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.13130x0R/WVF_RESBAR_CAP_REG_1_1GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17094Up to 1GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.14140x0R/WVF_RESBAR_CAP_REG_1_2GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17110Up to 2GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.15150x0R/WVF_RESBAR_CAP_REG_1_4GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17126Up to 4GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0R/WVF_RESBAR_CAP_REG_1_8GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17142Up to 8GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0R/WVF_RESBAR_CAP_REG_1_16GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17158Up to 16GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0R/WVF_RESBAR_CAP_REG_1_32GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17174Up to 32GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0R/WVF_RESBAR_CAP_REG_1_64GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17190Up to 64GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0R/WVF_RESBAR_CAP_REG_1_128GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17206Up to 128GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0R/WVF_RESBAR_CAP_REG_1_256GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17222Up to 256GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0R/WVF_RESBAR_CAP_REG_1_512GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17238Up to 512GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0R/WVF_RESBAR_CAP_REG_1_1TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17254Up to 1TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0R/WVF_RESBAR_CAP_REG_1_2TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17270Up to 2TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0R/WVF_RESBAR_CAP_REG_1_4TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17286Up to 4TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0R/WVF_RESBAR_CAP_REG_1_8TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17302Up to 8TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0R/WVF_RESBAR_CAP_REG_1_16TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17318Up to 16TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0R/WVF_RESBAR_CAP_REG_1_32TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17334Up to 32TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0R/WVF_RESBAR_CAP_REG_1_64TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17350Up to 64TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0R/WVF_RESBAR_CAP_REG_1_128TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17366Up to 128TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_1_REGVF_RESBAR_CTRL_REG_1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr176870x10R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REGResizable BAR1 Control Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVF_RESBAR_CTRL_REG_IDX_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17386BAR Index.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.200x0RRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17394Reserved for future use.430x0RVF_RESBAR_CTRL_REG_NUM_BARSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17408Number of Resizeable BARs.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.750x0RVF_RESBAR_CTRL_REG_BAR_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17422BAR Size.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1380x00R/WRSVDP_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17430Reserved for future use.15140x0RVF_RESBAR_CTRL_REG_1_256TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17446Up to 256TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0R/WVF_RESBAR_CTRL_REG_1_512TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17462Up to 512TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0R/WVF_RESBAR_CTRL_REG_1_1PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17478Up to 1PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0R/WVF_RESBAR_CTRL_REG_1_2PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17494Up to 2PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0R/WVF_RESBAR_CTRL_REG_1_4PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17510Up to 4PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0R/WVF_RESBAR_CTRL_REG_1_8PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17526Up to 8PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0R/WVF_RESBAR_CTRL_REG_1_16PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17542Up to 16PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0R/WVF_RESBAR_CTRL_REG_1_32PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17558Up to 32PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0R/WVF_RESBAR_CTRL_REG_1_64PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17574Up to 64PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0R/WVF_RESBAR_CTRL_REG_1_128PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17590Up to 128PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0R/WVF_RESBAR_CTRL_REG_1_256PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17606Up to 256PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0R/WVF_RESBAR_CTRL_REG_1_512PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17622Up to 512PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0R/WVF_RESBAR_CTRL_REG_1_1EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17638Up to 1EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0R/WVF_RESBAR_CTRL_REG_1_2EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17654Up to 2EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0R/WVF_RESBAR_CTRL_REG_1_4EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17670Up to 4EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0R/WVF_RESBAR_CTRL_REG_1_8EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17686Up to 8EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_2_REGVF_RESBAR_CAP_REG_2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr181490x14R/W0x00000010PE0_DWC_pcie_ctl_AXI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REGResizable BAR2 Capability Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17700Reserved for future use.300x0RVF_RESBAR_CAP_REG_2_1MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17716Up to 1MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.440x1R/WVF_RESBAR_CAP_REG_2_2MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17732Up to 2MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.550x0R/WVF_RESBAR_CAP_REG_2_4MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17748Up to 4MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.660x0R/WVF_RESBAR_CAP_REG_2_8MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17764Up to 8MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.770x0R/WVF_RESBAR_CAP_REG_2_16MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17780Up to 16MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.880x0R/WVF_RESBAR_CAP_REG_2_32MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17796Up to 32MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.990x0R/WVF_RESBAR_CAP_REG_2_64MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17812Up to 64MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.10100x0R/WVF_RESBAR_CAP_REG_2_128MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17828Up to 128MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.11110x0R/WVF_RESBAR_CAP_REG_2_256MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17844Up to 256MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.12120x0R/WVF_RESBAR_CAP_REG_2_512MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17860Up to 512MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.13130x0R/WVF_RESBAR_CAP_REG_2_1GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17876Up to 1GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.14140x0R/WVF_RESBAR_CAP_REG_2_2GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17892Up to 2GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.15150x0R/WVF_RESBAR_CAP_REG_2_4GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17908Up to 4GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0R/WVF_RESBAR_CAP_REG_2_8GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17924Up to 8GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0R/WVF_RESBAR_CAP_REG_2_16GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17940Up to 16GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0R/WVF_RESBAR_CAP_REG_2_32GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17956Up to 32GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0R/WVF_RESBAR_CAP_REG_2_64GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17972Up to 64GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0R/WVF_RESBAR_CAP_REG_2_128GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr17988Up to 128GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0R/WVF_RESBAR_CAP_REG_2_256GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18004Up to 256GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0R/WVF_RESBAR_CAP_REG_2_512GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18020Up to 512GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0R/WVF_RESBAR_CAP_REG_2_1TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18036Up to 1TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0R/WVF_RESBAR_CAP_REG_2_2TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18052Up to 2TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0R/WVF_RESBAR_CAP_REG_2_4TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18068Up to 4TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0R/WVF_RESBAR_CAP_REG_2_8TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18084Up to 8TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0R/WVF_RESBAR_CAP_REG_2_16TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18100Up to 16TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0R/WVF_RESBAR_CAP_REG_2_32TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18116Up to 32TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0R/WVF_RESBAR_CAP_REG_2_64TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18132Up to 64TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0R/WVF_RESBAR_CAP_REG_2_128TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18148Up to 128TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_2_REGVF_RESBAR_CTRL_REG_2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr184690x18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REGResizable BAR2 Control Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVF_RESBAR_CTRL_REG_IDX_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18168BAR Index.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.200x0RRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18176Reserved for future use.430x0RVF_RESBAR_CTRL_REG_NUM_BARSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18190Number of Resizeable BARs.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.750x0RVF_RESBAR_CTRL_REG_BAR_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18204BAR Size.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1380x00R/WRSVDP_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18212Reserved for future use.15140x0RVF_RESBAR_CTRL_REG_2_256TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18228Up to 256TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0R/WVF_RESBAR_CTRL_REG_2_512TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18244Up to 512TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0R/WVF_RESBAR_CTRL_REG_2_1PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18260Up to 1PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0R/WVF_RESBAR_CTRL_REG_2_2PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18276Up to 2PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0R/WVF_RESBAR_CTRL_REG_2_4PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18292Up to 4PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0R/WVF_RESBAR_CTRL_REG_2_8PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18308Up to 8PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0R/WVF_RESBAR_CTRL_REG_2_16PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18324Up to 16PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0R/WVF_RESBAR_CTRL_REG_2_32PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18340Up to 32PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0R/WVF_RESBAR_CTRL_REG_2_64PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18356Up to 64PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0R/WVF_RESBAR_CTRL_REG_2_128PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18372Up to 128PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0R/WVF_RESBAR_CTRL_REG_2_256PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18388Up to 256PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0R/WVF_RESBAR_CTRL_REG_2_512PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18404Up to 512PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0R/WVF_RESBAR_CTRL_REG_2_1EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18420Up to 1EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0R/WVF_RESBAR_CTRL_REG_2_2EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18436Up to 2EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0R/WVF_RESBAR_CTRL_REG_2_4EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18452Up to 4EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0R/WVF_RESBAR_CTRL_REG_2_8EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18468Up to 8EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0R/WgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGICPF0_PORT_LOGICPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr243110x700R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGICPort LogicregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.ACK_LATENCY_TIMER_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VENDOR_SPEC_DLLP_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PORT_FORCE_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.ACK_F_ASPM_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PORT_LINK_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.LANE_SKEW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TIMER_CTRL_MAX_FUNC_NUM_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.SYMBOL_TIMER_FILTER_1_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.FILTER_MASK_2_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PL_DEBUG0_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PL_DEBUG1_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TX_P_FC_CREDIT_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TX_NP_FC_CREDIT_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TX_CPL_FC_CREDIT_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.QUEUE_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_1_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_2_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC0_P_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC0_NP_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC0_CPL_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC1_P_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC1_NP_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC1_CPL_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC2_P_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC2_NP_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC2_CPL_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC3_P_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC3_NP_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC3_CPL_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN2_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PHY_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PHY_CONTROL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TRGT_MAP_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_ADDR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_UPPER_ADDR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_MASK_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_MASK_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_MASK_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_MASK_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_MASK_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_MASK_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_MASK_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_MASK_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_GPIO_IO_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.CLOCK_GATING_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN3_RELATED_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN3_EQ_CONTROL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN3_EQ_FB_MODE_DIR_CHANGE_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.ORDER_RULE_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PIPE_LOOPBACK_CONTROL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MISC_CONTROL_1_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MULTI_LANE_CONTROL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PHY_INTEROP_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TRGT_CPL_LUT_DELETE_ENTRY_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.LINK_FLUSH_CONTROL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AMBA_ERROR_RESPONSE_DEFAULT_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AMBA_LINK_TIMEOUT_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AMBA_ORDERING_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_1_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_2_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_3_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_NUMBER_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_TYPE_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSIX_DOORBELL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSIX_RAM_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PL_LTR_LATENCY_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AUX_CLK_FREQ_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.L1_SUBSTATES_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.POWERDOWN_CTRL_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_1_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_2_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PIPE_RELATED_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.ACK_LATENCY_TIMER_OFFACK_LATENCY_TIMER_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr185270x0R/W0x0c23040bPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFFAck Latency Timer and Replay Timer Register.falsefalsefalsefalseROUND_TRIP_LATENCY_TIME_LIMITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18502Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details, see "Ack Scheduling".You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.After reset, the controller updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed.The value is determined from Tables 3-7, 3-8, and 3-9 of the PCIe 3.0 specification.The limit must reflect the round trip latency from requester to completer.If there is a change in the payload size or link width, the controller will override any value that you have written to this register field, and reset the field back to the specification-defined value. It will not change the value in the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.1500x040bR/WREPLAY_TIME_LIMITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18526Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details, see "Transmit Replay".You can modify the effective timer limit with the TIMER_MOD_REPLAY_TIMER field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.After reset, the controller updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed.The value is determined from Tables 3-4, 3-5, and 3-6 of the PCIe 3.0 specification.If there is a change in the payload size or link speed, the controller will override any value that you have written to this register field, and reset the field back to the specification-defined value. It will not change the value in the TIMER_MOD_REPLAY_TIMER field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.31160x0c23R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VENDOR_SPEC_DLLP_OFFVENDOR_SPEC_DLLP_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr185490x4R/W0xffffffffPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFFVendor Specific DLLP Register.falsefalsefalsefalseVENDOR_SPEC_DLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18548Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP.Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register, then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to send the DLLP. - [7:0] = Type - [31:8] = Payload (24 bits)The dllp type is in bits [7:0] while the remainder is the vendor defined payload.Note: This register field is sticky.3100xffffffffR/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PORT_FORCE_OFFPORT_FORCE_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr186430x8R/W0x00800004PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PORT_FORCE_OFFPort Force Link Register.falsefalsefalsefalseLINK_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18561Link Number. Not used for endpoint. Not used for M-PCIe.Note: This register field is sticky.700x04R/WFORCED_LTSSMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18574Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link).Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v.Note: This register field is sticky.1180x0R/WRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18582Reserved for future use.14120x0RFORCE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18601Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state, and to force the controller to transmit a specific Link Command. Asserting this bit triggers the following actions: - Forces the LTSSM to the state specified by the Forced LTSSM State field. - Forces the controller to transmit the command specified by the Forced Link Command field.This is a self-clearing register field. Reading from this register field always returns a "0".15150x0WLINK_STATEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18613Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link).LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v.Note: This register field is sticky.21160x00R/WRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18621Reserved for future use.22220x0RDO_DESKEW_FOR_SRISPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18634Use the transitions from TS2 to Logical Idle Symbol, SKP OS to Logical Idle Symbol, EIEOS to Logical Idle Symbol, and FTS Sequence to SKP OS to do deskew instead of using received SKP OS or TS1 to TS2 transition if DO_DESKEW_FOR_SRIS is set to 1.Note: This register field is sticky.23230x1R/WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18642Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.ACK_F_ASPM_CTRL_OFFACK_F_ASPM_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr187700xCR/W0x1bc8c800PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFFAck Frequency and L0-L1 ASPM Control Register.falsefalsefalsefalseACK_FREQPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18671Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before scheduling an ACK DLLP. - 0: Indicates that this Ack Frequency Counter feature is turned off. The controller generates a low-priority ACK request for every TLP that it receives. The controller waits until the ACK Latency Timer expires, then converts the current low-priority ACK request to a high-priority ACK request and schedules the DLLP for transmission to the remote link partner. - 1-255: Indicates that the controller will schedule a high-priority ACK after receiving this number of TLPs. It might schedule the ACK before receiving this number of TLPs if the ACK Latency Timer expires, but never later.For a typical system, you do not have to modify the default setting. For more details, see "ACK/NAK Scheduling".Note: This register field is sticky.700x00R/WACK_N_FTSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18687N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255.The controller does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s.This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.1580xc8R/WCOMMON_CLK_N_FTSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18713Common Clock N_FTS. This is the N_FTS when common clock is used.The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. This field is only writable (sticky) when all of the following configuration parameter equations are true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCYThe controller does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 23160xc8RL0S_ENTRANCE_LATENCYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18730L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 usThis field is applicable to STALL while in L0 for M-PCIe.Note: This register field is sticky.26240x3R/WL1_ENTRANCE_LATENCYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18749L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 usNote: Programming this timer with a value greater that 32us has no effect unless extended sync is used, or all of the credits are infinite.Note: This register field is sticky.29270x3R/WENTER_ASPMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18761ASPM L1 Entry Control. - 1: Controller enters ASPM L1 after a period in which it has been idle. - 0: Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s.Note: This register field is sticky.30300x0R/WRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18769Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PORT_LINK_CTRL_OFFPORT_LINK_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr189660x10R/W0x00000120PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFFPort Link Control Register.falsefalsefalsefalseVENDOR_SPECIFIC_DLLP_REQPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18787Vendor Specific DLLP Request. When software writes a '1' to this bit, the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF.Reading from this self-clearing register field always returns a '0'.000x0R/W1CSCRAMBLE_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18796Scramble Disable. Turns off data scrambling.Note: This register field is sticky.110x0R/WLOOPBACK_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18812Loopback Enable. Turns on loopback. For more details, see "Loopback".For M-PCIe, to force the master to enter Digital Loopback mode, you must set this field to "1" during Configuration.start state(initial discovery/configuration).M-PCIe doesn't support loopback mode from L0 state - only from Configuration.start.Note: This register field is sticky.220x0R/WRESET_ASSERTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18822Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only).Note: This register field is sticky.330x0R/WRSVDP_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18830Reserved for future use.440x0RDLL_LINK_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18841DLL Link Enable. Enables link initialization. When DLL Link Enable =0, the controller does not transmit InitFC DLLPs and does not establish a link.Note: This register field is sticky.550x1R/WLINK_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18850LINK_DISABLE is an internally reserved field. Do not use.Note: This register field is sticky.660x0R/WFAST_LINK_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18877Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster.The default scaling factor can be changed using the DEFAULT_FAST_LINK_SCALING_FACTOR parameter or through the FAST_LINK_SCALING_FACTOR field in the TIMER_CTRL_MAX_FUNC_NUM_OFF register.Fast Link Mode can also be activated by setting the diag_ctrl_bus[2] pin to '1'.For more details, see the "Fast Link Simulation Mode" section in the "Integrating the Controller with the PHY or Application RTL or Verification IP" chapter of the User Guide.For M-PCIe, this field also affects Remain Hibern8 Time, Minimum Activate Time, and RRAP timeout. If this bit is set to '1', tRRAPInitiatorResponse is set to 1.88 ms(60 ms/32).Note: This register field is sticky.770x0R/WLINK_RATEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18886LINK_RATE is an internally reserved field. Do not use.Note: This register field is sticky.1180x1R/WRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18894Reserved for future use.15120x0RLINK_CAPABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18918Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes. You must also change the value in the "Predetermined Number of Lanes" field of the "Link Width and Speed Change Control Register". For more information, see "How to Tie Off Unused Lanes". For information on upsizing and downsizing the link width, see "Link Establishment". - 000001: x1 - 000011: x2 - 000111: x4 - 001111: x8 - 011111: x16 - 111111: x32 (not supported)This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.2116R/W--23220x0rBEACON_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18927BEACON_ENABLE is an internally reserved field. Do not use.Note: This register field is sticky.24240x0R/WCORRUPT_LCRC_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18937CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use.Note: This register field is sticky.25250x0R/WEXTENDED_SYNCHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18947EXTENDED_SYNCH is an internally reserved field. Do not use.Note: This register field is sticky.26260x0R/WTRANSMIT_LANE_REVERSALE_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18957TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use.Note: This register field is sticky.27270x0R/WRSVDP_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18965Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.LANE_SKEW_OFFLANE_SKEW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr190470x14R/W0x3c000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_LANE_SKEW_OFFLane Skew Register.falsefalsefalsefalseINSERT_LANE_SKEWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18979INSERT_LANE_SKEW is an internally reserved field. Do not use.Note: This register field is sticky.2300x000000R/WFLOW_CTRL_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18989Flow Control Disable. Prevents the controller from sending FC DLLPs.Note: This register field is sticky.24240x0R/WACK_NAK_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr18999Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs.Note: This register field is sticky.25250x0R/WELASTIC_BUFFER_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19010Selects Elasticity Buffer operating mode:0: Nominal Half Full Buffer mode1: Nominal Empty Buffer ModeNote: This register field is sticky.26260x1R/WIMPLEMENT_NUM_LANESPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19036Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanesThe number of lanes to be used when in Loopback Master. The number of lanes programmed must be equal to or less than the valid number of lanes set in LINK_CAPABLE field. You must configure this field before initiating Loopback by writing in the LOOPBACK_ENABLE field.The controller will transition from Loopback.Entry to Loopback.Active after receiving two consecutive TS1 Ordered Sets with the Loopback bit asserted on the implementation specific number of lanes configured in this field.Note: This register field is sticky.30270x7R/WDISABLE_LANE_TO_LANE_DESKEWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19046Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TIMER_CTRL_MAX_FUNC_NUM_OFFTIMER_CTRL_MAX_FUNC_NUM_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr191440x18R/W0x40000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFFTimer Control and Max Function Number Register.falsefalsefalsefalseMAX_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19061Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request).Note: This register field is sticky.700x00R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19069Reserved for future use.1380x00RTIMER_MOD_REPLAY_TIMERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19089Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed, and in increments of 256 clock cycles at Gen3 speed. A value of "0" represents no modification to the timer limit. For more details, see the REPLAY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register.At Gen3 speed, the controller automatically changes the value of this field to DEFAULT_GEN3_REPLAY_ADJ.For M-PCIe, this field increases the time-out value for the replay timer in increments of 64 clock cycles at HS-Gear1, HS-Gear2, or HS-Gear3 speed.Note: This register field is sticky.1814R/WTIMER_MOD_ACK_NAKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19103Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of "0" represents no modification to the timer value. For more details, see the ROUND_TRIP_LATENCY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register.Note: This register field is sticky.23190x00R/WUPDATE_FREQ_TIMERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19113UPDATE_FREQ_TIMER is an internally reserved field. Do not use.Note: This register field is sticky.28240x00R/WFAST_LINK_SCALING_FACTORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19135Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us *a) - 1: Scaling Factor is 256 (1ms is 4us) - 2: Scaling Factor is 64 (1ms is 16us) - 3: Scaling Factor is 16 (1ms is 64us)Default is set by the hidden configuration parameter DEFAULT_FAST_LINK_SCALING_FACTOR which defaults to '0'.*a. When the LTSSM is in Config or L12 Entry State, 1ms timer is 2us, 2ms timer is 4us and 3ms timer is 6us.Not used for M-PCIe. Note: This register field is sticky.30290x2R/WRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19143Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.SYMBOL_TIMER_FILTER_1_OFFSYMBOL_TIMER_FILTER_1_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr193010x1CR/W0x00000140PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFFSymbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.falsefalsefalsefalseSKP_INT_VALPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19183SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application must program this register accordingly. For example, if 1536 were programmed into this register (in a 250 MHz controller), then the controller actually transmits SKP ordered sets once every 1537 symbol times.The value programmed to this register is actually clock ticks and not symbol times. In a 125 MHz controller, programming the value programmed to this register should be scaled down by a factor of 2 (because one clock tick = two symbol times in this case).Note: This value is not used at Gen3 speed; the skip interval is hardcoded to 370 blocks.For M-PCIe configurations, if the 2K_PPM_DISABLED field in the M-PCIe Configuration Attribute is changed, then this field is changed automatically as follows. - 2K_PPM_DISABLED=1: 1280 / CX_NB - 2K_PPM_DISABLED=0: 228/CX_NBYou need to set this field again if necessary when 2K_PPM_DISABLED is changed.Note: This register field is sticky.1000x140R/WEIDLE_TIMERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19192EIDLE_TIMER is an internally reserved field. Do not use.Note: This register field is sticky.14110x0R/WDISABLE_FC_WD_TIMERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19201Disable FC Watchdog Timer.Note: This register field is sticky.15150x0R/WMASK_RADM_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19300Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.[31]: CX_FLT_MASK_RC_CFG_DISCARD - 0: For RADM RC filter to not allow CFG transaction being received - 1: For RADM RC filter to allow CFG transaction being received[30]: CX_FLT_MASK_RC_IO_DISCARD - 0: For RADM RC filter to not allow IO transaction being received - 1: For RADM RC filter to allow IO transaction being received[29]: CX_FLT_MASK_MSG_DROP - 0: Drop MSG TLP (except for Vendor MSG). Send decoded message on the SII. - 1: Do not Drop MSG (except for Vendor MSG). Send message TLPs to your application on TRGT1 and send decoded message on the SII. - The default for this bit is the inverse of FLT_DROP_MSG. That is, if FLT_DROP_MSG =1, then the default of this bit is "0" (drop message TLPs). This bit only controls message TLPs other than Vendor MSGs. Vendor MSGs are controlled by Filter Mask Register 2, bits [1:0]. The controller never passes ATS Invalidate messages to the SII interface regardless of this filter rule setting. The controller passes all ATS Invalidate messages to TRGT1 (or AXI bridge master), as they are too big for the SII.[28]: CX_FLT_MASK_CPL_ECRC_DISCARD - Only used when completion queue is advertised with infinite credits and is in store-and-forward mode. - 0: Discard completions with ECRC errors - 1: Allow completions with ECRC errors to be passed up - Reserved field for SW.[27]: CX_FLT_MASK_ECRC_DISCARD - 0: Discard TLPs with ECRC errors - 1: Allow TLPs with ECRC errors to be passed up[26]: CX_FLT_MASK_CPL_LEN_MATCH - 0: Enforce length match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err - 1: MASK length match for completions[25]: CX_FLT_MASK_CPL_ATTR_MATCH - 0: Enforce attribute match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask attribute match for completions[24]: CX_FLT_MASK_CPL_TC_MATCH - 0: Enforce Traffic Class match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Traffic Class match for completions[23]: CX_FLT_MASK_CPL_FUNC_MATCH - 0: Enforce function match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask function match for completions[22]: CX_FLT_MASK_CPL_REQID_MATCH - 0: Enforce Req. Id match for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Req. Id match for completions[21]: CX_FLT_MASK_CPL_TAGERR_MATCH - 0: Enforce Tag Error Rules for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Tag Error Rules for completions[20]: CX_FLT_MASK_LOCKED_RD_AS_UR - 0: Treat locked Read TLPs as UR for EP; Supported for RC - 1: Treat locked Read TLPs as Supported for EP; UR for RC[19]: CX_FLT_MASK_CFG_TYPE1_REQ_AS_UR - 0: Treat CFG type1 TLPs as UR for EP; Supported for RC - 1: Treat CFG type1 TLPs as Supported for EP; UR for RC - When CX_SRIOV_ENABLE is set then this bit is set to allow the filter to process Type 1 Config requests if the EP consumes more than one bus number.[18]: CX_FLT_MASK_UR_OUTSIDE_BAR - 0: Treat out-of-bar TLPs as UR - 1: Do not treat out-of-bar TLPs as UR[17]: CX_FLT_MASK_UR_POIS - 0: Treat poisoned request TLPs as UR - 1: Do not treat poisoned request TLPs as UR - The native controller always passes poisoned completions to your application except when you are using the DMA read channel.[16]: CX_FLT_MASK_UR_FUNC_MISMATCH - 0: Treat Function MisMatched TLPs as UR - 1: Do not treat Function MisMatched TLPs as URNote: This register field is sticky.31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.FILTER_MASK_2_OFFFILTER_MASK_2_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr193620x20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_FILTER_MASK_2_OFFFilter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.falsefalsefalsefalseMASK_RADM_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19361Filter Mask 2. This field modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.[31:10]: Reserved[9]: CX_FLT_MASK_CPL_IN_LUT_CHECK - 0: Disable masking of checking if the tag of CPL is registered in LUT - 1: Enable masking of checking if the tag of CPL is registered in LUT[8]: CX_FLT_MASK_POIS_ERROR_REPORTING - 0: Disable masking of error reporting for Poisoned TLPs - 1: Enable masking of error reporting for Poisoned TLPs[7]: CX_FLT_MASK_PRS_DROP - 0: Allow PRS message to pass through - 1: Drop PRS Messages silently - This bit is ignored when the CX_FLT_MASK_MSG_DROP bit in the MASK_RADM_1 field of the SYMBOL_TIMER_FILTER_1_OFF register is set to '1'.[6]: CX_FLT_UNMASK_TD - 0: Disable unmask TD bit if CX_STRIP_ECRC_ENABLE - 1: Enable unmask TD bit if CX_STRIP_ECRC_ENABLE[5]: CX_FLT_UNMASK_UR_POIS_TRGT0 - 0: Disable unmask CX_FLT_MASK_UR_POIS with TRGT0 destination - 1: Enable unmask CX_FLT_MASK_UR_POIS with TRGT0 destination[4]: CX_FLT_MASK_LN_VENMSG1_DROP - 0: Allow LN message to pass through - 1: Drop LN Messages silently[3]: CX_FLT_MASK_HANDLE_FLUSH - 0: Disable controller Filter to handle flush request - 1: Enable controller Filter to handle flush request[2]: CX_FLT_MASK_DABORT_4UCPL - 0: Enable DLLP abort for unexpected completion - 1: Do not enable DLLP abort for unexpected completion[1]: CX_FLT_MASK_VENMSG1_DROP - 0: Vendor MSG Type 1 dropped silently - 1: Vendor MSG Type 1 not dropped[0]: CX_FLT_MASK_VENMSG0_DROP - 0: Vendor MSG Type 0 dropped with UR error reporting - 1: Vendor MSG Type 0 not droppedNote: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFAMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr193960x24R/W0x00000001PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFAMBA Multiple Outbound Decomposed NP SubRequests Control Register.falsefalsefalsefalseOB_RD_SPLIT_BURST_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19387Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to "0" disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request. For more details, see "AXI Bridge Ordering" in the AXI chapter of the Databook.You should not clear this register unless your application master is requesting an amount of read data greater than Max_Read_Request_Size, and the remote device (or switch) is reordering completions that have different tags.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.000x1R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19395Reserved for future use.3110x00000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PL_DEBUG0_OFFPL_DEBUG0_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr194090x28RPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PL_DEBUG0_OFFDebug Register 0falsefalsefalsefalseDEB_REG_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19408The value on cxpl_debug_info[31:0].310RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PL_DEBUG1_OFFPL_DEBUG1_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr194220x2CRPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PL_DEBUG1_OFFDebug Register 1falsefalsefalsefalseDEB_REG_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19421The value on cxpl_debug_info[63:32].310RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TX_P_FC_CREDIT_STATUS_OFFTX_P_FC_CREDIT_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr194760x30R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFFTransmit Posted FC Credit StatusfalsefalsefalsefalseTX_P_DATA_FC_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19447Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].1500x0000RTX_P_HEADER_FC_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19468Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].27160x000RRSVDP_TX_P_FC_CREDIT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19475Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TX_NP_FC_CREDIT_STATUS_OFFTX_NP_FC_CREDIT_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr195300x34R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFFTransmit Non-Posted FC Credit StatusfalsefalsefalsefalseTX_NP_DATA_FC_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19501Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].1500x0000RTX_NP_HEADER_FC_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19522Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].27160x000RRSVDP_TX_NP_FC_CREDIT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19529Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TX_CPL_FC_CREDIT_STATUS_OFFTX_CPL_FC_CREDIT_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr195840x38R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFFTransmit Completion FC Credit StatusfalsefalsefalsefalseTX_CPL_DATA_FC_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19555Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].1500x0000RTX_CPL_HEADER_FC_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19576Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].27160x000RRSVDP_TX_CPL_FC_CREDIT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19583Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.QUEUE_STATUS_OFFQUEUE_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr196880x3CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_QUEUE_STATUS_OFFQueue StatusfalsefalsefalsefalseRX_TLP_FC_CREDIT_NON_RETURNPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19601Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the link.000x0RTX_RETRY_BUFFER_NEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19612Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer.110x0RRX_QUEUE_NON_EMPTYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19623Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers.220x0RRX_QUEUE_OVERFLOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19634Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue.330x0R/W1CRSVDP_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19642Reserved for future use.1240x000RRX_SERIALIZATION_Q_NON_EMPTYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19653Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue.13130x0R--15140x0rTIMER_MOD_FLOW_CONTROLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19666FC Latency Timer Override Value. When you set the "FC Latency Timer Override Enable" in this register, the value in this field will override the FC latency timer value that the controller calculates according to the PCIe specification. For more details, see "Flow Control".Note: This register field is sticky.28160x0000R/WRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19674Reserved for future use.30290x0RTIMER_MOD_FLOW_CONTROL_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19687FC Latency Timer Override Enable. When this bit is set, the value from the "FC Latency Timer Override Value" field in this register will override the FC latency timer value that the controller calculates according to the PCIe specification.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_1_OFFVC_TX_ARBI_1_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr197370x40R0x0000000fPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFFVC Transmit Arbitration Register 1falsefalsefalsefalseWRR_WEIGHT_VC_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19703WRR Weight for VC0.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 700x0fRWRR_WEIGHT_VC_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19714WRR Weight for VC1.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 1580x00RWRR_WEIGHT_VC_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19725WRR Weight for VC2.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 23160x00RWRR_WEIGHT_VC_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19736WRR Weight for VC3.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_2_OFFVC_TX_ARBI_2_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr197860x44R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFFVC Transmit Arbitration Register 2falsefalsefalsefalseWRR_WEIGHT_VC_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19752WRR Weight for VC4.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 700x00RWRR_WEIGHT_VC_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19763WRR Weight for VC5.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 1580x00RWRR_WEIGHT_VC_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19774WRR Weight for VC6.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 23160x00RWRR_WEIGHT_VC_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19785WRR Weight for VC7.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC0_P_RX_Q_CTRL_OFFVC0_P_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr198900x48R/W0x462602e0PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFFSegmented-Buffer VC0 Posted Receive Queue Control.falsefalsefalsefalseVC0_P_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19803VC0 Posted Data Credits. The number of initial posted data credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x2e0R/WVC0_P_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19817VC0 Posted Header Credits. The number of initial posted header credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19826Reserved.Note: This register field is sticky.20200x0R/WVC0_P_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19835Reserved.Note: This register field is sticky.23210x1R/WVC0_P_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19845VC0 Scale Posted Header Credites.Note: This register field is sticky.25240x2R/WVC0_P_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19855VC0 Scale Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19864Reserved.Note: This register field is sticky.29280x0R/WTLP_TYPE_ORDERING_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19876TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-postedNote: This register field is sticky.30300x1R/WVC_ORDERING_RX_QPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19889VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues, used only in the segmented-buffer configuration: - 1: Strict ordering, higher numbered VCs have higher priority - 0: Round robinNote: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC0_NP_RX_Q_CTRL_OFFVC0_NP_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr199690x4CR/W0x06260060PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFFSegmented-Buffer VC0 Non-Posted Receive Queue Control.falsefalsefalsefalseVC0_NP_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19907VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x060R/WVC0_NP_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19921VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19930Reserved.Note: This register field is sticky.20200x0R/WVC0_NP_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19939Reserved.Note: This register field is sticky.23210x1R/WVC0_NP_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19949VC0 Scale Non-Posted Header Credites.Note: This register field is sticky.25240x2R/WVC0_NP_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19959VC0 Scale Non-Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19968Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC0_CPL_RX_Q_CTRL_OFFVC0_CPL_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr200480x50R/W0x06200000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFFSegmented-Buffer VC0 Completion Receive Queue Control.falsefalsefalsefalseVC0_CPL_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr19986VC0 Completion Data Credits. The number of initial Completion data credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x000R/WVC0_CPL_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20000VC0 Completion Header Credits. The number of initial Completion header credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x00R/WRESERVED8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20009Reserved.Note: This register field is sticky.20200x0R/WVC0_CPL_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20018Reserved.Note: This register field is sticky.23210x1R/WVC0_CPL_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20028VC0 Scale CPL Header Credites.Note: This register field is sticky.25240x2R/WVC0_CPL_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20038VC0 Scale CPL Data Credites.Note: This register field is sticky.27260x1R/WRESERVED9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20047Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC1_P_RX_Q_CTRL_OFFVC1_P_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr201480x54R/W0x462602e0PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFFSegmented-Buffer VC#i Posted Receive Queue Control.falsefalsefalsefalseVC1_P_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20065VC1 Posted Data Credits. The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x2e0R/WVC1_P_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20079VC1 Posted Header Credits. The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED0_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20088Reserved.Note: This register field is sticky.20200x0R/WVC1_P_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20097Reserved.Note: This register field is sticky.23210x1R/WVC1_P_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20107VC1 Scale Posted Header Credites.Note: This register field is sticky.25240x2R/WVC1_P_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20117VC1 Scale Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED1_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20126Reserved.Note: This register field is sticky.29280x0R/WTLP_TYPE_ORDERING_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20138TLP Type Ordering for VC#i. Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-postedNote: This register field is sticky.30300x1R/WRESERVED2_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20147Reserved.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC1_NP_RX_Q_CTRL_OFFVC1_NP_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr202270x58R/W0x06260001PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFFSegmented-Buffer VC#i Non-Posted Receive Queue Control.falsefalsefalsefalseVC1_NP_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20165VC#i Non-Posted Data Credits. The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x001R/WVC1_NP_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20179VC#i Non-Posted Header Credits. The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED3_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20188Reserved.Note: This register field is sticky.20200x0R/WVC1_NP_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20197Reserved.Note: This register field is sticky.23210x1R/WVC1_NP_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20207VC1 Scale Non-Posted Header Credites.Note: This register field is sticky.25240x2R/WVC1_NP_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20217VC1 Scale Non-Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED4_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20226Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC1_CPL_RX_Q_CTRL_OFFVC1_CPL_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr203060x5CR/W0x06200000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFFSegmented-Buffer VC#i Completion Receive Queue Control.falsefalsefalsefalseVC1_CPL_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20244VC#i Completion Data Credits. The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x000R/WVC1_CPL_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20258VC#i Completion Header Credits. The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x00R/WRESERVED5_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20267Reserved.Note: This register field is sticky.20200x0R/WVC1_CPL_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20276Reserved.Note: This register field is sticky.23210x1R/WVC1_CPL_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20286VC1 Scale CPL Header Credites.Note: This register field is sticky.25240x2R/WVC1_CPL_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20296VC1 Scale CPL Data Credites.Note: This register field is sticky.27260x1R/WRESERVED6_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20305Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC2_P_RX_Q_CTRL_OFFVC2_P_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr204060x60R/W0x462602e0PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFFSegmented-Buffer VC#i Posted Receive Queue Control.falsefalsefalsefalseVC2_P_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20323VC2 Posted Data Credits. The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x2e0R/WVC2_P_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20337VC2 Posted Header Credits. The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED0_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20346Reserved.Note: This register field is sticky.20200x0R/WVC2_P_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20355Reserved.Note: This register field is sticky.23210x1R/WVC2_P_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20365VC2 Scale Posted Header Credites.Note: This register field is sticky.25240x2R/WVC2_P_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20375VC2 Scale Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED1_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20384Reserved.Note: This register field is sticky.29280x0R/WTLP_TYPE_ORDERING_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20396TLP Type Ordering for VC#i. Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-postedNote: This register field is sticky.30300x1R/WRESERVED2_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20405Reserved.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC2_NP_RX_Q_CTRL_OFFVC2_NP_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr204850x64R/W0x06260001PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFFSegmented-Buffer VC#i Non-Posted Receive Queue Control.falsefalsefalsefalseVC2_NP_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20423VC#i Non-Posted Data Credits. The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x001R/WVC2_NP_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20437VC#i Non-Posted Header Credits. The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED3_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20446Reserved.Note: This register field is sticky.20200x0R/WVC2_NP_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20455Reserved.Note: This register field is sticky.23210x1R/WVC2_NP_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20465VC2 Scale Non-Posted Header Credites.Note: This register field is sticky.25240x2R/WVC2_NP_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20475VC2 Scale Non-Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED4_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20484Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC2_CPL_RX_Q_CTRL_OFFVC2_CPL_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr205640x68R/W0x06200000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFFSegmented-Buffer VC#i Completion Receive Queue Control.falsefalsefalsefalseVC2_CPL_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20502VC#i Completion Data Credits. The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x000R/WVC2_CPL_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20516VC#i Completion Header Credits. The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x00R/WRESERVED5_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20525Reserved.Note: This register field is sticky.20200x0R/WVC2_CPL_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20534Reserved.Note: This register field is sticky.23210x1R/WVC2_CPL_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20544VC2 Scale CPL Header Credites.Note: This register field is sticky.25240x2R/WVC2_CPL_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20554VC2 Scale CPL Data Credites.Note: This register field is sticky.27260x1R/WRESERVED6_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20563Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC3_P_RX_Q_CTRL_OFFVC3_P_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr206640x6CR/W0x462602e0PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFFSegmented-Buffer VC#i Posted Receive Queue Control.falsefalsefalsefalseVC3_P_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20581VC3 Posted Data Credits. The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x2e0R/WVC3_P_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20595VC3 Posted Header Credits. The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED0_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20604Reserved.Note: This register field is sticky.20200x0R/WVC3_P_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20613Reserved.Note: This register field is sticky.23210x1R/WVC3_P_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20623VC3 Scale Posted Header Credites.Note: This register field is sticky.25240x2R/WVC3_P_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20633VC3 Scale Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED1_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20642Reserved.Note: This register field is sticky.29280x0R/WTLP_TYPE_ORDERING_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20654TLP Type Ordering for VC#i. Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-postedNote: This register field is sticky.30300x1R/WRESERVED2_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20663Reserved.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC3_NP_RX_Q_CTRL_OFFVC3_NP_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr207430x70R/W0x06260001PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFFSegmented-Buffer VC#i Non-Posted Receive Queue Control.falsefalsefalsefalseVC3_NP_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20681VC#i Non-Posted Data Credits. The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x001R/WVC3_NP_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20695VC#i Non-Posted Header Credits. The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED3_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20704Reserved.Note: This register field is sticky.20200x0R/WVC3_NP_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20713Reserved.Note: This register field is sticky.23210x1R/WVC3_NP_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20723VC3 Scale Non-Posted Header Credites.Note: This register field is sticky.25240x2R/WVC3_NP_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20733VC3 Scale Non-Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED4_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20742Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC3_CPL_RX_Q_CTRL_OFFVC3_CPL_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr208220x74R/W0x06200000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFFSegmented-Buffer VC#i Completion Receive Queue Control.falsefalsefalsefalseVC3_CPL_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20760VC#i Completion Data Credits. The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x000R/WVC3_CPL_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20774VC#i Completion Header Credits. The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x00R/WRESERVED5_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20783Reserved.Note: This register field is sticky.20200x0R/WVC3_CPL_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20792Reserved.Note: This register field is sticky.23210x1R/WVC3_CPL_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20802VC3 Scale CPL Header Credites.Note: This register field is sticky.25240x2R/WVC3_CPL_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20812VC3 Scale CPL Data Credites.Note: This register field is sticky.27260x1R/WRESERVED6_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20821Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN2_CTRL_OFFGEN2_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr21106Link Width and Speed Change Control Register.0x10CR/W0x000108c8PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_GEN2_CTRL_OFFThis register is used to control various functions of the controller related to link training, lane reversal, and equalization.falsefalsefalsefalseFAST_TRAINING_SEQPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20849Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a low power state. The number should be provided by the PHY vendor. Do not set N_FTS to zero; doing so can cause the LTSSM to go into the recovery state when exiting from L0s.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.700xc8R/WNUM_OF_LANESPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20889Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken" or "unused" lanes that detect a receiver. Indicates the number of lanes to check for exit from Electrical Idle in Polling.Active and L2.Idle. It is possible that the LTSSM might detect a receiver on a bad or broken lane during the Detect Substate. However, it is also possible that such a lane might also fail to exit Electrical Idle and therefore prevent a valid link from being configured. This value is referred to as the "Predetermined Number of Lanes" in section 4.2.6.2.1 of the PCI Express Base 3.0 Specification, revision 1.0. Encoding is as follows: - 0x01: 1 lane - 0x02: 2 lanes - 0x03: 3 lanes - ..When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes. You must also change the value in the "Link Mode Enable" field of PORT_LINK_CTRL_OFF. The value in this register is normally the same as the encoded value in PORT_LINK_CTRL_OFF. If you find that one of your used lanes is bad then you must reduce the value in this register. For more information, see "How to Tie Off Unused Lanes." For information on upsizing and downsizing the link width, see "Link Establishment."This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.1280x08R/WPRE_DET_LANEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20939Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect.This field is used to restrict the receiver detect procedure to a particular lane when the default detect and polling procedure performed on all lanes cannot be successful. A notable example of when it is useful to program this field to a value different from the default, is when a lane is asymmetrically broken, that is, it is detected in Detect LTSSM state but it cannot exit Electrical Idle in Polling LTSSM state.Note: This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.15130x0R/WfalsetruefalseLANE00x0Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/2-1 or CX_NL/4-1 or CX_NL/8-1, depending on which lane is detectedLANE10x1Connect logical Lane0 to physical lane 1LANE150x4Connect logical Lane0 to physical lane 15LANE30x2Connect logical Lane0 to physical lane 3LANE70x3connect logical lane0 to physical lane 7AUTO_LANE_FLIP_CTRL_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20957Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For more details, see the 'Lane Reversal' appendix in the Databook. This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.16160x1R/WDIRECT_SPEED_CHANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr20990Directed Speed Change. Writing "1" to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed.When the speed change occurs, the controller will clear the contents of this field; and a read to this field by your software will return a "0".To manually initiate the speed change: - Write to LINK_CONTROL2_LINK_STATUS2_REG . PCIE_CAP_TARGET_LINK_SPEED in the local device - Deassert this field - Assert this fieldIf you set the default of this field using the DEFAULT_GEN2_SPEED_CHANGE configuration parameter to "1", then the speed change is initiated automatically after link up, and the controller clears the contents of this field. If you want to prevent this automatic speed change, then write a lower speed value to the Target Link Speed field of the Link Control 2 register (LINK_CONTROL2_LINK_STATUS2_OFF . PCIE_CAP_TARGET_LINK_SPEED) through the DBI before link up.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 17170x0R/WCONFIG_PHY_TX_CHANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21007Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low SwingThis field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.18180x0R/WCONFIG_TX_COMP_RXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21022Config Tx Compliance Receive Bit. When set to 1, signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to "1").This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.19190x0R/WSEL_DEEMPHASISPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21038Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dBThis field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.20200x0R/WGEN1_EI_INFERENCEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21056Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a "1" value on RxElecIdle instead of looking for a "0" on RxValid. If the PHY fails to deassert the RxValid signal in Recovery.Speed or Loopback.Active (because of corrupted EIOS for example), then EI cannot be inferred successfully in the controller by just detecting the condition RxValid=0. - 0: Use RxElecIdle signal to infer Electrical Idle - 1: Use RxValid signal to infer Electrical IdleNote: This register field is sticky.21210x0R/WRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21064Reserved for future use.23220x0RLANE_UNDER_TESTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21080The Lane Under Test is the lane for Forced Lane Flip or for Loopback Eq. The value is from 0 to CX_NL. Only one lane is configured each time. The default of this field is the CX_DEFAULT_LANE_UNDER_TEST configuration parameter.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.27240x0R/W--29280x0rFORCE_LANE_FLIPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21097Enable to force the LANE_UNDER_TEST physical lane flips to logical lane 0. All the other physical lanes are turned off. The LINK_CAPABLE register must be set to 1 and only x1 link can be formed if the FORCE_LANE_FLIP register is set to 1.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.30300x0R/WRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21105Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PHY_STATUS_OFFPHY_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr211300x110RPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PHY_STATUS_OFFPHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins.falsefalsefalsefalsePHY_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21129PHY Status. Data received directly from the phy_cfg_status bus.These is a GPIO register reflecting the values on the static phy_cfg_status input signals. The usage is left completely to the user and does not in any way influence controller functionality. You can use it for any static sideband status signalling requirements that you have for your PHY.This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.310RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PHY_CONTROL_OFFPHY_CONTROL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr211520x114R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PHY_CONTROL_OFFPHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins.falsefalsefalsefalsePHY_CONTROLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21151PHY Control. Data sent directly to the cfg_phy_control bus.These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller functionality. You can use it for any static sideband control signalling requirements that you have for your PHY.This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TRGT_MAP_CTRL_OFFTRGT_MAP_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr212110x11CR/W0x0000006fPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFFProgrammable Target Map Control Register.falsefalsefalsefalseTARGET_MAP_PFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21165Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits.500x2fR/WTARGET_MAP_ROMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21176Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits.660x1R/W--1270x0rTARGET_MAP_RESERVED_13_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21188Reserved.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: R (sticky) 15130x0RTARGET_MAP_INDEXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21198The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits.20160x00R/WTARGET_MAP_RESERVED_21_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21210Reserved.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: R (sticky) 31210x000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_ADDR_OFFMSI_CTRL_ADDR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr212310x120R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFFIntegrated MSI Reception Module (iMRM) Address Register.falsefalsefalsefalseMSI_CTRL_ADDRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21230Integrated MSI Reception Module Address. System specified address for MSI memory write transaction termination.Within the AXI Bridge, every received Memory Write request is examined to see if it targets the MSI Address that has been specified in this register; and also to see if it satisfies the definition of an MSI interrupt request. When these conditions are satisfied the Memory Write request is marked as an MSI request.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_UPPER_ADDR_OFFMSI_CTRL_UPPER_ADDR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr212470x124R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFFIntegrated MSI Reception Module Upper Address Register.falsefalsefalsefalseMSI_CTRL_UPPER_ADDRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21246Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_EN_OFFMSI_CTRL_INT_0_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr212640x128R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_0_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21263MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_MASK_OFFMSI_CTRL_INT_0_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr212820x12CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_0_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21281MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_STATUS_OFFMSI_CTRL_INT_0_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr213000x130R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_0_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21299MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_EN_OFFMSI_CTRL_INT_1_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr213170x134R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_1_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21316MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_MASK_OFFMSI_CTRL_INT_1_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr213350x138R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_1_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21334MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_STATUS_OFFMSI_CTRL_INT_1_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr213530x13CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_1_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21352MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_EN_OFFMSI_CTRL_INT_2_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr213700x140R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_2_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21369MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_MASK_OFFMSI_CTRL_INT_2_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr213880x144R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_2_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21387MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_STATUS_OFFMSI_CTRL_INT_2_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr214060x148R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_2_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21405MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_EN_OFFMSI_CTRL_INT_3_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr214230x14CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_3_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21422MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_MASK_OFFMSI_CTRL_INT_3_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr214410x150R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_3_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21440MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_STATUS_OFFMSI_CTRL_INT_3_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr214590x154R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_3_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21458MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_EN_OFFMSI_CTRL_INT_4_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr214760x158R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_4_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21475MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_MASK_OFFMSI_CTRL_INT_4_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr214940x15CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_4_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21493MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_STATUS_OFFMSI_CTRL_INT_4_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr215120x160R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_4_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21511MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_EN_OFFMSI_CTRL_INT_5_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr215290x164R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_5_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21528MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_MASK_OFFMSI_CTRL_INT_5_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr215470x168R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_5_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21546MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_STATUS_OFFMSI_CTRL_INT_5_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr215650x16CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_5_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21564MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_EN_OFFMSI_CTRL_INT_6_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr215820x170R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_6_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21581MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_MASK_OFFMSI_CTRL_INT_6_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr216000x174R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_6_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21599MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_STATUS_OFFMSI_CTRL_INT_6_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr216180x178R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_6_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21617MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_EN_OFFMSI_CTRL_INT_7_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr216350x17CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_7_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21634MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_MASK_OFFMSI_CTRL_INT_7_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr216530x180R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_7_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21652MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_STATUS_OFFMSI_CTRL_INT_7_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr216710x184R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_7_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21670MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_GPIO_IO_OFFMSI_GPIO_IO_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr216850x188R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_GPIO_IO_OFFIntegrated MSI Reception Module General Purpose IO Register.falsefalsefalsefalseMSI_GPIO_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21684MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0]Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.CLOCK_GATING_CTRL_OFFCLOCK_GATING_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr217530x18CR/W0x00000003PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFFThis register enables you to disable dynamic clock gating. By default dynamic clock gating is on, allowing the controller to autonomously enable and disable its clocks. The clock gating is performed in the clock and reset module, DWC_pcie_clk_rst.v, and is initiated by the controllers clock enable signals. The following modules support dynamic clock gating: - AXI Bridge - RADMfalsefalsefalsefalseRADM_CLK_GATING_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21717RADM Clock Gating Enable. This register, if set, enables the RADM to autonomously enable and disable its clock. The DWC_pcie_clk_rst.v module provides the gated clock, radm_clk_g, to the RADM and is enabled when the controllers clock enable signal, en_radm_clk_g, is asserted. The RADM clock is a gated version of the controller clock, core_clk. The controller de-asserts en_radm_clk_g when there is no Rx traffic, Rx queues and pre/post-queue pipelines are empty, RADM completion LUT is empty, and there are no FLR actions pending. - 0: Disable - 1: Enable (default)Note: This register field is sticky.000x1R/WAXI_CLK_GATING_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21744AXI Clock Gating Enable. This register enables the AXI Bridge to autonomously enable and disable the AXI Master clock, the AXI Slave clock and the AXI DBI slave clock. The DWC_pcie_clk_rst.v module provides the gated clock, mstr_axi_aclk_gated, to the AXI Bridge and is enabled when the controllers clock enable signal, mstr_aclk_active, is asserted. For the AXI Slave this module provides the gated clock, slv_axi_aclk_gated, to the AXI Bridge and is enabled when the controllers clock enable signal, slv_aclk_active, is asserted. If the AXI DBI Slave is enabled (DBI_4SLAVE_POPULATED=1) the module provides the gated clock, dbi_axi_aclk_gated, to the AXI Bridge and is enabled when the controllers clock enable signal, dbi_aclk_active, is asserted. The controller de-asserts the clock enable signals when the respective AXI Master/Slave interfaces are idle. - 0: Disable - 1: Enable (default)Note: This register field is sticky.110x1R/WRSVDP_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21752Reserved for future use.3120x00000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN3_RELATED_OFFGEN3_RELATED_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr220980x190R/W0x00402001PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_GEN3_RELATED_OFFGen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the "Link Width and Speed Change Control Register" is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific "Directed Speed Change" field. The "Directed Speed Change" field in the "Link Width and Speed Change Control Register" is used to change to Gen2 or Gen3 speed. A speed change to Gen3 occurs if (1) the "Directed Speed Change" field is set to "1" and (2) the "Target Link Speed" field in the Link Control 2 Register is set to Gen3. Gen3 support is advertised by both sides of the link during link training.M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist.falsefalsefalsefalseGEN3_ZRXDC_NONCOMPLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21788Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the following LTSSM states: Polling, Rx_L0s, L1, L2, and Disabled. - 0: The receiver complies with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher. - 1: The receiver does not comply with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rates.Note: This register field is sticky.000x1R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21796Reserved for future use.710x00RDISABLE_SCRAMBLER_GEN_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21811Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller (for example within the PHY).Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.880x0R/WEQ_PHASE_2_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21832Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description Note: This register field is sticky.990x0R/WEQ_EIEOS_CNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21846Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.10100x0R/WEQ_REDOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21866Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. The received presets or coefficients mismatch in Recovery.RcvrLock after Recovery EQ phases causes the EQ redo requests. If the EQ redo is infinite or you do not want eq requests and redo, setting this bit to 1 will stop the EQ requests and EQ redo so that the link can go ahead to L0 state for packet trasmissions.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.11110x0R/WRXEQ_PH01_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21897Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be performed by the PHY. This bit is used during Virtex-7 Gen3 equalization. The programmable bits [RXEQ_PH01_EN, EQ_PHASE_2_3] can be used to obtain the following variations of the equalization procedure: - 00: Tx equalization only in phase 2/3 - 01: No Tx equalization, no Rx equalization - 10: Tx equalization in phase 2/3, Rx equalization in phase 0/1 - 11: No Tx equalization, Rx equalization in phase 0/1Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description Note: This register field is sticky.12120x0R/WRXEQ_RGRDLESS_RXTSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21923When set to '1', the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from remote partner. - 1: mac_phy_rxeqeval asserts after 500ns regardless of TS's received or not.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description Note: This register field is sticky.13130x1R/WRSVDP_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21931Reserved for future use.15140x0RGEN3_EQUALIZATION_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21945Equalization Disable. Disable equalization feature. This bit cannot be changed once the LTSSM starts link training.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.16160x0R/WGEN3_DLLP_XMT_DELAY_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21959DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.17170x0R/WGEN3_DC_BALANCE_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21971DC Balance Disable. Disable DC Balance feature.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.18180x0R/WRSVDP_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_SETDWC_pcie_dbi_cpcie_usp_4x8.csr21979Reserved for future use.20190x0RAUTO_EQ_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22006Autonomous Equalization Disable. When the controller is in L0 state at Gen3 data rate and equalization was completed successfully in Autonomous EQ Mechanism, setting this bit in DSP will not direct the controller to Recovery state to perform Gen4 equalization. Link stays in Gen3 rate and DSP sends DLLPs to USP. If the bit is 0, DSP will block DLLPs and direct the link to perform Gen4 EQ in Autonomous Mechanism.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is RSVD. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description Note: This register field is sticky.21210x0R/WUSP_SEND_8GT_EQ_TS2_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22033Upstream Port Send 8GT/s or 16GT/s EQ TS2 Disable. The base spec defines that USP can optionally send 8GT or 16GT EQ TS2 and it means USP can set DSP TxPreset value in Gen4 or Gen5 Data Rate. If this register set to 0, USP sends 8GT or 16GT EQ TS2. If this register set to 1, USP does not send 8GT or 16GT EQ TS2. This applies to upstream ports only. No Function for downstream ports.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is RSVD. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. Value after reset in Gen4/Gen5 is 0x1.Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description Note: This register field is sticky.22220x1R/WGEN3_EQ_INVREQ_EVAL_DIFF_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22048Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.23230x0R/WRATE_SHADOW_SELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22089Rate Shadow Select. This register value decide the Data Rate of shadow register. - 00b: Gen3 Data Rate is selected for shadow register. - 01b: Gen4 Data Rate is selected for shadow register. - 10b: Gen5 Data Rate is selected for shadow register. - 11b: Reserved.The following shadow registers are controlled by this register. - GEN3_RELATED_OFF[9] EQ_PHASE_2_3 - GEN3_RELATED_OFF[12] RXEQ_PH01_EN - GEN3_RELATED_OFF[19] RE_EQ_REQUEST_ENABLE - GEN3_RELATED_OFF[21] AUTO_EQ_DISABLE - GEN3_RELATED_OFF[22] USP_SEND_8GT_EQ_TS2_DISABLE - GEN3_EQ_LOCAL_FS_LF_OFF[5:0] GEN3_EQ_LOCAL_LF - GEN3_EQ_LOCAL_FS_LF_OFF[11:6] GEN3_EQ_LOCAL_FS - GEN3_EQ_PSET_COEFF_MAP_0[5:0] GEN3_EQ_PRE_CURSOR_PSET - GEN3_EQ_PSET_COEFF_MAP_0[11:6] GEN3_EQ_CURSOR_PSET - GEN3_EQ_PSET_COEFF_MAP_0[17:12] GEN3_EQ_POSET_CURSOR_PSET - GEN3_EQ_CONTROL_OFF[3:0] GEN3_EQ_FB_MODE - GEN3_EQ_CONTROL_OFF[4] GEN3_EQ_PHASE23_EXIT_MODE - GEN3_EQ_CONTROL_OFF[5] GEN3_EQ_EVAL_2MS_DISABLE - GEN3_EQ_CONTROL_OFF[23:8] GEN3_EQ_PSET_REQ_VEC - GEN3_EQ_CONTROL_OFF[24] GEN3_EQ_FOM_INC_INITIAL_EVAL - GEN3_EQ_CONTROL_OFF[25] GEN3_EQ_PSET_REQ_AS_COEF - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[4:0] GEN3_EQ_FMDC_T_MIN_PHASE23 - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[9:5] GEN3_EQ_FMDC_N_EVALS - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[13:10] GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[17:14] GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTANote: This register field is sticky.25240x0R/WRSVDP_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22097Reserved for future use.31260x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN3_EQ_CONTROL_OFFGEN3_EQ_CONTROL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr223300x1A8R/W0x05039f71PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFFGen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP), or Phase3 in a downstream port (DSP).M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist.falsefalsefalsefalseGEN3_EQ_FB_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22126Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - .....: Reserved - 1111b: ReservedNote: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is a shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.300x1R/WGEN3_EQ_PHASE23_EXIT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22173Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3When optimal settings are not found then: - Equalization Phase 2 Successful status bit is not set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 0 - Equalization Phase 2 Successful status bit is set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 1 - Equalization Phase 2 Complete status bit is set in the "Link Status Register 2"For a DSP: Determine next LTSSM state from Phase3 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.RcvrLockWhen optimal settings are not found then: - Equalization Phase 3 Successful status bit is not set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 0 - Equalization Phase 3 Successful status bit is set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 1 - Equalization Phase 3 Complete status bit is set in the "Link Status Register 2"Note: GEN3_EQ_PHASE23_EXIT_MODE = 1 affects Direction Change feed back mode. EQ requests for Figure Of Merit mode complete before 24 ms timeout. Please see GEN3_EQ_PSET_REQ_VEC Register for more.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.440x1R/WGEN3_EQ_EVAL_2MS_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22197Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation, stop any attempt to modify the remote transmitter settings, Phase2 is terminated by the 24ms timeout - 1: ignore the 2ms timeout and continue as normal. This is used to support PHYs that require more than 2ms to respond to the assertion of RxEqEval.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.550x1R/WGEN3_LOWER_RATE_EQ_REDO_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22211Support EQ redo and lower rate change: - 0: not support - 1: supportNote: Gen3 and Gen4 share the same register bit and have the same feature.Note: This register field is sticky.660x1R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22219Reserved for future use.770x0RGEN3_EQ_PSET_REQ_VECPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22274Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: "Preset=i" is requested and evaluated in EQ Master Phase. - 0000000000000000: No preset be requested and evaluated in EQ Master Phase - 000000xxxxxxxxx1: Preset 0 is requested and evaluated in EQ Master Phase - 000000xxxxxxxx1x: Preset 1 is requested and evaluated in EQ Master Phase - 000000xxxxxxx1xx: Preset 2 is requested and evaluated in EQ Master Phase - 000000xxxxxx1xxx: Preset 3 is requested and evaluated in EQ Master Phase - 000000xxxxx1xxxx: Preset 4 is requested and evaluated in EQ Master Phase - 000000xxxx1xxxxx: Preset 5 is requested and evaluated in EQ Master Phase - 000000xxx1xxxxxx: Preset 6 is requested and evaluated in EQ Master Phase - 000000xx1xxxxxxx: Preset 7 is requested and evaluated in EQ Master Phase - 000000x1xxxxxxxx: Preset 8 is requested and evaluated in EQ Master Phase - 00000x1xxxxxxxxx: Preset 9 is requested and evaluated in EQ Master Phase - 000001xxxxxxxxxx: Preset 10 is requested and evaluated in EQ Master Phase - All other encodings: ReservedNote: You must contact your PHY vendor to ensure 24 ms timeout does not occur in presets requests in EQ master phase, i.e., you must set a proper value to the GEN3_EQ_PSET_REQ_VEC register so that the EQ tunning for Figure of Merit in the EQ master phase completes before 24 ms timeout.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.2380x039fR/WGEN3_EQ_FOM_INC_INITIAL_EVALPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22294Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master, when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: IncludeNote: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.24240x1R/WGEN3_EQ_PSET_REQ_AS_COEFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22305GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use.Note: This register field is sticky.25250x0R/WGEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22321Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: requestNote: Gen3 and Gen4 share the same register bit and have the same feature.Note: This register field is sticky.26260x1R/WRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22329Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN3_EQ_FB_MODE_DIR_CHANGE_OFFGEN3_EQ_FB_MODE_DIR_CHANGE_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr224360x1ACR/W0x00000040PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFFGen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP), when you set the Feedback Mode in "Gen3 EQ Control Register" to "Direction Change." These fields allow control over the initial starting point for the search of optimal coefficient settings, and allow control over the criteria used to determine when the optimal settings have been achieved. The values are applied to all the lanes.falsefalsefalsefalseGEN3_EQ_FMDC_T_MIN_PHASE23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22361Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time, before starting to check for convergence of the coefficients.Allowed values 0,1,...,24.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.400x00R/WGEN3_EQ_FMDC_N_EVALSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22388Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found.Allowed range: 0,1,2,..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH.When set to 0, EQ Master is performed without sending any requests to the remote partner in Phase 2 for USP and Phase 3 for DSP. Therefore, the remote partner will not change its transmitter coefficients and will move to the next state.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.950x02R/WGEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22408Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth.Allowed range: 0,1,2,..15.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.13100x0R/WGEN3_EQ_FMDC_MAX_POST_CUSROR_DELTAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22427Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0,1,2,..15.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.17140x0R/WRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22435Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.ORDER_RULE_CTRL_OFFORDER_RULE_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr224700x1B4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFFOrder Rule Control Register.falsefalsefalsefalseNP_PASS_PPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22450Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P700x00R/WCPL_PASS_PPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22461Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P1580x00R/WRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22469Reserved for future use.31160x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PIPE_LOOPBACK_CONTROL_OFFPIPE_LOOPBACK_CONTROL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr225260x1B8R/W0x000000ffPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFFPIPE Loopback Control Register.falsefalsefalsefalseLPBK_RXVALIDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22482LPBK_RXVALID is an internally reserved field. Do not use.Note: This register field is sticky.1500x00ffR/WRXSTATUS_LANEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22491RXSTATUS_LANE is an internally reserved field. Do not use.Note: This register field is sticky.21160x00R/WRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22499Reserved for future use.23220x0RRXSTATUS_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22508RXSTATUS_VALUE is an internally reserved field. Do not use.2624WRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22516Reserved for future use.30270x0RPIPE_LOOPBACKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22525PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MISC_CONTROL_1_OFFMISC_CONTROL_1_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr227200x1BCR/W0x0007ff48PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MISC_CONTROL_1_OFFDBI Read-Only Write Enable Register.falsefalsefalsefalseDBI_RO_WR_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22544Write to RO Registers Using DBI. Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'.For more details, see "Writing to Read-Only Registers" in "Register Module, LBC, and DBI" section in the "Controller Operations" chapter of the Databook.Note: This register field is sticky.000x0R/WDEFAULT_TARGETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22565Default target for an IO or MEM request with UR/CA/CRS received. Based on the value of this field the controller either drops or forwards these requests to your application. - 0: The controller drops all incoming I/O or MEM requests (after corresponding error reporting). A completion with UR status is generated for non-posted requests. - 1: The controller forwards all incoming I/O or MEM requests with UR/CA/CRS status to your application.For more details, see "ECRC Handling" and "Request TLP Routing Rules" in "Receive Routing" section of the "Controller Operations" chapter of the Databook.Note: This register field is sticky.110x0R/WUR_CA_MASK_4_TRGT1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22579When this field is set to '1', the controller suppresses error logging, error message generation, and CPL generation for non-posted requests TLPs (with UR filtering status) forwarded to your application (that is, when DEFAULT_TARGET =1). For more details, see "Advanced Error Handling For Received TLPs" chapter of the Databook.Note: This register field is sticky.220x0R/WSIMPLIFIED_REPLAY_TIMERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22598Enables Simplified Replay Timer (Gen4). For more details, see "Transmit Replay" in "Transmit TLP Processing" section in the "Controller Operations" chapter of the Databook.Simplified Replay Timer can have the following Values: - A value from 24,000 to 31,000 Symbol Times when Extended Synch is 0b. - A value from 80,000 to 100,000 Symbol Times when Extended Synch is 1b.The Simplified Replay Timer value must not be changed while the link is in use.Note: This register field is sticky.330x1R/WDISABLE_AUTO_LTR_CLR_MSGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22616Disable the autonomous generation of LTR clear message in upstream port. This field can have the following values: - 0: Allow the autonomous generation of LTR clear message. - 1: Disable the autonomous generation of LTR clear message.For more details, see "Latency Tolerance Reporting (LTR) Message Generation[EP Mode]" in "Message Generation" section of the "Controller Operations" chapter of the Databook.Note: This register field is sticky.440x0R/WARI_DEVICE_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22626When ARI is enabled, this field enables use of the device ID.Note: This register field is sticky.550x0R/WCPLQ_MNG_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22636This field enables the Completion Queue Management feature.Note: This register field is sticky.660x1R/WCFG_TLP_BYPASS_EN_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22655Setting of this field defines which field TARGET_ABOVE_CONFIG_LIMIT_REG or CONFIG_LIMIT_REG decides the destination of Configuration requests. This field can have the following values: - 0: Configuration TLPs are routed according to the setting of TARGET_ABOVE_CONFIG_LIMIT_REG - 1: Configuration TLPs are routed according to the setting of CONFIG_LIMIT_REGNote: When app_req_retry_en is asserted, the setting of this field is ignored.Note: This register field is sticky.770x0R/WCONFIG_LIMIT_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22676Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. - Configuration requests with an address less CONFIG_LIMIT_REG are directed to the CDM - Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of TARGET_ABOVE_CONFIG_LIMIT_REG field.Your application must set a proper value for this field based on your extended configuration registers. For more details, see the "CDM/ELBI Register Space Access Through CFG Request" in "Register Module, LBC, and DBI" section in the "Controller Operations" chapter of the Databook.Note: This register field is sticky.1780x3ffR/WTARGET_ABOVE_CONFIG_LIMIT_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22689Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of this field. This field can have the following values: - 1: ELBI - 2: TRGT1Note: This register field is sticky.19180x1R/WP2P_TRACK_CPL_TO_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22700Determines whether to enable Peer to Peer (P2P) error reporting. - 0: Disable P2P error reporting - 1: Enable P2P error reportingNote: This register field is sticky.20200x0R/WP2P_ERR_RPT_CTRLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22711Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode. - 0: Do not track completion - 1: Track completionNote: This register field is sticky.21210x0R/WRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22719Reserved for future use.31220x000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MULTI_LANE_CONTROL_OFFMULTI_LANE_CONTROL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr227940x1C0R/W0x00000080PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFFUpConfigure Multi-lane Control Register.Used when upsizing or downsizing the link width through Configuration state without bringing the link down.For more details, see the "Link Establishment" section in the "ControllerOperations" chapter of the Databook.falsefalsefalsefalseTARGET_LINK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22747Target Link Width.Values correspond to: - 6'b000000: Controller does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 - 6'b100000: x32This field is reserved (fixed to '0') for M-PCIe.500x00R/WDIRECT_LINK_WIDTH_CHANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22770Directed Link Width Change.The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in LINK_CONTROL_LINK_STATUS_REG is '0', the controller starts upconfigure or autonomous width downsizing (to the TARGET_LINK_WIDTH value) in the Configuration state. - If TARGET_LINK_WIDTH value is 0x0, the controller does not start upconfigure or autonomous width downsizing in the Configuration state.The controller self-clears this field when the controller accepts this request.This field is reserved (fixed to '0') for M-PCIe.660x0R/WUPCONFIGURE_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22785Upconfigure Support.The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state.This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.770x1R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22793Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PHY_INTEROP_CTRL_OFFPHY_INTEROP_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr229100x1C4R/W0x00000a44PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFFPHY Interoperability Control Register.falsefalsefalsefalseRXSTANDBY_CONTROLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22823Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. This field is reserved for internal use.You should not write to this field and change the default unless specifically instructed by Synopsys support. - [0]: Rx EIOS and subsequent T TX-IDLE-MIN - [1]: Rate Change - [2]: Inactive lane for upconfigure/downconfigure - [3]: PowerDown=P1orP2 - [4]: RxL0s.Idle - [5]: EI Infer in L0 - [6]: Execute RxStandby/RxStandbyStatus HandshakeThis field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.600x44R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22831Reserved for future use.770x0RL1SUB_EXIT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22848L1 Exit Control Using phy_mac_pclkack_n. This field is reserved for internal use.You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller exits L1 without waiting for the PHY to assert phy_mac_pclkack_n. - 0: Controller waits for the PHY to assert phy_mac_pclkack_n before exiting L1.Note: This register field is sticky.880x0R/WL1_NOWAIT_P1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22869L1 entry control bit. This field is reserved for internal use.You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not wait for PHY to acknowledge transition to P1 before entering L1. - 0: Controller waits for the PHY to acknowledge transition to P1 before entering L1.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.990x1RL1_CLK_SELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22886L1 Clock control bit. This field is reserved for internal use.You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not request aux_clk switch and core_clk gating in L1. - 0: Controller requests aux_clk switch and core_clk gating in L1.Note: This register field is sticky.10100x0R/WP2NOBEACON_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22901P2.NoBeacon Enable bit. - 1: Controller drives P2.NoBeacon encoding for PHY power down state, when the link goes to L2. - 0: Controller drives P2 encoding for PHY power down state, when the link goes to L2.Note:This field is reserved (fixed to '0') if CX_P2NOBEACON_ENABLE is not set.Note: This register field is sticky.11110x1R/WRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22909Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TRGT_CPL_LUT_DELETE_ENTRY_OFFTRGT_CPL_LUT_DELETE_ENTRY_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr229460x1C8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFFTRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion because of an FLR or any other reason.Note:: The target completion LUT (and associated target completion timeout event) is watching for completions (from your application on XALI0/1/2 or AXI master read channel) corresponding to previously received non-posted requests from the PCIe wire.falsefalsefalsefalseLOOK_UP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22932This number selects one entry to delete of the TRGT_CPL_LUT.3000x00000000R/WDELETE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22945This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field.This is a self-clearing register field. Reading from this register field always returns a '0'.31310x0WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.LINK_FLUSH_CONTROL_OFFLINK_FLUSH_CONTROL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr229920x1CCR/W0xff000001PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFFLink Reset Request Flush Control Register.falsefalsefalsefalseAUTO_FLUSH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22974Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge.The flushing process is initiated if any of the following events occur: - Hot reset request. A downstream port (DSP) can "hot reset" an upstream port (USP) by sending two consecutive TS1 ordered sets with the hot reset bit asserted. - Warm (Soft) reset request. Generated when exiting from D3 to D0 and cfg_pm_no_soft_rst=0. - Link down reset request. A high to low transition on smlh_req_rst_not indicates the link has gone down and the controller is requesting a reset.If you disable automatic flushing, your application is responsible for resetting the PCIe controller and the AXI Bridge. For more details see "Warm and Hot Resets" section in the Architecture chapter of the Databook.Note: This register field is sticky.000x1R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22982Reserved for future use.2310x000000RRSVD_I_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr22991This is an internally reserved field. Do not use.Note: This register field is sticky.31240xffR/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AMBA_ERROR_RESPONSE_DEFAULT_OFFAMBA_ERROR_RESPONSE_DEFAULT_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr23122AXI Bridge Slave Error Response Register.0x1D0R/W0x00009c00PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFFAXI Bridge Slave Error Response Register.falsefalsefalsefalseAMBA_ERROR_RESPONSE_GLOBALPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23021Global Slave Error Response Mapping. Determines the AXI slave response for all error scenarios on non-posted requests. For more details see "Error Handling" in the AXI chapter of the Databook.AHB: - 0: OKAY (with FFFF data for non-posted requests) and ignore the setting in bit [2] of this register. - 1: ERROR for normal link (data) accesses and look at bit [2] for other scenarios.AXI: - 0: OKAY (with FFFF data for non-posted requests) - 1: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping)The error response mapping is not applicable to Non-existent Vendor ID register reads.Note: This register field is sticky.000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23029Reserved for future use.110x0RAMBA_ERROR_RESPONSE_VENDORIDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23048Vendor ID Non-existent Slave Error Response Mapping. Determines the AXI slave response for errors on reads to non-existent Vendor ID register. For more details see "Error Handling" in the AXI chapter of the Databook.AHB: - 0: OKAY (with FFFF data). The controller ignores the setting in the bit when bit 0 of this register is '0'. - 1: ERRORAXI: - 0: OKAY (with FFFF data). - 1: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping)Note: This register field is sticky.220x0R/WAMBA_ERROR_RESPONSE_CRSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23070CRS Slave Error Response Mapping. Determines the AXI slave response for CRS completions. For more details see "Error Handling" in the AXI chapter of the Databook.AHB: - always returns OKAYAXI: - 00: OKAY - 01: OKAY with all FFFF_FFFF data for all CRS completions - 10: OKAY with FFFF_0001 data for CRS completions to vendor ID read requests, OKAY with FFFF_FFFF data for all other CRS completions - 11: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping)Note: This register field is sticky.430x0R/WRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23078Reserved for future use.950x00RAMBA_ERROR_RESPONSE_MAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23113AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses, slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is always mapped to OKAY. - [0] -- 0: UR (unsupported request) -> DECERR -- 1: UR (unsupported request) -> SLVERR - [1] -- 0: CRS (configuration retry status) -> DECERR -- 1: CRS (configuration retry status) -> SLVERR - [2] -- 0: CA (completer abort) -> DECERR -- 1: CA (completer abort) -> SLVERR - [3]: Reserved - [4]: Reserved - [5]: -- 0: Completion Timeout -> DECERR -- 1: Completion Timeout -> SLVERRThe AXI bridge internally drops (processes internally but not passed to your application) a completion that has been marked by the Rx filter as UC or MLF, and does not pass its status directly down to the slave interface. It waits for a timeout and then signals "Completion Timeout" to the slave interface.The controller sets the AXI slave read databus to 0xFFFF for all error responses.Note: This register field is sticky.15100x27R/WRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23121Reserved for future use.31160x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AMBA_LINK_TIMEOUT_OFFAMBA_LINK_TIMEOUT_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr231690x1D4R/W0x00000032PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFFLink Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational, the controller starts a "flush" timer. The timeout value of the timer is set by this register. If the timer times out before the PCIe link is operational, the bridge TX request queues are flushed. For more details, see the "AXI Bridge Initialization, Clocking and Reset" section in the AXI chapter of the Databook.falsefalsefalsefalseLINK_TIMEOUT_PERIOD_DEFAULTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23150Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not transmitting any of these requests.The timer is clocked by core_clk. For an M-PCIe configuration: - Time unit of this field is 4 ms. - Margin of error for RateA clock is < 1%. - Margin of error for RateB clock is between 16% and 17%.Note: This register field is sticky.700x32R/WLINK_TIMEOUT_ENABLE_DEFAULTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23160Disable Flush. You can disable the flush feature by setting this field to "1".Note: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23168Reserved for future use.3190x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AMBA_ORDERING_CTRL_OFFAMBA_ORDERING_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr232790x1D8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFFAMBA Ordering Control.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23180Reserved for future use.000x0RAX_SNP_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23194AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR and WAW hazards at the remote link partner. For more details, see the "Optional Serialization of AXI Slave Non-posted Requests" section in the AXI chapter of the Databook.110x0R/WRSVDP_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23202Reserved for future use.220x0RAX_MSTR_ORDR_P_EVENT_SELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23246AXI Master Posted Ordering Event Selector. This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule, "NP must not pass P" at the AXI Master Interface.The AXI protocol does not support ordering between channels. Therefore, NP reads can pass P on your AXI bus fabric. This can result in an ordering violation when the read overtakes a P that is going to the same address. Therefore, the bridge master does not issue any NP requests until all outstanding P writes reach their destination. It does this by waiting for the all of the write responses on the B channel. This can affect the performance of the master read channel.For scenarios where the interconnect serializes the AXI master "AW", "W" and "AR" channels,you can increase the performance by reducing the need to wait until the complete Posted transaction has effectively reached the application slave. - 00: B'last event: wait for the all of the write responses on the B channel thereby ensuring that the complete Posted transaction has effectively reached the application slave (default). - 01: AW'last event: wait until the complete Posted transaction has left the AXI address channel at the bridge master. - 10: W'last event: wait until the complete Posted transaction has left the AXI data channel at the bridge master. - 11: ReservedNote 2: This setting will not affect: - MSI interrupt catcher and P data ordering. This is always driven by the B'last event. - DMA read engine TLP ordering. This is always driven by the B'last event. - NP write transactions which are always serialized with P write transactions.430x0R/WRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23254Reserved for future use.650x0RAX_MSTR_ZEROLREAD_FWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23270AXI Master Zero Length Read Forward to the application. The DW PCIe controller AXI bridge is able to terminate in order with the Posted transactions the zero length read, implementing the PCIe express flush semantics of the Posted transactions. - 0x0: The zero length Read is terminated at the DW PCIe AXI bridge master - 0x1: The zero length Read is forward to the application.770x0R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23278Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_1_OFFCOHERENCY_CONTROL_1_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr233160x1E0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFFACE Cache Coherency Control Register 1falsefalsefalsefalseCFG_MEMTYPE_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23293Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = PeripheralNote: This register field is sticky.000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23301Reserved for future use.110x0RCFG_MEMTYPE_BOUNDARY_LOW_ADDRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23315Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are "00". Addresses up to but not including this value are in the lower address space region; addresses equal or greater than this value are in the upper address space region.Note: This register field is sticky.3120x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_2_OFFCOHERENCY_CONTROL_2_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr233310x1E4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFFACE Cache Coherency Control Register 2falsefalsefalsefalseCFG_MEMTYPE_BOUNDARY_HIGH_ADDRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23330Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_3_OFFCOHERENCY_CONTROL_3_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr233890x1E8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFFACE Cache Coherency Control Register 3falsefalsefalsefalse--200x0rCFG_MSTR_ARCACHE_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23347Master Read CACHE Signal Behavior.Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE fieldNote: This register field is sticky.630x0R/W--1070x0rCFG_MSTR_AWCACHE_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23363Master Write CACHE Signal Behavior.Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE fieldNote: for message requests the value of mstr_awcache is always "0000" regardless of the value of this bitNote: This register field is sticky.14110x0R/W--18150x0rCFG_MSTR_ARCACHE_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23374Master Read CACHE Signal Value.Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'.Note: This register field is sticky.22190x0R/W--26230x0rCFG_MSTR_AWCACHE_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23388Master Write CACHE Signal Value.Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'.Note: not applicable to message requests; for message requests the value of mstr_awcache is always "0000"Note: This register field is sticky.30270x0R/W--31310x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_LOW_OFFAXI_MSTR_MSG_ADDR_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr234220x1F0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFFLower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases, the third and fourth DWORDs of a message (Msg/MsgD) TLP header were delivered though the AXI master address bus (mstr_awaddr). These DWORDS are now supplied through the mstr_awmisc_info_hdr_34dw[63:0] output; and the value on mstr_awaddr is driven to the value you have programmed into the AXI_MSTR_MSG_ADDR_LOW_OFF and AXI_MSTR_MSG_ADDR_HIGH_OFF registers.falsefalsefalsefalseCFG_AXIMSTR_MSG_ADDR_LOW_RESERVEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23411Reserved for future use.Note: This register field is sticky.1100x000RCFG_AXIMSTR_MSG_ADDR_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23421Lower 20 bits of the programmable AXI address for Messages.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_HIGH_OFFAXI_MSTR_MSG_ADDR_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr234370x1F4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFFUpper 32 bits of the programmable AXI address where Messages coming from wire are mapped to.falsefalsefalsefalseCFG_AXIMSTR_MSG_ADDR_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23436Upper 32 bits of the programmable AXI address for Messages.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_NUMBER_OFFPCIE_VERSION_NUMBER_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr234620x1F8R0x3533302aPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFFPCIe Controller IIP Release Version Number. The version number is given inhex format. You should convert each pair of hex characters to ASCII to interpret.Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x67612a2a which translates to ga**Using 4.70a-ea01 as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x65613031 which translates to ea01GA is a general release available on www.designware.comEA is an early release available on a per-customer basis.falsefalsefalsefalseVERSION_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23461Version Number.3100x3533302aRregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_TYPE_OFFPCIE_VERSION_TYPE_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr234870x1FCR0x6c703038PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFFPCIe Controller IIP Release Version Type. The type is given inhex format. You should convert each pair of hex characters to ASCII to interpret.Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x67612a2a which translates to ga**Using 4.70a-ea01 as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x65613031 which translates to ea01GA is a general release available on www.designware.comEA is an early release available on a per-customer basis.falsefalsefalsefalseVERSION_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23486Version Type.3100x6c703038RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_LOW_OFFMSIX_ADDRESS_MATCH_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr235290x240R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFFMSI-X Address Match Low Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more details, see the Interrupts section in the "Controller Operations" chapter of the Databook. This register is only used in AXI configurations. When your local AXI application writes (MWr) to the address defined in this register (and MSIX_ADDRESS_MATCH_HIGH_OFF), the controller will load the MSIX_DOORBELL_OFF register with the contents of the MWr and subsequently create and send MSI-X TLPsfalsefalsefalsefalseMSIX_ADDRESS_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23509MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present.Note: This register field is sticky.000x0R/WMSIX_ADDRESS_MATCH_RESERVED_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23519Reserved.Note: This register field is sticky.110x0RMSIX_ADDRESS_MATCH_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23528MSI-X Address Match Low Address.Note: This register field is sticky.3120x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_HIGH_OFFMSIX_ADDRESS_MATCH_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr235510x244R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFFMSI-X Address Match High Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more details, see the Interrupts section in the "Controller Operations" chapter of the Databook. This register is only used in AXI configurations. When your local AXI application writes (MWr) to the address defined in this register (and MSIX_ADDRESS_MATCH_LOW_OFF), the controller will load the MSIX_DOORBELL_OFF register with the contents of the MWr and subsequently create and send MSI-X TLPsfalsefalsefalsefalseMSIX_ADDRESS_MATCH_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23550MSI-X Address Match High Address.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSIX_DOORBELL_OFFMSIX_DOORBELL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr236250x248W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSIX_DOORBELL_OFFMSI-X Doorbell Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more details, see the Interrupts section in the "Controller Operations" chapter of the Databook. - For AXI configurations: when your local application writes (MWr) to the address defined in MSIX_ADDRESS_MATCH_LOW_OFF, the controller will load this register with the contents of the MWr and subsequently create and send MSI-X TLPs. - For AHB configurations: the MSI-X Table RAM feature is not supported. - For non-AMBA configurations: when your local application writes to this register, the controller will create and send MSI-X TLPs.falsefalsefalsefalseMSIX_DOORBELL_VECTORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23576MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for.1000x000WMSIX_DOORBELL_RESERVED_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23583Reserved.11110x0WMSIX_DOORBELL_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23592MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X transaction with.14120x0WMSIX_DOORBELL_VF_ACTIVEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23601MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to generate the MSI-X transaction.15150x0WMSIX_DOORBELL_VFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23609MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction.23160x00WMSIX_DOORBELL_PFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23617MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X transaction.28240x00WMSIX_DOORBELL_RESERVED_29_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23624Reserved.31290x0WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSIX_RAM_CTRL_OFFMSIX_RAM_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr237630x24CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFFMSI-X RAM power mode and debug control register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more details, see the Interrupts section in the "Controller Operations" chapter of the Databook.falsefalsefalsefalseMSIX_RAM_CTRL_TABLE_DSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23643MSIX Table RAM Deep Sleep. Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode.Note: This register field is sticky.000x0R/WMSIX_RAM_CTRL_TABLE_SDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23654MSIX Table RAM Shut Down. Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode.Note: This register field is sticky.110x0R/WMSIX_RAM_CTRL_RESERVED_2_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23664Reserved.Note: This register field is sticky.720x00RMSIX_RAM_CTRL_PBA_DSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23675MSIX PBA RAM Deep Sleep. Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode.Note: This register field is sticky.880x0R/WMSIX_RAM_CTRL_PBA_SDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23686MSIX PBA RAM Shut Down. Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode.Note: This register field is sticky.990x0R/WMSIX_RAM_CTRL_RESERVED_10_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23696Reserved.Note: This register field is sticky.15100x00RMSIX_RAM_CTRL_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23712MSIX RAM Control Bypass. The bypass field, when set, disables the internal generation of low power signals for both RAMs.It is up to the application to ensure the RAMs are in the proper power state before trying to access them. Moreover, the application needs to observe all timing requirements of the RAM low power signals before trying to use the MSIX functionality.Note: This register field is sticky.16160x0R/WMSIX_RAM_CTRL_RESERVED_17_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23722Reserved.Note: This register field is sticky.23170x00RMSIX_RAM_CTRL_DBG_TABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23737MSIX Table RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the Table. Use can also use the dbg_table input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into the RAM and maps the entire table linearly from the base address of the BAR (indicated by the BIR) in function 0.Note: This register field is sticky.24240x0R/WMSIX_RAM_CTRL_DBG_PBAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23752MSIX PBA RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the PBA. Use can also use the dbg_pba input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into the RAM and maps the entire table linearly from the base address of the BAR (indicated by the BIR) in function 0.Note: This register field is sticky.25250x0R/WMSIX_RAM_CTRL_RESERVED_26_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23762Reserved.Note: This register field is sticky.31260x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PL_LTR_LATENCY_OFFPL_LTR_LATENCY_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr238570x430R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFFLTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port, the register fields capture the corresponding fields in the LTR messages that are transmitted by the port. For a downstream port, the register fields capture the corresponding fields in the LTR messages that are received by the port. The full content of the register is reflected on the app_ltr_latency[31:0] output.falsefalsefalsefalseSNOOP_LATENCY_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23785Snoop Latency Value.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R/W 900x000R/WSNOOP_LATENCY_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23796Snoop Latency Scale.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R/W 12100x0R/WRSVDP_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23804Reserved for future use.14130x0RSNOOP_LATENCY_REQUIREPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23815Snoop Latency Requirement.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R/W 15150x0R/WNO_SNOOP_LATENCY_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23826No Snoop Latency Value.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R/W 25160x000R/WNO_SNOOP_LATENCY_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23837No Snoop Latency Scale.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R/W 28260x0R/WRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23845Reserved for future use.30290x0RNO_SNOOP_LATENCY_REQUIREPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23856No Snoop Latency Requirement.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AUX_CLK_FREQ_OFFAUX_CLK_FREQ_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr238920x440R/W0x00000018PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFFAuxiliary Clock Frequency Control Register.falsefalsefalsefalseAUX_CLK_FREQPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23883The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk.Frequencies lower than 1 MHz are possible but with a loss of accuracy in the time counted.If the actual frequency (f) of aux_clk does not exactly match the programmed frequency (f_prog), then there is an error in the time counted by the controller that can be expressed in percentage as: err% = (f_prog/f-1)*100. For example if f=2.5 MHz and f_prog=3 MHz, then err% =(3/2.5-1)*100 =20%, meaning that the time counted by the controller on aux_clk will be 20% greater than the time in us programmed in the corresponding time register (for example T_POWER_ON).Note: This register field is sticky.900x018R/WRSVDP_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23891Reserved for future use.31100x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.L1_SUBSTATES_OFFL1_SUBSTATES_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr239520x444R/W0x000000d2PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_L1_SUBSTATES_OFFL1 Substates Timing Register.falsefalsefalsefalseL1SUB_T_POWER_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23905Duration (in 1us units) of L1.2.Entry. The actual timeout value will be L1SUB_T_POWER_OFF + 1. Range is 0.3.Note: This register field is sticky.100x2R/WL1SUB_T_L1_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23915Duration (in 1us units) of L1.2. The actual timeout value will be L1SUB_T_L1_2 + 1. Range is 0.15.Note: This register field is sticky.520x4R/WL1SUB_T_PCLKACKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23928Max delay (in 1us units) between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this time the request is aborted.The actual timeout value will be L1SUB_T_PCLKACK + 1. Range is 0..3Note: This register field is sticky.760x3R/WL1SUB_LOW_POWER_CLOCK_SWITCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23943If this bit is set to 1'b1 the reference clock will be running regardless of the CLKREQ# setting. If this bit is set to 1'b0 the reference clock may be gated off when CLKREQ# is de-asserted. If the bit is set to 1'b1 the controller will delay the switching of aux_clk to the slow platform clock until it detects that the link partner has de-asserted CLKREQ#.Note: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23951Reserved for future use.3190x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.POWERDOWN_CTRL_STATUS_OFFPOWERDOWN_CTRL_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr240130x448R/W0x00000220PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFFPowerdown Control and Status Register.falsefalsefalsefalsePOWERDOWN_FORCEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23971This field is a one shot field. Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake regardless of whether the PHY has returned Phystatus. This field could be used for debug purposes in event that the P2 Powerdown transition does not complete. It will allow the controller to proceed with the transition to the P1 Powerdown state. This field always reads back as 1'b0.000x0WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23979Reserved for future use.310x0RPOWERDOWN_MAC_POWERDOWNPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr23990This field represents the Powerdown value driven by the controller to the PHY.740x2RPOWERDOWN_PHY_POWERDOWNPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24004This field represents the Powerdown value that has been acknowledged by the PHY. It is updated with the value of Powerdown driven by the controller, when the PHY has returned the Phystatus acknowledgment for the Powerdown transition.1180x2RRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24012Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_1_OFFGEN4_LANE_MARGINING_1_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr241010x480R/W0x05201409PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFFGen4 Lane Margining 1 Register.falsefalsefalsefalseMARGINING_NUM_TIMING_STEPSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24029M(NumTimingSteps) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.500x09R/WRSVDP_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24037Reserved for future use.760x0RMARGINING_MAX_TIMING_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24050M(MaxTimingOffset) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.1380x14R/WRSVDP_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24058Reserved for future use.15140x0RMARGINING_NUM_VOLTAGE_STEPSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24071M(NumVoltageSteps) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.22160x20R/WRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24079Reserved for future use.23230x0RMARGINING_MAX_VOLTAGE_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24092M(MaxVoltageOffset) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.29240x05R/WRSVDP_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24100Reserved for future use.31300x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_2_OFFGEN4_LANE_MARGINING_2_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr242480x484R/W0x060f0000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFFGen4 Lane Margining 2 Register.falsefalsefalsefalseMARGINING_SAMPLE_RATE_VOLTAGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24120M(SamplingRateVoltage) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This value is not used when MARGINING_IND_ERROR_SAMPLER is 0b. The M(SamplingRateVoltage) is fixed to 63 internally.Note: This register field is sticky.500x00R/WRSVDP_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24128Reserved for future use.760x0RMARGINING_SAMPLE_RATE_TIMINGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24144M(SamplingRateTiming) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter , see the PCI Express Base Specification 4.0.Note: This value is not used when MARGINING_IND_ERROR_SAMPLER is 0b. The M(SamplingRateTiming) is fixed to 63 internally.Note: This register field is sticky.1380x00R/WRSVDP_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24152Reserved for future use.15140x0RMARGINING_MAXLANESPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24165M(MaxLanes) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.20160x0fR/WRSVDP_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24173Reserved for future use.23210x0RMARGINING_VOLTAGE_SUPPORTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24186M(VoltageSupported) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.24240x0R/WMARGINING_IND_UP_DOWN_VOLTAGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24199M(IndUpDownVoltage) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.25250x1R/WMARGINING_IND_LEFT_RIGHT_TIMINGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24212M(IndLeftRightTiming) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.26260x1R/WMARGINING_SAMPLE_REPORTING_METHODPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24226M(SampleReportingMethod) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.27270x0R/WMARGINING_IND_ERROR_SAMPLERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24239M(IndErrorSampler) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.28280x0R/WRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24247Reserved for future use.30290x0R--31310x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PIPE_RELATED_OFFPIPE_RELATED_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr243100x490R/W0x00000022PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PIPE_RELATED_OFFPIPE Related Register.This register controls the pipe's capabitity, control, and status parameters.falsefalsefalsefalseRX_MESSAGE_BUS_WRITE_BUFFER_DEPTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24268RXMessageBusWriteBufferDepth defined in the PIPE Specification.Indicates the number of write buffer entries that the PHY has implemented to receive writes from the controller.If the value is less than 2 for PIPE 5.1.1 or 1 for PIPE 4.4.1, the controller issues only write_commited commands, never write_uncommitted.Note: This register field is sticky.300x2R/WTX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24282TXMessageBusMinWriteBufferDepth defined in the PIPE Specification.Indicates the minimum number of write buffer entries that the PHY expects the controller to implement to receive writes from it.Note: This register field is sticky.740x2RPIPE_GARBAGE_DATA_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24301PIPE Garbage Data Mode. - 0: PIPE Spec compliant mode: The MAC discards any symbols received after the electrical idle ordered-set until RxValid is deasserted. - 1: Special PHY Support mode: The MAC discards any symbols received after the electrical idle ordered-set until when any of the following three conditions are true: -- RxValid is deasserted -- a valid RxStartBlock is received at 128b/130b encoding -- a valid COM symbol is received at 8b/10b encodingNote: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24309Reserved for future use.3190x000000RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR_DBI2PF0_TYPE0_HDR_DBI2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr246580x100000R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_DBI2DBI2 Shadow Block: PF PCI-Compatible Configuration Space Header Type0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR_DBI2.BAR0_MASK_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR_DBI2.BAR1_MASK_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR_DBI2.BAR2_MASK_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR_DBI2.BAR3_MASK_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR_DBI2.BAR4_MASK_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR_DBI2.BAR5_MASK_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR_DBI2.EXP_ROM_BAR_MASK_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR_DBI2.BAR0_MASK_REGBAR0_MASK_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr243660x10W0xffffffffPE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REGBAR0 Mask Register. This register is the mask for BAR0_REG. If implemented, it exists as a shadow register at the BAR0_REG address.Normally, the BAR masks are used for indicating the amount of address space that each BAR requests from host software. The BAR masks determine which bits in each BAR are non-writable by host software, which determines the size of the address space claimed by each BAR. The BAR mask values indicate the range of low-order bits, in each implemented BAR, not to use for address matching. The BAR mask value also indicates the range of low-order bits in the BAR that cannot be written from the host. The application can write to all BAR bits to allow setting of memory, I/O, and other standard BAR options.Your local CPU can change the mask at runtime using the DBI. The mask register is invisible to the PCIe wire but visible to your local CPU through the DBI. You cannot read the mask register but you can write to it. It is accessed by asserting dbi_cs2 and dbi_cs. If you only assert dbi_cs then you will access the BAR which is the primary register at that location. Use CS2 instead of dbi_cs2 when you are using the AHB/AXI bridge.falsefalsefalsefalsePCI_TYPE0_BAR0_ENABLEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24351BAR0 Mask Enabled.Note: This register field is sticky.000x1WPCI_TYPE0_BAR0_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24365BAR0 Mask.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: W (sticky)Note: This register field is sticky.3110x7fffffffWregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR_DBI2.BAR1_MASK_REGBAR1_MASK_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr244160x14W0xfffffffePE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REGBAR1 Mask Register. This register is the mask for BAR1_REG. If implemented, it exists as a shadow register at the BAR1_REG address.Normally, the BAR masks are used for indicating the amount of address space that each BAR requests from host software. The BAR masks determine which bits in each BAR are non-writable by host software, which determines the size of the address space claimed by each BAR. The BAR mask values indicate the range of low-order bits, in each implemented BAR, not to use for address matching. The BAR mask value also indicates the range of low-order bits in the BAR that cannot be written from the host. The application can write to all BAR bits to allow setting of memory, I/O, and other standard BAR options.Your local CPU can change the mask at runtime using the DBI. The mask register is invisible to the PCIe wire but visible to your local CPU through the DBI. You cannot read the mask register but you can write to it. It is accessed by asserting dbi_cs2 and dbi_cs. If you only assert dbi_cs then you will access the BAR which is the primary register at that location. Use CS2 instead of dbi_cs2 when you are using the AHB/AXI bridge.falsefalsefalsefalsePCI_TYPE0_BAR1_ENABLEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24401BAR1 Mask Enabled.Note: This register field is sticky.000x0WPCI_TYPE0_BAR1_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24415BAR1 Mask.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: W (sticky)Note: This register field is sticky.3110x7fffffffWregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR_DBI2.BAR2_MASK_REGBAR2_MASK_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr244660x18W0xffffffffPE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REGBAR2 Mask Register. This register is the mask for BAR2_REG. If implemented, it exists as a shadow register at the BAR2_REG address.Normally, the BAR masks are used for indicating the amount of address space that each BAR requests from host software. The BAR masks determine which bits in each BAR are non-writable by host software, which determines the size of the address space claimed by each BAR. The BAR mask values indicate the range of low-order bits, in each implemented BAR, not to use for address matching. The BAR mask value also indicates the range of low-order bits in the BAR that cannot be written from the host. The application can write to all BAR bits to allow setting of memory, I/O, and other standard BAR options.Your local CPU can change the mask at runtime using the DBI. The mask register is invisible to the PCIe wire but visible to your local CPU through the DBI. You cannot read the mask register but you can write to it. It is accessed by asserting dbi_cs2 and dbi_cs. If you only assert dbi_cs then you will access the BAR which is the primary register at that location. Use CS2 instead of dbi_cs2 when you are using the AHB/AXI bridge.falsefalsefalsefalsePCI_TYPE0_BAR2_ENABLEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24451BAR2 Mask Enabled.Note: This register field is sticky.000x1WPCI_TYPE0_BAR2_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24465BAR2 Mask.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: W (sticky)Note: This register field is sticky.3110x7fffffffWregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR_DBI2.BAR3_MASK_REGBAR3_MASK_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr245160x1CW0xfffffffePE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REGBAR3 Mask Register. This register is the mask for BAR3_REG. If implemented, it exists as a shadow register at the BAR3_REG address.Normally, the BAR masks are used for indicating the amount of address space that each BAR requests from host software. The BAR masks determine which bits in each BAR are non-writable by host software, which determines the size of the address space claimed by each BAR. The BAR mask values indicate the range of low-order bits, in each implemented BAR, not to use for address matching. The BAR mask value also indicates the range of low-order bits in the BAR that cannot be written from the host. The application can write to all BAR bits to allow setting of memory, I/O, and other standard BAR options.Your local CPU can change the mask at runtime using the DBI. The mask register is invisible to the PCIe wire but visible to your local CPU through the DBI. You cannot read the mask register but you can write to it. It is accessed by asserting dbi_cs2 and dbi_cs. If you only assert dbi_cs then you will access the BAR which is the primary register at that location. Use CS2 instead of dbi_cs2 when you are using the AHB/AXI bridge.falsefalsefalsefalsePCI_TYPE0_BAR3_ENABLEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24501BAR3 Mask Enabled.Note: This register field is sticky.000x0WPCI_TYPE0_BAR3_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24515BAR3 Mask.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: W (sticky)Note: This register field is sticky.3110x7fffffffWregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR_DBI2.BAR4_MASK_REGBAR4_MASK_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr245660x20W0xffffffffPE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REGBAR4 Mask Register. This register is the mask for BAR4_REG. If implemented, it exists as a shadow register at the BAR4_REG address.Normally, the BAR masks are used for indicating the amount of address space that each BAR requests from host software. The BAR masks determine which bits in each BAR are non-writable by host software, which determines the size of the address space claimed by each BAR. The BAR mask values indicate the range of low-order bits, in each implemented BAR, not to use for address matching. The BAR mask value also indicates the range of low-order bits in the BAR that cannot be written from the host. The application can write to all BAR bits to allow setting of memory, I/O, and other standard BAR options.Your local CPU can change the mask at runtime using the DBI. The mask register is invisible to the PCIe wire but visible to your local CPU through the DBI. You cannot read the mask register but you can write to it. It is accessed by asserting dbi_cs2 and dbi_cs. If you only assert dbi_cs then you will access the BAR which is the primary register at that location. Use CS2 instead of dbi_cs2 when you are using the AHB/AXI bridge.falsefalsefalsefalsePCI_TYPE0_BAR4_ENABLEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24551BAR4 Mask Enabled.Note: This register field is sticky.000x1WPCI_TYPE0_BAR4_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24565BAR4 Mask.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: W (sticky)Note: This register field is sticky.3110x7fffffffWregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR_DBI2.BAR5_MASK_REGBAR5_MASK_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr246160x24W0xfffffffePE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REGBAR5 Mask Register. This register is the mask for BAR5_REG. If implemented, it exists as a shadow register at the BAR5_REG address.Normally, the BAR masks are used for indicating the amount of address space that each BAR requests from host software. The BAR masks determine which bits in each BAR are non-writable by host software, which determines the size of the address space claimed by each BAR. The BAR mask values indicate the range of low-order bits, in each implemented BAR, not to use for address matching. The BAR mask value also indicates the range of low-order bits in the BAR that cannot be written from the host. The application can write to all BAR bits to allow setting of memory, I/O, and other standard BAR options.Your local CPU can change the mask at runtime using the DBI. The mask register is invisible to the PCIe wire but visible to your local CPU through the DBI. You cannot read the mask register but you can write to it. It is accessed by asserting dbi_cs2 and dbi_cs. If you only assert dbi_cs then you will access the BAR which is the primary register at that location. Use CS2 instead of dbi_cs2 when you are using the AHB/AXI bridge.falsefalsefalsefalsePCI_TYPE0_BAR5_ENABLEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24601BAR5 Mask Enabled.Note: This register field is sticky.000x0WPCI_TYPE0_BAR5_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24615BAR5 Mask.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: W (sticky)Note: This register field is sticky.3110x7fffffffWregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE0_HDR_DBI2.EXP_ROM_BAR_MASK_REGEXP_ROM_BAR_MASK_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr246570x30R/W0x0001ffffPE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REGExpansion ROM BAR Mask Register. This register is the mask for EXP_ROM_BASE_ADDR_REG register. If implemented, it exists as a shadow register at EXP_ROM_BAR_MASK_REG address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to this register.falsefalsefalsefalseROM_BAR_ENABLEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24640Expansion ROM Bar Mask Register Enabled.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if ROM_MASK_WRITABLE then WNote: This register field is sticky.000x1WROM_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24656Expansion ROM Mask.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if ROM_BAR_ENABLED && ROM_MASK_WRITABLE then WNote: This register field is sticky.3110x0000ffffRmemoryPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP_DBI2PF0_PCIE_CAP_DBI2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DBI2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DBI2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DBI2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DBI2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr246640x1000700xFR/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_DBI2DBI2 Shadow Block: PF PCI Express Capability StructuregroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP_DBI2PF0_MSIX_CAP_DBI2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr247960x1000B0RPE0_DWC_pcie_ctl_AXI_Slave_PF0_MSIX_CAP_DBI2DBI2 Shadow Block: PF MSI-X Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_TABLE_OFFSET_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_PBA_OFFSET_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REGSHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr247090x0R0x00800000PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REGMSI-X Capability ID, Next Pointer, Control Registers.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24683Reserved for future use.1500x0000RPCI_MSIX_TABLE_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24699MSI-X Table Size in the shadow register.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W else RNote: This register field is sticky.26160x080RRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24708Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_TABLE_OFFSET_REGSHADOW_MSIX_TABLE_OFFSET_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr247520x4R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REGMSI-X Table Offset and BIR Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCI_MSIX_BIRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24733MSI-X Table BAR Indicator Register Field.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1 ) then R/W else RNote: This register field is sticky.200x0RPCI_MSIX_TABLE_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24751MSI-X Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1 ) then R/W else RNote: This register field is sticky.3130x00000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_PBA_OFFSET_REGSHADOW_MSIX_PBA_OFFSET_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr247950x8R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REGMSI-X PBA Offset and BIR Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCI_MSIX_PBA_BIRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24776MSI-X PBA BIR.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1 ) then R/W else RNote: This register field is sticky.200x0RPCI_MSIX_PBA_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24794MSI-X PBA Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1 ) then R/W else RNote: This register field is sticky.3130x00000000RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP_DBI2PF0_TPH_CAP_DBI2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr249520x100208RPE0_DWC_pcie_ctl_AXI_Slave_PF0_TPH_CAP_DBI2DBI2 Shadow Block: PF TLP Processing Hints Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP_DBI2.SHADOW_TPH_REQ_CAP_REG_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP_DBI2.SHADOW_TPH_REQ_CAP_REG_REGSHADOW_TPH_REQ_CAP_REG_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr249510x4R0x00000001PE0_DWC_pcie_ctl_AXI_Slave_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REGShadow register TPH Requestor Capability Register.falsefalsefalsefalseTPH_REQ_NO_ST_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24816No ST Mode Supported in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x1RTPH_REQ_CAP_INT_VECPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24834Interrupt Vector Mode Supported in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)Note: This register field is sticky.110x0RTPH_REQ_DEVICE_SPECPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24852Device Specific Mode Supported in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)Note: This register field is sticky.220x0RRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24861Reserved for future use.730x00RTPH_REQ_EXTENDED_TPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24879Extended TPH Requester Supported in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)Note: This register field is sticky.880x0RTPH_REQ_CAP_ST_TABLE_LOC_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24897ST Table Location Bit 0 in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)Note: This register field is sticky.990x0RTPH_REQ_CAP_ST_TABLE_LOC_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24915ST Table Location Bit 1 in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)Note: This register field is sticky.10100x0RRSVDP_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24924Reserved for future use.15110x00RTPH_REQ_CAP_ST_TABLE_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24941ST Table Size in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W else RNote: This register field is sticky.26160x000RRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24950Reserved for future use.31270x00RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAPPF0_ATU_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr507490x300000R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAPATU Por Logic StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_0IATU_REGION_CTRL_1_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr250590x0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24970When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24981When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr24990This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25001When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25013When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25025Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25038When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25058Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_0IATU_REGION_CTRL_2_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr252670x4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25080MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25092TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25112TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25124TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25137Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25149Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25172TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25189Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25210Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25224DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25244CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25256Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25266Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr253040x8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25292Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25303Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr253200xCR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25319Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_0IATU_LIMIT_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr253470x10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25336Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25346Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr253760x14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25375When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr253900x18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25389Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr254220x20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25409Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25421Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_0IATU_REGION_CTRL_1_OFF_INBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr255350x100R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25436When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25449When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25462When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25475When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25488When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25500Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25514When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25534Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_0IATU_REGION_CTRL_2_OFF_INBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr258300x104R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25560MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25585BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25603Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25614TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25625TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25637ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25650TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25664Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25683Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25696PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25712Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25728Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25747Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25762CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25774Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25819Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25829Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_0IATU_LWR_BASE_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr258670x108R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25855Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25866Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_0IATU_UPPER_BASE_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr258810x10CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25880Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_0IATU_LIMIT_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr259080x110R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25897Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25907Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_0IATU_LWR_TARGET_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr259470x114R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25933Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25946Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr259630x118R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25962Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr259950x120R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25982Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr25994Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_1IATU_REGION_CTRL_1_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr260980x200R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26009When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26020When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26029This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26040When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26052When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26064Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26077When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26097Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_1IATU_REGION_CTRL_2_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr263060x204R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26119MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26131TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26151TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26163TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26176Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26188Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26211TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26228Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26249Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26263DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26283CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26295Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26305Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr263430x208R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26331Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26342Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr263590x20CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26358Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_1IATU_LIMIT_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr263860x210R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26375Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26385Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr264150x214R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26414When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr264290x218R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26428Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr264610x220R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26448Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26460Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_1IATU_REGION_CTRL_1_OFF_INBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr265740x300R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26475When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26488When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26501When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26514When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26527When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26539Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26553When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26573Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_1IATU_REGION_CTRL_2_OFF_INBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr268690x304R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26599MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26624BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26642Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26653TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26664TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26676ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26689TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26703Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26722Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26735PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26751Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26767Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26786Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26801CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26813Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26858Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26868Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_1IATU_LWR_BASE_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr269060x308R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26894Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26905Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_1IATU_UPPER_BASE_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr269200x30CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26919Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_1IATU_LIMIT_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr269470x310R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26936Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26946Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_1IATU_LWR_TARGET_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr269860x314R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26972Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr26985Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr270020x318R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27001Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr270340x320R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27021Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27033Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_2IATU_REGION_CTRL_1_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr271370x400R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27048When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27059When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27068This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27079When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27091When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27103Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27116When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27136Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_2IATU_REGION_CTRL_2_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr273450x404R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27158MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27170TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27190TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27202TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27215Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27227Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27250TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27267Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27288Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27302DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27322CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27334Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27344Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr273820x408R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27370Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27381Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr273980x40CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27397Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_2IATU_LIMIT_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr274250x410R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27414Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27424Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr274540x414R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27453When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr274680x418R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27467Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr275000x420R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27487Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27499Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_2IATU_REGION_CTRL_1_OFF_INBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr276130x500R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27514When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27527When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27540When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27553When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27566When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27578Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27592When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27612Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_2IATU_REGION_CTRL_2_OFF_INBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr279080x504R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27638MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27663BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27681Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27692TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27703TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27715ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27728TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27742Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27761Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27774PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27790Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27806Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27825Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27840CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27852Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27897Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27907Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_2IATU_LWR_BASE_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr279450x508R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27933Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27944Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_2IATU_UPPER_BASE_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr279590x50CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27958Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_2IATU_LIMIT_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr279860x510R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27975Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr27985Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_2IATU_LWR_TARGET_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr280250x514R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28011Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28024Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr280410x518R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28040Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr280730x520R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28060Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28072Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_3IATU_REGION_CTRL_1_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr281760x600R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28087When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28098When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28107This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28118When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28130When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28142Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28155When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28175Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_3IATU_REGION_CTRL_2_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr283840x604R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28197MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28209TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28229TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28241TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28254Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28266Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28289TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28306Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28327Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28341DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28361CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28373Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28383Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr284210x608R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28409Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28420Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr284370x60CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28436Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_3IATU_LIMIT_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr284640x610R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28453Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28463Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr284930x614R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28492When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr285070x618R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28506Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr285390x620R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28526Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28538Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_3IATU_REGION_CTRL_1_OFF_INBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr286520x700R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28553When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28566When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28579When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28592When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28605When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28617Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28631When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28651Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_3IATU_REGION_CTRL_2_OFF_INBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr289470x704R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28677MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28702BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28720Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28731TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28742TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28754ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28767TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28781Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28800Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28813PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28829Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28845Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28864Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28879CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28891Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28936Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28946Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_3IATU_LWR_BASE_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr289840x708R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28972Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28983Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_3IATU_UPPER_BASE_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr289980x70CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr28997Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_3IATU_LIMIT_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr290250x710R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29014Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29024Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_3IATU_LWR_TARGET_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr290640x714R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29050Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29063Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr290800x718R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29079Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr291120x720R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29099Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29111Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_4IATU_REGION_CTRL_1_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr292150x800R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29126When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29137When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29146This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29157When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29169When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29181Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29194When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29214Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_4IATU_REGION_CTRL_2_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr294230x804R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29236MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29248TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29268TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29280TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29293Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29305Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29328TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29345Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29366Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29380DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29400CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29412Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29422Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr294600x808R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29448Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29459Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr294760x80CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29475Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_4IATU_LIMIT_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr295030x810R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29492Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29502Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr295320x814R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29531When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr295460x818R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29545Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr295780x820R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29565Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29577Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_4IATU_REGION_CTRL_1_OFF_INBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr296910x900R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29592When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29605When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29618When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29631When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29644When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29656Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29670When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29690Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_4IATU_REGION_CTRL_2_OFF_INBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr299860x904R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29716MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29741BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29759Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29770TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29781TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29793ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29806TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29820Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29839Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29852PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29868Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29884Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29903Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29918CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29930Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29975Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr29985Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_4IATU_LWR_BASE_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr300230x908R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30011Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30022Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_4IATU_UPPER_BASE_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr300370x90CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30036Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_4IATU_LIMIT_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr300640x910R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30053Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30063Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_4IATU_LWR_TARGET_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr301030x914R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30089Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30102Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr301190x918R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30118Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr301510x920R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30138Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30150Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_5IATU_REGION_CTRL_1_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr302540xA00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30165When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30176When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30185This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30196When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30208When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30220Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30233When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30253Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_5IATU_REGION_CTRL_2_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr304620xA04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30275MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30287TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30307TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30319TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30332Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30344Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30367TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30384Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30405Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30419DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30439CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30451Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30461Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr304990xA08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30487Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30498Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr305150xA0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30514Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_5IATU_LIMIT_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr305420xA10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30531Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30541Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr305710xA14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30570When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr305850xA18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30584Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr306170xA20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30604Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30616Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_5IATU_REGION_CTRL_1_OFF_INBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr307300xB00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30631When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30644When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30657When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30670When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30683When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30695Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30709When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30729Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_5IATU_REGION_CTRL_2_OFF_INBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr310250xB04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30755MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30780BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30798Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30809TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30820TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30832ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30845TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30859Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30878Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30891PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30907Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30923Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30942Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30957CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr30969Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31014Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31024Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_5IATU_LWR_BASE_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr310620xB08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31050Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31061Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_5IATU_UPPER_BASE_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr310760xB0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31075Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_5IATU_LIMIT_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr311030xB10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31092Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31102Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_5IATU_LWR_TARGET_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr311420xB14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31128Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31141Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr311580xB18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31157Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr311900xB20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31177Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31189Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_6IATU_REGION_CTRL_1_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr312930xC00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31204When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31215When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31224This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31235When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31247When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31259Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31272When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31292Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_6IATU_REGION_CTRL_2_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr315010xC04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31314MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31326TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31346TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31358TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31371Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31383Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31406TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31423Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31444Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31458DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31478CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31490Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31500Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr315380xC08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31526Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31537Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr315540xC0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31553Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_6IATU_LIMIT_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr315810xC10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31570Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31580Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr316100xC14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31609When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr316240xC18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31623Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr316560xC20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31643Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31655Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_6IATU_REGION_CTRL_1_OFF_INBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr317690xD00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31670When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31683When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31696When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31709When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31722When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31734Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31748When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31768Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_6IATU_REGION_CTRL_2_OFF_INBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr320640xD04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31794MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31819BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31837Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31848TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31859TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31871ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31884TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31898Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31917Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31930PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31946Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31962Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31981Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr31996CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32008Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32053Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32063Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_6IATU_LWR_BASE_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr321010xD08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32089Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32100Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_6IATU_UPPER_BASE_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr321150xD0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32114Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_6IATU_LIMIT_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr321420xD10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32131Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32141Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_6IATU_LWR_TARGET_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr321810xD14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32167Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32180Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr321970xD18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32196Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr322290xD20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32216Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32228Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_7IATU_REGION_CTRL_1_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr323320xE00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32243When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32254When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32263This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32274When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32286When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32298Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32311When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32331Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_7IATU_REGION_CTRL_2_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr325400xE04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32353MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32365TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32385TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32397TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32410Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32422Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32445TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32462Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32483Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32497DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32517CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32529Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32539Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr325770xE08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32565Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32576Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr325930xE0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32592Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_7IATU_LIMIT_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr326200xE10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32609Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32619Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr326490xE14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32648When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr326630xE18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32662Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr326950xE20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32682Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32694Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_7IATU_REGION_CTRL_1_OFF_INBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr328080xF00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32709When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32722When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32735When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32748When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32761When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32773Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32787When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32807Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_7IATU_REGION_CTRL_2_OFF_INBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr331030xF04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32833MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32858BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32876Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32887TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32898TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32910ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32923TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32937Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32956Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32969PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr32985Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33001Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33020Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33035CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33047Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33092Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33102Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_7IATU_LWR_BASE_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr331400xF08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33128Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33139Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_7IATU_UPPER_BASE_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr331540xF0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33153Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_7IATU_LIMIT_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr331810xF10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33170Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33180Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_7IATU_LWR_TARGET_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr332200xF14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33206Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33219Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr332360xF18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33235Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr332680xF20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33255Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33267Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_8IATU_REGION_CTRL_1_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr333710x1000R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33282When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33293When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33302This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33313When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33325When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33337Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33350When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33370Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_8IATU_REGION_CTRL_2_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr335790x1004R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33392MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33404TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33424TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33436TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33449Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33461Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33484TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33501Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33522Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33536DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33556CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33568Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33578Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr336160x1008R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33604Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33615Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr336320x100CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33631Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_8IATU_LIMIT_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr336590x1010R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33648Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33658Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr336880x1014R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33687When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr337020x1018R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33701Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr337340x1020R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33721Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33733Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_8IATU_REGION_CTRL_1_OFF_INBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr338470x1100R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33748When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33761When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33774When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33787When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33800When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33812Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33826When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33846Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_8IATU_REGION_CTRL_2_OFF_INBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr341420x1104R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33872MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33897BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33915Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33926TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33937TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33949ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33962TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33976Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr33995Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34008PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34024Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34040Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34059Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34074CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34086Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34131Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34141Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_8IATU_LWR_BASE_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr341790x1108R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34167Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34178Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_8IATU_UPPER_BASE_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr341930x110CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34192Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_8IATU_LIMIT_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr342200x1110R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34209Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34219Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_8IATU_LWR_TARGET_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr342590x1114R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34245Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34258Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr342750x1118R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34274Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr343070x1120R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34294Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34306Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_9IATU_REGION_CTRL_1_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr344100x1200R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34321When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34332When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34341This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34352When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34364When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34376Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34389When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34409Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_9IATU_REGION_CTRL_2_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr346180x1204R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34431MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34443TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34463TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34475TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34488Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34500Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34523TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34540Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34561Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34575DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34595CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34607Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34617Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr346550x1208R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34643Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34654Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr346710x120CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34670Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_9IATU_LIMIT_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr346980x1210R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34687Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34697Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr347270x1214R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34726When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr347410x1218R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34740Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr347730x1220R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34760Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34772Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_9IATU_REGION_CTRL_1_OFF_INBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr348860x1300R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34787When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34800When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34813When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34826When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34839When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34851Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34865When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34885Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_9IATU_REGION_CTRL_2_OFF_INBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr351810x1304R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34911MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34936BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34954Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34965TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34976TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr34988ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35001TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35015Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35034Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35047PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35063Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35079Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35098Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35113CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35125Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35170Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35180Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_9IATU_LWR_BASE_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr352180x1308R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35206Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35217Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_9IATU_UPPER_BASE_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr352320x130CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35231Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_9IATU_LIMIT_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr352590x1310R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35248Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35258Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_9IATU_LWR_TARGET_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr352980x1314R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35284Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35297Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr353140x1318R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35313Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr353460x1320R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35333Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35345Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_10IATU_REGION_CTRL_1_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr354490x1400R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35360When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35371When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35380This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35391When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35403When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35415Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35428When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35448Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_10IATU_REGION_CTRL_2_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr356570x1404R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35470MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35482TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35502TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35514TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35527Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35539Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35562TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35579Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35600Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35614DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35634CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35646Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35656Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr356940x1408R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35682Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35693Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr357100x140CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35709Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_10IATU_LIMIT_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr357370x1410R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35726Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35736Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr357660x1414R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35765When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr357800x1418R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35779Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr358120x1420R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35799Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35811Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_10IATU_REGION_CTRL_1_OFF_INBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr359250x1500R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35826When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35839When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35852When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35865When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35878When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35890Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35904When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35924Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_10IATU_REGION_CTRL_2_OFF_INBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr362200x1504R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35950MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35975BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr35993Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36004TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36015TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36027ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36040TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36054Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36073Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36086PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36102Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36118Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36137Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36152CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36164Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36209Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36219Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_10IATU_LWR_BASE_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr362570x1508R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36245Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36256Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_10IATU_UPPER_BASE_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr362710x150CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36270Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_10IATU_LIMIT_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr362980x1510R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36287Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36297Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_10IATU_LWR_TARGET_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr363370x1514R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36323Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36336Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr363530x1518R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36352Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr363850x1520R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36372Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36384Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_11IATU_REGION_CTRL_1_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr364880x1600R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36399When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36410When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36419This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36430When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36442When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36454Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36467When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36487Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_11IATU_REGION_CTRL_2_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr366960x1604R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36509MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36521TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36541TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36553TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36566Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36578Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36601TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36618Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36639Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36653DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36673CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36685Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36695Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr367330x1608R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36721Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36732Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr367490x160CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36748Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_11IATU_LIMIT_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr367760x1610R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36765Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36775Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr368050x1614R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36804When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr368190x1618R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36818Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr368510x1620R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36838Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36850Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_11IATU_REGION_CTRL_1_OFF_INBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr369640x1700R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36865When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36878When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36891When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36904When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36917When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36929Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36943When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36963Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_11IATU_REGION_CTRL_2_OFF_INBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr372590x1704R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr36989MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37014BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37032Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37043TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37054TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37066ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37079TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37093Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37112Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37125PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37141Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37157Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37176Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37191CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37203Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37248Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37258Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_11IATU_LWR_BASE_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr372960x1708R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37284Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37295Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_11IATU_UPPER_BASE_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr373100x170CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37309Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_11IATU_LIMIT_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr373370x1710R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37326Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37336Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_11IATU_LWR_TARGET_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr373760x1714R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37362Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37375Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr373920x1718R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37391Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr374240x1720R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37411Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37423Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_12IATU_REGION_CTRL_1_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr375270x1800R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37438When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37449When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37458This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37469When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37481When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37493Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37506When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37526Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_12IATU_REGION_CTRL_2_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr377350x1804R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37548MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37560TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37580TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37592TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37605Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37617Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37640TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37657Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37678Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37692DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37712CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37724Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37734Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr377720x1808R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37760Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37771Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr377880x180CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37787Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_12IATU_LIMIT_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr378150x1810R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37804Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37814Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr378440x1814R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37843When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr378580x1818R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37857Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr378900x1820R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37877Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37889Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_12IATU_REGION_CTRL_1_OFF_INBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr380030x1900R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37904When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37917When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37930When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37943When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37956When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37968Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr37982When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38002Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_12IATU_REGION_CTRL_2_OFF_INBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr382980x1904R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38028MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38053BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38071Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38082TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38093TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38105ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38118TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38132Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38151Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38164PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38180Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38196Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38215Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38230CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38242Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38287Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38297Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_12IATU_LWR_BASE_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr383350x1908R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38323Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38334Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_12IATU_UPPER_BASE_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr383490x190CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38348Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_12IATU_LIMIT_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr383760x1910R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38365Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38375Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_12IATU_LWR_TARGET_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr384150x1914R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38401Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38414Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr384310x1918R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38430Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr384630x1920R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38450Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38462Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_13IATU_REGION_CTRL_1_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr385660x1A00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38477When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38488When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38497This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38508When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38520When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38532Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38545When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38565Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_13IATU_REGION_CTRL_2_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr387740x1A04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38587MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38599TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38619TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38631TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38644Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38656Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38679TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38696Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38717Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38731DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38751CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38763Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38773Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr388110x1A08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38799Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38810Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr388270x1A0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38826Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_13IATU_LIMIT_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr388540x1A10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38843Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38853Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr388830x1A14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38882When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr388970x1A18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38896Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr389290x1A20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38916Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38928Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_13IATU_REGION_CTRL_1_OFF_INBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr390420x1B00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38943When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38956When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38969When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38982When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr38995When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39007Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39021When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39041Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_13IATU_REGION_CTRL_2_OFF_INBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr393370x1B04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39067MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39092BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39110Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39121TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39132TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39144ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39157TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39171Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39190Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39203PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39219Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39235Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39254Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39269CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39281Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39326Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39336Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_13IATU_LWR_BASE_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr393740x1B08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39362Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39373Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_13IATU_UPPER_BASE_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr393880x1B0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39387Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_13IATU_LIMIT_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr394150x1B10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39404Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39414Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_13IATU_LWR_TARGET_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr394540x1B14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39440Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39453Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr394700x1B18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39469Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr395020x1B20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39489Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39501Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_14IATU_REGION_CTRL_1_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr396050x1C00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39516When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39527When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39536This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39547When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39559When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39571Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39584When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39604Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_14IATU_REGION_CTRL_2_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr398130x1C04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39626MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39638TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39658TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39670TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39683Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39695Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39718TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39735Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39756Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39770DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39790CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39802Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39812Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr398500x1C08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39838Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39849Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr398660x1C0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39865Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_14IATU_LIMIT_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr398930x1C10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39882Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39892Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr399220x1C14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39921When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr399360x1C18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39935Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr399680x1C20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39955Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39967Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_14IATU_REGION_CTRL_1_OFF_INBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr400810x1D00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39982When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr39995When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40008When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40021When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40034When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40046Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40060When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40080Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_14IATU_REGION_CTRL_2_OFF_INBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr403760x1D04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40106MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40131BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40149Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40160TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40171TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40183ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40196TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40210Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40229Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40242PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40258Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40274Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40293Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40308CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40320Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40365Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40375Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_14IATU_LWR_BASE_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr404130x1D08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40401Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40412Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_14IATU_UPPER_BASE_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr404270x1D0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40426Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_14IATU_LIMIT_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr404540x1D10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40443Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40453Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_14IATU_LWR_TARGET_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr404930x1D14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40479Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40492Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr405090x1D18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40508Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr405410x1D20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40528Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40540Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_15IATU_REGION_CTRL_1_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr406440x1E00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40555When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40566When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40575This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40586When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40598When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40610Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40623When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40643Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_15IATU_REGION_CTRL_2_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr408520x1E04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40665MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40677TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40697TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40709TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40722Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40734Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40757TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40774Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40795Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40809DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40829CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40841Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40851Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr408890x1E08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40877Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40888Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr409050x1E0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40904Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_15IATU_LIMIT_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr409320x1E10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40921Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40931Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr409610x1E14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40960When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr409750x1E18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40974Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr410070x1E20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr40994Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41006Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_15IATU_REGION_CTRL_1_OFF_INBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr411200x1F00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41021When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41034When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41047When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41060When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41073When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41085Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41099When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41119Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_15IATU_REGION_CTRL_2_OFF_INBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr414150x1F04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41145MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41170BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41188Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41199TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41210TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41222ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41235TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41249Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41268Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41281PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41297Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41313Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41332Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41347CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41359Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41404Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41414Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_15IATU_LWR_BASE_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr414520x1F08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41440Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41451Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_15IATU_UPPER_BASE_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr414660x1F0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41465Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_15IATU_LIMIT_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr414930x1F10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41482Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41492Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_15IATU_LWR_TARGET_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr415320x1F14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41518Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41531Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr415480x1F18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41547Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr415800x1F20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41567Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41579Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_16IATU_REGION_CTRL_1_OFF_INBOUND_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr416930x2100R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41594When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41607When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41620When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41633When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41646When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41658Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41672When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41692Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_16IATU_REGION_CTRL_2_OFF_INBOUND_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr419880x2104R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41718MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41743BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41761Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41772TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41783TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41795ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41808TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41822Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41841Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41854PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41870Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41886Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41905Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41920CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41932Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41977Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr41987Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_16IATU_LWR_BASE_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr420250x2108R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42013Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42024Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_16IATU_UPPER_BASE_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr420390x210CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42038Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_16IATU_LIMIT_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr420660x2110R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42055Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42065Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_16IATU_LWR_TARGET_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr421050x2114R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42091Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42104Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr421210x2118R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42120Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr421530x2120R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42140Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42152Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_17IATU_REGION_CTRL_1_OFF_INBOUND_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr422660x2300R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42167When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42180When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42193When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42206When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42219When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42231Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42245When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42265Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_17IATU_REGION_CTRL_2_OFF_INBOUND_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr425610x2304R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42291MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42316BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42334Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42345TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42356TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42368ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42381TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42395Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42414Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42427PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42443Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42459Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42478Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42493CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42505Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42550Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42560Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_17IATU_LWR_BASE_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr425980x2308R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42586Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42597Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_17IATU_UPPER_BASE_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr426120x230CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42611Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_17IATU_LIMIT_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr426390x2310R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42628Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42638Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_17IATU_LWR_TARGET_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr426780x2314R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42664Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42677Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr426940x2318R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42693Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr427260x2320R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42713Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42725Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_18IATU_REGION_CTRL_1_OFF_INBOUND_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr428390x2500R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42740When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42753When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42766When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42779When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42792When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42804Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42818When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42838Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_18IATU_REGION_CTRL_2_OFF_INBOUND_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr431340x2504R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42864MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42889BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42907Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42918TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42929TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42941ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42954TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42968Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr42987Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43000PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43016Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43032Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43051Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43066CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43078Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43123Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43133Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_18IATU_LWR_BASE_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr431710x2508R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43159Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43170Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_18IATU_UPPER_BASE_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr431850x250CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43184Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_18IATU_LIMIT_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr432120x2510R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43201Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43211Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_18IATU_LWR_TARGET_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr432510x2514R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43237Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43250Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr432670x2518R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43266Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr432990x2520R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43286Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43298Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_19IATU_REGION_CTRL_1_OFF_INBOUND_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr434120x2700R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43313When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43326When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43339When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43352When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43365When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43377Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43391When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43411Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_19IATU_REGION_CTRL_2_OFF_INBOUND_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr437070x2704R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43437MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43462BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43480Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43491TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43502TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43514ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43527TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43541Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43560Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43573PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43589Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43605Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43624Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43639CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43651Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43696Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43706Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_19IATU_LWR_BASE_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr437440x2708R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43732Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43743Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_19IATU_UPPER_BASE_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr437580x270CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43757Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_19IATU_LIMIT_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr437850x2710R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43774Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43784Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_19IATU_LWR_TARGET_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr438240x2714R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43810Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43823Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr438400x2718R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43839Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr438720x2720R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43859Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43871Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_20IATU_REGION_CTRL_1_OFF_INBOUND_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr439850x2900R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43886When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43899When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43912When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43925When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43938When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43950Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43964When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr43984Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_20IATU_REGION_CTRL_2_OFF_INBOUND_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr442800x2904R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44010MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44035BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44053Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44064TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44075TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44087ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44100TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44114Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44133Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44146PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44162Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44178Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44197Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44212CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44224Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44269Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44279Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_20IATU_LWR_BASE_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr443170x2908R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44305Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44316Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_20IATU_UPPER_BASE_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr443310x290CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44330Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_20IATU_LIMIT_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr443580x2910R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44347Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44357Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_20IATU_LWR_TARGET_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr443970x2914R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44383Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44396Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr444130x2918R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44412Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr444450x2920R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44432Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44444Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_21IATU_REGION_CTRL_1_OFF_INBOUND_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr445580x2B00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44459When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44472When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44485When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44498When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44511When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44523Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44537When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44557Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_21IATU_REGION_CTRL_2_OFF_INBOUND_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr448530x2B04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44583MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44608BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44626Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44637TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44648TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44660ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44673TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44687Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44706Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44719PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44735Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44751Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44770Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44785CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44797Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44842Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44852Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_21IATU_LWR_BASE_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr448900x2B08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44878Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44889Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_21IATU_UPPER_BASE_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr449040x2B0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44903Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_21IATU_LIMIT_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr449310x2B10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44920Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44930Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_21IATU_LWR_TARGET_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr449700x2B14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44956Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44969Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr449860x2B18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr44985Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr450180x2B20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45005Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45017Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_22IATU_REGION_CTRL_1_OFF_INBOUND_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr451310x2D00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45032When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45045When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45058When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45071When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45084When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45096Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45110When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45130Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_22IATU_REGION_CTRL_2_OFF_INBOUND_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr454260x2D04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45156MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45181BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45199Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45210TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45221TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45233ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45246TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45260Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45279Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45292PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45308Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45324Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45343Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45358CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45370Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45415Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45425Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_22IATU_LWR_BASE_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr454630x2D08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45451Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45462Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_22IATU_UPPER_BASE_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr454770x2D0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45476Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_22IATU_LIMIT_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr455040x2D10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45493Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45503Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_22IATU_LWR_TARGET_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr455430x2D14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45529Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45542Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr455590x2D18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45558Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr455910x2D20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45578Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45590Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_23IATU_REGION_CTRL_1_OFF_INBOUND_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr457040x2F00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45605When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45618When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45631When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45644When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45657When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45669Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45683When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45703Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_23IATU_REGION_CTRL_2_OFF_INBOUND_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr459990x2F04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45729MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45754BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45772Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45783TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45794TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45806ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45819TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45833Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45852Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45865PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45881Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45897Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45916Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45931CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45943Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45988Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr45998Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_23IATU_LWR_BASE_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr460360x2F08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46024Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46035Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_23IATU_UPPER_BASE_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr460500x2F0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46049Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_23IATU_LIMIT_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr460770x2F10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46066Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46076Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_23IATU_LWR_TARGET_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr461160x2F14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46102Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46115Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr461320x2F18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46131Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr461640x2F20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46151Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46163Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_24IATU_REGION_CTRL_1_OFF_INBOUND_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr462770x3100R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46178When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46191When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46204When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46217When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46230When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46242Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46256When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46276Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_24IATU_REGION_CTRL_2_OFF_INBOUND_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr465720x3104R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46302MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46327BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46345Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46356TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46367TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46379ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46392TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46406Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46425Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46438PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46454Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46470Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46489Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46504CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46516Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46561Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46571Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_24IATU_LWR_BASE_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr466090x3108R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46597Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46608Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_24IATU_UPPER_BASE_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr466230x310CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46622Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_24IATU_LIMIT_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr466500x3110R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46639Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46649Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_24IATU_LWR_TARGET_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr466890x3114R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46675Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46688Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr467050x3118R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46704Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr467370x3120R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46724Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46736Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_25IATU_REGION_CTRL_1_OFF_INBOUND_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr468500x3300R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46751When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46764When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46777When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46790When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46803When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46815Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46829When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46849Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_25IATU_REGION_CTRL_2_OFF_INBOUND_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr471450x3304R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46875MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46900BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46918Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46929TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46940TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46952ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46965TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46979Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr46998Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47011PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47027Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47043Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47062Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47077CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47089Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47134Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47144Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_25IATU_LWR_BASE_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr471820x3308R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47170Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47181Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_25IATU_UPPER_BASE_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr471960x330CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47195Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_25IATU_LIMIT_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr472230x3310R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47212Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47222Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_25IATU_LWR_TARGET_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr472620x3314R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47248Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47261Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr472780x3318R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47277Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr473100x3320R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47297Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47309Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_26IATU_REGION_CTRL_1_OFF_INBOUND_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr474230x3500R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47324When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47337When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47350When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47363When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47376When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47388Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47402When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47422Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_26IATU_REGION_CTRL_2_OFF_INBOUND_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr477180x3504R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47448MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47473BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47491Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47502TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47513TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47525ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47538TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47552Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47571Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47584PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47600Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47616Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47635Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47650CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47662Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47707Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47717Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_26IATU_LWR_BASE_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr477550x3508R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47743Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47754Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_26IATU_UPPER_BASE_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr477690x350CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47768Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_26IATU_LIMIT_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr477960x3510R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47785Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47795Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_26IATU_LWR_TARGET_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr478350x3514R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47821Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47834Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr478510x3518R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47850Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr478830x3520R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47870Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47882Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_27IATU_REGION_CTRL_1_OFF_INBOUND_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr479960x3700R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47897When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47910When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47923When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47936When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47949When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47961Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47975When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr47995Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_27IATU_REGION_CTRL_2_OFF_INBOUND_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr482910x3704R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48021MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48046BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48064Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48075TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48086TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48098ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48111TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48125Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48144Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48157PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48173Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48189Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48208Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48223CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48235Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48280Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48290Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_27IATU_LWR_BASE_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr483280x3708R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48316Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48327Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_27IATU_UPPER_BASE_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr483420x370CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48341Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_27IATU_LIMIT_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr483690x3710R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48358Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48368Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_27IATU_LWR_TARGET_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr484080x3714R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48394Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48407Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr484240x3718R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48423Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr484560x3720R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48443Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48455Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_28IATU_REGION_CTRL_1_OFF_INBOUND_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr485690x3900R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48470When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48483When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48496When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48509When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48522When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48534Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48548When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48568Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_28IATU_REGION_CTRL_2_OFF_INBOUND_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr488640x3904R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48594MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48619BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48637Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48648TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48659TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48671ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48684TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48698Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48717Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48730PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48746Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48762Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48781Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48796CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48808Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48853Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48863Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_28IATU_LWR_BASE_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr489010x3908R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48889Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48900Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_28IATU_UPPER_BASE_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr489150x390CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48914Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_28IATU_LIMIT_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr489420x3910R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48931Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48941Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_28IATU_LWR_TARGET_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr489810x3914R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48967Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48980Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr489970x3918R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr48996Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr490290x3920R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49016Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49028Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_29IATU_REGION_CTRL_1_OFF_INBOUND_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr491420x3B00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49043When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49056When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49069When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49082When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49095When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49107Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49121When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49141Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_29IATU_REGION_CTRL_2_OFF_INBOUND_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr494370x3B04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49167MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49192BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49210Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49221TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49232TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49244ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49257TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49271Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49290Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49303PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49319Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49335Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49354Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49369CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49381Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49426Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49436Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_29IATU_LWR_BASE_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr494740x3B08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49462Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49473Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_29IATU_UPPER_BASE_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr494880x3B0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49487Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_29IATU_LIMIT_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr495150x3B10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49504Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49514Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_29IATU_LWR_TARGET_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr495540x3B14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49540Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49553Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr495700x3B18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49569Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr496020x3B20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49589Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49601Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_30IATU_REGION_CTRL_1_OFF_INBOUND_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr497150x3D00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49616When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49629When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49642When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49655When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49668When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49680Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49694When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49714Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_30IATU_REGION_CTRL_2_OFF_INBOUND_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr500100x3D04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49740MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49765BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49783Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49794TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49805TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49817ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49830TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49844Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49863Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49876PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49892Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49908Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49927Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49942CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49954Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr49999Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50009Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_30IATU_LWR_BASE_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr500470x3D08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50035Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50046Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_30IATU_UPPER_BASE_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr500610x3D0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50060Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_30IATU_LIMIT_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr500880x3D10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50077Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50087Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_30IATU_LWR_TARGET_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr501270x3D14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50113Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50126Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr501430x3D18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50142Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr501750x3D20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50162Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50174Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_31IATU_REGION_CTRL_1_OFF_INBOUND_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr502880x3F00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50189When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50202When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50215When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50228When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50241When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50253Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50267When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50287Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_31IATU_REGION_CTRL_2_OFF_INBOUND_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr505830x3F04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50313MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50338BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50356Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50367TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50378TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50390ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50403TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50417Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50436Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50449PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50465Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50481Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50500Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50515CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50527Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50572Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50582Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_31IATU_LWR_BASE_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr506200x3F08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50608Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50619Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_31IATU_UPPER_BASE_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr506340x3F0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50633Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_31IATU_LIMIT_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr506610x3F10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50650Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50660Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_31IATU_LWR_TARGET_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr507000x3F14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50686Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50699Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr507160x3F18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50715Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr507480x3F20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50735Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50747Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAPPF0_DMA_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr570970x380000R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAPDMA Port Logic StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CTRL_DATA_ARB_PRIOR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DOORBELL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DOORBELL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_MASK_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_CLEAR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ERR_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH01_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH23_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH45_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH67_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_LINKED_LIST_ERR_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_MASK_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_CLEAR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_LINKED_LIST_ERR_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH01_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH23_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH45_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH67_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CTRL_DATA_ARB_PRIOR_OFFDMA_CTRL_DATA_ARB_PRIOR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr508270x0R/W0x00000688PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFFDMA Arbitration Scheme for TRGT1 Interface. This register is used to control traffic priorities among various sources that are delivered to your application through TRGT1 where 0x0 represents the highest priority. - Non-DMA Rx Requests - DMA Write Channel MRd Requests (DMA data requests and LL element/descriptor access) - DMA Read Channel MRd Requests (LL element/descriptor access) - DMA Read Channel MWr RequestsConcurrent traffic from channels with same priority are sorted according to Round-Robin arbitration rules.The arbitration priority defaults to Non-DMA requests (highest), Write Channel MRd, Read Channel MRd, Read Channel MWr.For more details, see the For more details, see the Internal Architecture section in the DMA chapter of the Databook.falsefalsefalsefalseRTRGT1_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50783Non-DMA Rx Requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 200x0R/WWR_CTRL_TRGT_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50795DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 530x1R/WRD_CTRL_TRGT_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50807DMA Read Channel MRd Requests. For LL element/descriptor access.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 860x2R/WRDBUFF_TRGT_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50818DMA Read Channel MWr Requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1190x3R/WRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50826Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CTRL_OFFDMA_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr509030x8R/W0x00040004PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CTRL_OFFDMA Number of Channels Register.falsefalsefalsefalseNUM_DMA_WR_CHANPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50840Number of Write Channels. You can read this register to determine the number of write channels the DMA controller has been configured to support.300x4RRSVDP_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50848Reserved for future use.1540x000RNUM_DMA_RD_CHANPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50858Number of Read Channels. You can read this register to determine the number of read channels the DMA controller has been configured to support.19160x4RRSVDP_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50866Reserved for future use.23200x0RDIS_C2W_CACHE_WRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50880Disable DMA Write Channels "completion to memory write" context cache pre-fetch function.Note: For internal debugging only.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDIS_C2W_CACHE_RDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50894Disable DMA Read Channels "completion to memory write" context cache pre-fetch function.Note: For internal debugging only.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WRSVDP_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50902Reserved for future use.31260x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_EN_OFFDMA_WRITE_ENGINE_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr510620xCR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFFDMA Write Engine Enable Register.falsefalsefalsefalseDMA_WRITE_ENGINEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50957DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset)For normal operation, you must initially set this bit to "1", before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation.You should set this bit to "0" when you want to "Soft Reset" the DMA controller write logic. There are three possible reasons for resetting the DMA controller write logic: - The "Abort Interrupt Status" bit is set (in the "DMA Write Interrupt Status Register" DMA_WRITE_INT_STATUS_OFF), and any of the bits is in the "DMA Write Error Status Register" (DMA_WRITE_ERR_STATUS_OFF) are set. Resetting the DMA controller write logic re-initializes the control logic, ensuring that the next DMA write transfer is executed successfully. - You have executed the procedure outlined in "Stop Bit" , after which, the "Abort Interrupt Status" bit is set and the Channel Status field (CS) of the DMA write "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_WRCH_0) is set to "Stopped." Resetting the DMA controller write logic re-initializes the control logic ensuring that the next DMA write transfer is executed successfully. - During software development, when you incorrectly program the DMA write engine.To "Soft Reset" the DMA controller write logic, you must: - De-assert the DMA write engine enable bit. - Wait for the DMA to complete any in-progress TLP transfer, by waiting until a read on the DMA write engine enable bit returns a "0". - Assert the DMA write engine enable bit.This "Soft Reset" does not clear the DMA configuration registers. The DMA write transfer does not start until you write to the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50965Reserved for future use.1510x0000RDMA_WRITE_ENGINE_EN_HSHAKE_CH0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50976Enable Handshake for DMA Write Engine Channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16160x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50987Enable Handshake for DMA Write Engine Channel 1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 17170x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr50998Enable Handshake for DMA Write Engine Channel 2.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 18180x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51009Enable Handshake for DMA Write Engine Channel 3.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19190x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51020Enable Handshake for DMA Write Engine Channel 4.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 20200x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51031Enable Handshake for DMA Write Engine Channel 5.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21210x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51042Enable Handshake for DMA Write Engine Channel 6.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51053Enable Handshake for DMA Write Engine Channel 7.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51061Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DOORBELL_OFFDMA_WRITE_DOORBELL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr511150x10R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFFDMA Write Doorbell Register.falsefalsefalsefalseWR_DOORBELL_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51085Doorbell Number. You must write the channel number to this register to start the DMA write transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. You do not need to toggle or write any other value to this register to start a new transfer.The range of this field is 0x0 to 0x7, and 0x0 corresponds to channel 0. Also note that a write to this field triggers the controller to exit L1 substates.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 200x0R/WRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51093Reserved for future use.3030x0000000RWR_STOPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51114Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests, sets the channel status to "Stopped", and asserts the "Abort" interrupt if it is enabled. Before setting the Stop bit, you must read the channel Status field (CS) of the "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_WRCH_0) to ensure that the write channel is "Running" (transferring data).For more information, see "Stopping the DMA Transfer (Software Stop)."Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFDMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr511970x18R/W0x00008421PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFDMA Write Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for write channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to the arbitration routine. When the channel weight count is reached or DMA channel request transfer size reaches zero, the WWR arbiter selects the next channel to be processed. Your software must initialize this register before ringing the doorbell. For more details, see "Multichannel Arbitration". Value range is (0-0x1F) corresponding to (1-32) transaction requests.falsefalsefalsefalseWRITE_CHANNEL0_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51143Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 400x01R/WWRITE_CHANNEL1_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51158Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 950x01R/WWRITE_CHANNEL2_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51173Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 14100x01R/WWRITE_CHANNEL3_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51188Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19150x01R/WRSVDP_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51196Reserved for future use.31200x000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFDMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr512790x1CR/W0x00008421PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFDMA Write Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for write channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to the arbitration routine. When the channel weight count is reached or DMA channel request transfer size reaches zero, the WWR arbiter selects the next channel to be processed. Your software must initialize this register before ringing the doorbell. For more details, see "Multichannel Arbitration". Value range is (0-0x1F) corresponding to (1-32) transaction requests.falsefalsefalsefalseWRITE_CHANNEL4_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51225Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 400x01R/WWRITE_CHANNEL5_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51240Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 950x01R/WWRITE_CHANNEL6_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51255Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 14100x01R/WWRITE_CHANNEL7_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51270Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19150x01R/WRSVDP_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51278Reserved for future use.31200x000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_EN_OFFDMA_READ_ENGINE_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr514370x2CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFFDMA Read Engine Enable Register.falsefalsefalsefalseDMA_READ_ENGINEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51332DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset)For normal operation, you must initially set this bit to "1", before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation.You should set this field to "0" when you want to "Soft Reset" the DMA controller read logic. There are three possible reasons for resetting the DMA controller read logic: - The "Abort Interrupt Status" bit is set (in the "DMA Read Interrupt Status Register" (DMA_READ_INT_STATUS_OFF), and any of the bits in the "DMA Read Error Status Low Register" (DMA_READ_ERR_STATUS_LOW_OFF) is set. Resetting the DMA controller read logic re-initializes the control logic, ensuring that the next DMA read transfer is executed successfully. - You have executed the procedure outlined in "Stop Bit", after which, the "Abort Interrupt Status" bit is set and the channel Status field (CS) of the DMA read "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_WRCH_0) is set to "Stopped". Resetting the DMA controller read logic re-initializes the control logic ensuring that the next DMA read transfer is executed successfully. - During software development, when you incorrectly program the DMA read engine.To "Soft Reset" the DMA controller read logic, you must: - De-assert the DMA read engine enable bit. - Wait for the DMA to complete any in-progress TLP transfer, by waiting until a read on the DMA read engine enable bit returns a "0". - Assert the DMA read engine enable bit.This "Soft Reset" does not clear the DMA configuration registers. The DMA read transfer does not start until you write to the "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51340Reserved for future use.1510x0000RDMA_READ_ENGINE_EN_HSHAKE_CH0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51351Enable Handshake for DMA Read Engine Channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16160x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51362Enable Handshake for DMA Read Engine Channel 1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 17170x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51373Enable Handshake for DMA Read Engine Channel 2.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 18180x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51384Enable Handshake for DMA Read Engine Channel 3.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19190x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51395Enable Handshake for DMA Read Engine Channel 4.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 20200x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51406Enable Handshake for DMA Read Engine Channel 5.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21210x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51417Enable Handshake for DMA Read Engine Channel 6.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51428Enable Handshake for DMA Read Engine Channel 7.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51436Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DOORBELL_OFFDMA_READ_DOORBELL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr514880x30R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_DOORBELL_OFFDMA Read Doorbell Register.falsefalsefalsefalseRD_DOORBELL_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51458Doorbell Number. You must write 0x0 to this register to start the DMA read transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change.The range of this field is 0x0 to 0x7, and 0x0 corresponds to channel 0. Also note that a write to this field triggers the controller to exit L1 substates.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 200x0R/WRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51466Reserved for future use.3030x0000000RRD_STOPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51487Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests, sets the channel status to "Stopped", and asserts the "Abort" interrupt if it is enabled. Before setting the Stop bit, you must read the channel Status field (CS) of the "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_RDCH_0) to ensure that the read channel is "Running" (transferring data).For more information, see "Stopping the DMA Transfer (Software Stop)".Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFDMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr515650x38R/W0x00008421PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFDMA Read Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for read channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to the arbitration routine. When the channel weight count is reached or DMA channel request transfer size reaches zero, the WWR arbiter selects the next channel to be processed. Your software must initialize this register before ringing the doorbell. For more details, see "Multichannel Arbitration". Value range is (0-0x1F) corresponding to (1-32) transaction requests.falsefalsefalsefalseREAD_CHANNEL0_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51514Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 400x01R/WREAD_CHANNEL1_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51528Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 950x01R/WREAD_CHANNEL2_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51542Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 14100x01R/WREAD_CHANNEL3_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51556Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19150x01R/WRSVDP_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51564Reserved for future use.31200x000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFDMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr516420x3CR/W0x00008421PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFDMA Read Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for read channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to the arbitration routine. When the channel weight count is reached or DMA channel request transfer size reaches zero, the WWR arbiter selects the next channel to be processed. Your software must initialize this register before ringing the doorbell. For more details, see "Multichannel Arbitration". Value range is (0-0x1F) corresponding to (1-32) transaction requests.falsefalsefalsefalseREAD_CHANNEL4_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51591Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 400x01R/WREAD_CHANNEL5_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51605Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 950x01R/WREAD_CHANNEL6_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51619Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 14100x01R/WREAD_CHANNEL7_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51633Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19150x01R/WRSVDP_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51641Reserved for future use.31200x000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_STATUS_OFFDMA_WRITE_INT_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr517160x4CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFFDMA Write Interrupt Status Register.falsefalsefalsefalseWR_DONE_INT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51672Done Interrupt Status. The DMA write channel has successfully completed the DMA transfer. For more details, see "Interrupts and Error Handling". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA write interrupt Clear register to clear this interrupt bit. Note: You can write to this register to emulate interrupt generation, during software or hardware testing. A write to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this register.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 700x00R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51680Reserved for future use.1580x00RWR_ABORT_INT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51707Abort Interrupt Status. The DMA write channel has detected an error, or you manually stopped the transfer as described in "Error Handling Assistance by Remote Software". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA write interrupt Clear register to clear this interrupt bit. Note: You can write to this register to emulate interrupt generation, during software or hardware testing. A write to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this register.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23160x00R/WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51715Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_MASK_OFFDMA_WRITE_INT_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr517640x54R/W0x000f000fPE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFFDMA Write Interrupt Mask Register.falsefalsefalsefalseWR_DONE_INT_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51733Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 300xfR/W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51741Reserved for future use.1580x00RWR_ABORT_INT_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51755Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19160xfR/W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51763Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_CLEAR_OFFDMA_WRITE_INT_CLEAR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr518160x58R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFFDMA Write Interrupt Clear Register.falsefalsefalsefalseWR_DONE_INT_CLEARPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51783Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: Reading from this self-clearing register field always returns a "0".300x0W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51791Reserved for future use.1580x00RWR_ABORT_INT_CLEARPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51807Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: Reading from this self-clearing register field always returns a "0".19160x0W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51815Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ERR_STATUS_OFFDMA_WRITE_ERR_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr518780x5CR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFFDMA Write Error Status RegisterfalsefalsefalsefalseAPP_READ_ERR_DETECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51841Application Read Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading data from it. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Write Interrupt Clear Register" (DMA_WRITE_INT_CLEAR_OFF) to clear this error bit.700x00RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51848Reserved for future use.1580x00RLINKLIST_ELEMENT_FETCH_ERR_DETECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51870Linked List Element Fetch Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Write Interrupt Clear Register" (DMA_WRITE_INT_CLEAR_OFF) to clear this error bit.23160x00RRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51877Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_LOW_OFFDMA_WRITE_DONE_IMWR_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr518950x60R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFFDMA Write Done IMWr Address Low Register.falsefalsefalsefalseDMA_WRITE_DONE_LOW_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51894The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be "00" as this address must be dword aligned.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_HIGH_OFFDMA_WRITE_DONE_IMWR_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr519110x64R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFFDMA Write Done IMWr Interrupt Address High Register.falsefalsefalsefalseDMA_WRITE_DONE_HIGH_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51910The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_LOW_OFFDMA_WRITE_ABORT_IMWR_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr519290x68R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFFDMA Write Abort IMWr Address Low Register.falsefalsefalsefalseDMA_WRITE_ABORT_LOW_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51928The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. Bits [1:0] must be "00" as this address must be dword aligned.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_HIGH_OFFDMA_WRITE_ABORT_IMWR_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr519450x6CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFFDMA Write Abort IMWr Address High Register.falsefalsefalsefalseDMA_WRITE_ABORT_HIGH_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51944The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH01_IMWR_DATA_OFFDMA_WRITE_CH01_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr519730x70R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFFDMA Write Channel 1 and 0 IMWr Data Register.falsefalsefalsefalseWR_CHANNEL_0_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51960The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WWR_CHANNEL_1_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51972The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH23_IMWR_DATA_OFFDMA_WRITE_CH23_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr520010x74R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFFDMA Write Channel 3 and 2 IMWr Data Register.falsefalsefalsefalseWR_CHANNEL_2_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr51988The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WWR_CHANNEL_3_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52000The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH45_IMWR_DATA_OFFDMA_WRITE_CH45_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr520290x78R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFFDMA Write Channel 5 and 4 IMWr Data Register.falsefalsefalsefalseWR_CHANNEL_4_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52016The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 4.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WWR_CHANNEL_5_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52028The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 5.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH67_IMWR_DATA_OFFDMA_WRITE_CH67_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr520570x7CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFFDMA Write Channel 7 and 6 IMWr Data Register.falsefalsefalsefalseWR_CHANNEL_6_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52044The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 6.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WWR_CHANNEL_7_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52056The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 7.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_LINKED_LIST_ERR_EN_OFFDMA_WRITE_LINKED_LIST_ERR_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr521150x90R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFFDMA Write Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel "done" interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel "abort" interrupts (local and remote).falsefalsefalsefalseWR_CHANNEL_LLRAIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52081Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Used in linked list mode only.For more details, see "Interrupt Handling".Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 300x0R/W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52089Reserved for future use.1580x00RWR_CHANNEL_LLLAIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52106Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Used in linked list mode only.For more details, see "Interrupt Handling".Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19160x0R/W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52114Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_STATUS_OFFDMA_READ_INT_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr521920xA0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFFDMA Read Interrupt Status Register.falsefalsefalsefalseRD_DONE_INT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52144Done Interrupt Status. The DMA read channel has successfully completed the DMA read transfer.Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA read interrupt Clear register to clear this interrupt bit. Note: You can write to this register to emulate interrupt generation, during software or hardware testing. A write to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this register.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 700x00R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52152Reserved for future use.1580x00RRD_ABORT_INT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52183Abort Interrupt Status. The DMA read channel has detected an error, or you manually stopped the transfer as described in "Stopping the DMA Transfer (Software Stop)". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.You can read the "DMA Read Error Status Low Register" (DMA_READ_ERR_STATUS_LOW_OFF) and "DMA Read Error Status High Register" (DMA_READ_ERR_STATUS_HIGH_OFF) to determine the source of the error. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA read interrupt Clear register to clear this interrupt bit. Note: You can write to this register to emulate interrupt generation, during software or hardware testing. A write to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this register.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23160x00R/WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52191Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_MASK_OFFDMA_READ_INT_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr522400xA8R/W0x000f000fPE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_INT_MASK_OFFDMA Read Interrupt Mask Register.falsefalsefalsefalseRD_DONE_INT_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52209Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 300xfR/W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52217Reserved for future use.1580x00RRD_ABORT_INT_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52231Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19160xfR/W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52239Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_CLEAR_OFFDMA_READ_INT_CLEAR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr522920xACR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFFDMA Read Interrupt Clear Register.falsefalsefalsefalseRD_DONE_INT_CLEARPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52259Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: Reading from this self-clearing register field always returns a "0".700x00WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52267Reserved for future use.1580x00RRD_ABORT_INT_CLEARPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52283Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: Reading from this self-clearing register field always returns a "0".23160x00WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52291Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_LOW_OFFDMA_READ_ERR_STATUS_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr523600xB4R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFFDMA Read Error Status Low Register.falsefalsefalsefalseAPP_WR_ERR_DETECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52322Application Write Error Detected. The DMA read channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while writing data to it. This error is fatal. You must restart the transfer from the beginning, as the channel context is corrupted, and the transfer is not rolled back. For more details, see "Linked List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this clears all bits in this register, and also the DMA Read Error Status High register (DMA_READ_ERR_STATUS_HIGH_OFF).700x00RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52329Reserved for future use.1580x00RLINK_LIST_ELEMENT_FETCH_ERR_DETECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52352Linked List Element Fetch Error Detected. - The DMA read channel has received an error response from the AXI bus while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this clears all bits in this register, and also the DMA Read Error Status High register (DMA_READ_ERR_STATUS_HIGH_OFF).23160x00RRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52359Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_HIGH_OFFDMA_READ_ERR_STATUS_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr524610xB8R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFFDMA Read Error Status High Register.falsefalsefalsefalseUNSUPPORTED_REQPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52387Unsupported Request. The DMA read channel has received a PCIe unsupported request completion status from the remote device in response to the MRd request. For more details, see "Linked List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the same channel in this register and in the DMA Read Error Status Low register.700x00RCPL_ABORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52411Completer Abort. The DMA read channel has received a PCIe completer abort completion status from the remote device in response to the MRd request. For more details, see "Linked List Mode".Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the same channel in this register and in the DMA Read Error Status Low register.1580x00RCPL_TIMEOUTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52434Completion Time Out. The DMA read channel has timed-out while waiting for the remote device to respond to the MRd request, or a malformed CplD has been received. For more details, see "Linked List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling" . - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the same channel in this register and in the DMA Read Error Status Low register.23160x00RDATA_POISIONINGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52460Data Poisoning. The DMA read channel has detected data poisoning in the completion from the remote device (in response to the MRd request).The DMA read channel will drop the completion and then be halted. The CX_FLT_MASK_UR_POIS filter rule does not affect this behavior.Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the same channel in this register and in the DMA Read Error Status Low register.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_LINKED_LIST_ERR_EN_OFFDMA_READ_LINKED_LIST_ERR_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr525180xC4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFFDMA Read Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel "done" interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel "abort" interrupts (local and remote).falsefalsefalsefalseRD_CHANNEL_LLRAIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52484Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Used in linked list mode only.For more details, see "Interrupt Handling".Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 300x0R/W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52492Reserved for future use.1580x00RRD_CHANNEL_LLLAIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52509Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Used in linked list mode only.For more details, see "Interrupt Handling".Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19160x0R/W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52517Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_LOW_OFFDMA_READ_DONE_IMWR_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr525350xCCR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFFDMA Read Done IMWr Address Low Register.falsefalsefalsefalseDMA_READ_DONE_LOW_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52534The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be "00" as this address must be dword aligned.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_HIGH_OFFDMA_READ_DONE_IMWR_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr525510xD0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFFDMA Read Done IMWr Address High Register.falsefalsefalsefalseDMA_READ_DONE_HIGH_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52550The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_LOW_OFFDMA_READ_ABORT_IMWR_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr525680xD4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFFDMA Read Abort IMWr Address Low Register.falsefalsefalsefalseDMA_READ_ABORT_LOW_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52567The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP. Bits [1:0] must be "00" as this address must be dword aligned.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_HIGH_OFFDMA_READ_ABORT_IMWR_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr525840xD8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFFDMA Read Abort IMWr Address High Register.falsefalsefalsefalseDMA_READ_ABORT_HIGH_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52583The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH01_IMWR_DATA_OFFDMA_READ_CH01_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr526120xDCR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFFDMA Read Channel 1 and 0 IMWr Data Register.falsefalsefalsefalseRD_CHANNEL_0_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52599The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WRD_CHANNEL_1_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52611The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH23_IMWR_DATA_OFFDMA_READ_CH23_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr526400xE0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFFDMA Read Channel 3 and 2 IMWr Data Register.falsefalsefalsefalseRD_CHANNEL_2_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52627The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 2.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WRD_CHANNEL_3_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52639The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 3.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH45_IMWR_DATA_OFFDMA_READ_CH45_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr526680xE4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFFDMA Read Channel 5 and 4 IMWr Data Register.falsefalsefalsefalseRD_CHANNEL_4_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52655The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 4.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WRD_CHANNEL_5_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52667The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 5.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH67_IMWR_DATA_OFFDMA_READ_CH67_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr526960xE8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFFDMA Read Channel 7 and 6 IMWr Data Register.falsefalsefalsefalseRD_CHANNEL_6_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52683The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 6.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WRD_CHANNEL_7_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52695The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 7.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFDMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr527690x108R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFDMA Write Engine Handshake Counter Channel 0/1/2/3 Register.falsefalsefalsefalseDMA_WRITE_ENGINE_HSHAKE_CNT_CH0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52710DMA handshake counter for DMA Write Engine Channel 0. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.400x00RRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52717Reserved for future use.750x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52727DMA handshake counter for DMA Write Engine Channel 1. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52734Reserved for future use.15130x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52744DMA handshake counter for DMA Write Engine Channel 2. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.20160x00RRSVDP_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52751Reserved for future use.23210x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52761DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.28240x00RRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52768Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFDMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr528420x10CR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFDMA Write Engine Handshake Counter Channel 4/5/6/7 Register.falsefalsefalsefalseDMA_WRITE_ENGINE_HSHAKE_CNT_CH4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52783DMA handshake counter for DMA Write Engine Channel 4. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.400x00RRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52790Reserved for future use.750x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52800DMA handshake counter for DMA Write Engine Channel 5. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52807Reserved for future use.15130x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52817DMA handshake counter for DMA Write Engine Channel 6. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.20160x00RRSVDP_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52824Reserved for future use.23210x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52834DMA handshake counter for DMA Write Engine Channel 7. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.28240x00RRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52841Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFDMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr529150x118R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFDMA Read Engine Handshake Counter Channel 0/1/2/3 Register.falsefalsefalsefalseDMA_READ_ENGINE_HSHAKE_CNT_CH0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52856DMA handshake counter for DMA Read Engine Channel 0. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.400x00RRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52863Reserved for future use.750x0RDMA_READ_ENGINE_HSHAKE_CNT_CH1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52873DMA handshake counter for DMA Read Engine Channel 1. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52880Reserved for future use.15130x0RDMA_READ_ENGINE_HSHAKE_CNT_CH2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52890DMA handshake counter for DMA Read Engine Channel 2. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.20160x00RRSVDP_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52897Reserved for future use.23210x0RDMA_READ_ENGINE_HSHAKE_CNT_CH3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52907DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.28240x00RRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52914Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFDMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr529880x11CR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFDMA Read Engine Handshake Counter Channel 4/5/6/7 Register.falsefalsefalsefalseDMA_READ_ENGINE_HSHAKE_CNT_CH4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52929DMA handshake counter for DMA Read Engine Channel 4. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.400x00RRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52936Reserved for future use.750x0RDMA_READ_ENGINE_HSHAKE_CNT_CH5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52946DMA handshake counter for DMA Read Engine Channel 5. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52953Reserved for future use.15130x0RDMA_READ_ENGINE_HSHAKE_CNT_CH6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52963DMA handshake counter for DMA Read Engine Channel 6. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.20160x00RRSVDP_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52970Reserved for future use.23210x0RDMA_READ_ENGINE_HSHAKE_CNT_CH7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52980DMA handshake counter for DMA Read Engine Channel 7. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.28240x00RRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_usp_4x8.csr52987Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_0DMA_CH_CONTROL1_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr532950x200R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0DMA Write Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53008Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53027Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53044Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53065Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53086Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53107Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53119Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53137Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53150Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53162Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53178Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Write Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_WRCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53190Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53212Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53226Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53240Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53254Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53266Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53280Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53294Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_0DMA_CH_CONTROL2_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr533510x204R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0DMA Write Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53311Steering Tag (ST). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53323Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53336Processing Hints (PH). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53350TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_0DMA_TRANSFER_SIZE_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr533820x208R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0DMA Write Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53381DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_0DMA_SAR_LOW_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr534030x20CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0DMA Write SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53402Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Write: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_0DMA_SAR_HIGH_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr534210x210R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0DMA Write SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53420Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_0DMA_DAR_LOW_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr534420x214R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0DMA Write DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53441Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Write: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_0DMA_DAR_HIGH_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr534610x218R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0DMA Write DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53460Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_0DMA_LLP_LOW_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr534830x21CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0DMA Write Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53482Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_0DMA_LLP_HIGH_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr535020x220R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0DMA Write Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53501Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_0DMA_CH_CONTROL1_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr538090x300R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0DMA Read Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53522Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53541Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53558Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53579Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53600Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53621Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Read Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53633Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53651Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53664Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53676Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53692Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Read Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_RDCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53704Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53726Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53740Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53754Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53768Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53780Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53794Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53808Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_0DMA_CH_CONTROL2_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr538650x304R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0DMA Read Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53825Steering Tag (ST). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53837Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53850Processing Hints (PH). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53864TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_0DMA_TRANSFER_SIZE_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr538960x308R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0DMA Read Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53895DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_0DMA_SAR_LOW_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr539170x30CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0DMA Read SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53916Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Read: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_0DMA_SAR_HIGH_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr539350x310R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0DMA Read SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53934Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_0DMA_DAR_LOW_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr539560x314R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0DMA Read DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53955Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Read: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_0DMA_DAR_HIGH_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr539740x318R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0DMA Read DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53973Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_0DMA_LLP_LOW_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr539960x31CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0DMA Read Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr53995Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_0DMA_LLP_HIGH_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr540150x320R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0DMA Read Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54014Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_1DMA_CH_CONTROL1_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr543220x400R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1DMA Write Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54035Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54054Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54071Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54092Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54113Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54134Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54146Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54164Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54177Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54189Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54205Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Write Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_WRCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54217Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54239Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54253Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54267Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54281Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54293Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54307Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54321Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_1DMA_CH_CONTROL2_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr543780x404R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1DMA Write Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54338Steering Tag (ST). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54350Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54363Processing Hints (PH). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54377TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_1DMA_TRANSFER_SIZE_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr544090x408R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1DMA Write Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54408DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_1DMA_SAR_LOW_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr544300x40CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1DMA Write SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54429Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Write: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_1DMA_SAR_HIGH_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr544480x410R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1DMA Write SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54447Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_1DMA_DAR_LOW_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr544690x414R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1DMA Write DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54468Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Write: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_1DMA_DAR_HIGH_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr544880x418R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1DMA Write DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54487Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_1DMA_LLP_LOW_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr545100x41CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1DMA Write Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54509Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_1DMA_LLP_HIGH_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr545290x420R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1DMA Write Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54528Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_1DMA_CH_CONTROL1_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr548360x500R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1DMA Read Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54549Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54568Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54585Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54606Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54627Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54648Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Read Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54660Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54678Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54691Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54703Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54719Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Read Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_RDCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54731Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54753Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54767Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54781Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54795Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54807Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54821Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54835Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_1DMA_CH_CONTROL2_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr548920x504R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1DMA Read Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54852Steering Tag (ST). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54864Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54877Processing Hints (PH). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54891TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_1DMA_TRANSFER_SIZE_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr549230x508R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1DMA Read Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54922DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_1DMA_SAR_LOW_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr549440x50CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1DMA Read SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54943Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Read: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_1DMA_SAR_HIGH_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr549620x510R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1DMA Read SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54961Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_1DMA_DAR_LOW_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr549830x514R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1DMA Read DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr54982Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Read: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_1DMA_DAR_HIGH_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr550010x518R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1DMA Read DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55000Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_1DMA_LLP_LOW_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr550230x51CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1DMA Read Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55022Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_1DMA_LLP_HIGH_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr550420x520R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1DMA Read Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55041Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_2DMA_CH_CONTROL1_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr553490x600R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2DMA Write Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55062Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55081Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55098Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55119Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55140Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55161Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55173Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55191Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55204Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55216Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55232Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Write Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_WRCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55244Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55266Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55280Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55294Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55308Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55320Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55334Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55348Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_2DMA_CH_CONTROL2_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr554050x604R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2DMA Write Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55365Steering Tag (ST). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55377Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55390Processing Hints (PH). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55404TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_2DMA_TRANSFER_SIZE_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr554360x608R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2DMA Write Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55435DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_2DMA_SAR_LOW_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr554570x60CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2DMA Write SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55456Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Write: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_2DMA_SAR_HIGH_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr554750x610R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2DMA Write SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55474Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_2DMA_DAR_LOW_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr554960x614R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2DMA Write DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55495Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Write: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_2DMA_DAR_HIGH_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr555150x618R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2DMA Write DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55514Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_2DMA_LLP_LOW_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr555370x61CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2DMA Write Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55536Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_2DMA_LLP_HIGH_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr555560x620R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2DMA Write Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55555Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_2DMA_CH_CONTROL1_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr558630x700R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2DMA Read Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55576Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55595Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55612Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55633Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55654Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55675Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Read Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55687Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55705Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55718Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55730Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55746Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Read Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_RDCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55758Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55780Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55794Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55808Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55822Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55834Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55848Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55862Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_2DMA_CH_CONTROL2_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr559190x704R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2DMA Read Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55879Steering Tag (ST). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55891Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55904Processing Hints (PH). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55918TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_2DMA_TRANSFER_SIZE_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr559500x708R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2DMA Read Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55949DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_2DMA_SAR_LOW_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr559710x70CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2DMA Read SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55970Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Read: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_2DMA_SAR_HIGH_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr559890x710R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2DMA Read SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr55988Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_2DMA_DAR_LOW_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr560100x714R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2DMA Read DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56009Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Read: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_2DMA_DAR_HIGH_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr560280x718R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2DMA Read DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56027Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_2DMA_LLP_LOW_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr560500x71CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2DMA Read Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56049Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_2DMA_LLP_HIGH_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr560690x720R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2DMA Read Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56068Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_3DMA_CH_CONTROL1_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr563760x800R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3DMA Write Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56089Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56108Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56125Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56146Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56167Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56188Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56200Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56218Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56231Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56243Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56259Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Write Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_WRCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56271Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56293Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56307Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56321Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56335Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56347Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56361Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56375Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_3DMA_CH_CONTROL2_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr564320x804R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3DMA Write Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56392Steering Tag (ST). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56404Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56417Processing Hints (PH). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56431TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_3DMA_TRANSFER_SIZE_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr564630x808R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3DMA Write Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56462DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_3DMA_SAR_LOW_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr564840x80CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3DMA Write SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56483Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Write: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_3DMA_SAR_HIGH_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr565020x810R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3DMA Write SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56501Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_3DMA_DAR_LOW_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr565230x814R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3DMA Write DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56522Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Write: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_3DMA_DAR_HIGH_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr565420x818R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3DMA Write DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56541Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_3DMA_LLP_LOW_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr565640x81CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3DMA Write Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56563Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_3DMA_LLP_HIGH_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr565830x820R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3DMA Write Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56582Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_3DMA_CH_CONTROL1_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr568900x900R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3DMA Read Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56603Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56622Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56639Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56660Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56681Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56702Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Read Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56714Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56732Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56745Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56757Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56773Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Read Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_RDCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56785Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56807Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56821Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56835Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56849Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56861Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56875Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56889Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_3DMA_CH_CONTROL2_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr569460x904R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3DMA Read Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56906Steering Tag (ST). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56918Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56931Processing Hints (PH). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56945TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_3DMA_TRANSFER_SIZE_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr569770x908R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3DMA Read Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56976DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_3DMA_SAR_LOW_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr569980x90CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3DMA Read SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr56997Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Read: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_3DMA_SAR_HIGH_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr570160x910R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3DMA Read SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57015Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_3DMA_DAR_LOW_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr570370x914R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3DMA Read DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57036Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Read: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_3DMA_DAR_HIGH_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr570550x918R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3DMA Read DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57054Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_3DMA_LLP_LOW_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr570770x91CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3DMA Read Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57076Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_3DMA_LLP_HIGH_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr570960x920R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3DMA Read Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57095Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WaddressmapPE0_DWC_pcie_ctl.DBI_SlaveDBI_SlaveDWC_pcie_dbi_cpcie_usp_4x8.csr114186R/WPE0_DWC_pcie_ctl_DBI_SlaveDWC PCIE-EP Memory MapgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDRgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_PM_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_LTR_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_LNR_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_DLINK_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_RESBAR_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_VF_RESBAR_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGICgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR_DBI2memoryPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP_DBI2groupPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP_DBI2groupPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP_DBI2groupPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP0x00x381123DBI_SlavePE0_DWC_pcie_ctl.DBI_Slave0x00x3FDBI_Slave.PF0_TYPE0_HDRPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR0x00x0DBI_Slave.PF0_TYPE0_HDR.DEVICE_ID_VENDOR_ID_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.DEVICE_ID_VENDOR_ID_REG0x40x4DBI_Slave.PF0_TYPE0_HDR.STATUS_COMMAND_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.STATUS_COMMAND_REG0x80x8DBI_Slave.PF0_TYPE0_HDR.CLASS_CODE_REVISION_IDPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.CLASS_CODE_REVISION_ID0xC0xCDBI_Slave.PF0_TYPE0_HDR.BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG0x100x10DBI_Slave.PF0_TYPE0_HDR.BAR0_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.BAR0_REG0x140x14DBI_Slave.PF0_TYPE0_HDR.BAR1_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.BAR1_REG0x180x18DBI_Slave.PF0_TYPE0_HDR.BAR2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.BAR2_REG0x1C0x1CDBI_Slave.PF0_TYPE0_HDR.BAR3_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.BAR3_REG0x200x20DBI_Slave.PF0_TYPE0_HDR.BAR4_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.BAR4_REG0x240x24DBI_Slave.PF0_TYPE0_HDR.BAR5_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.BAR5_REG0x280x28DBI_Slave.PF0_TYPE0_HDR.CARDBUS_CIS_PTR_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.CARDBUS_CIS_PTR_REG0x2C0x2CDBI_Slave.PF0_TYPE0_HDR.SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG0x300x30DBI_Slave.PF0_TYPE0_HDR.EXP_ROM_BASE_ADDR_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.EXP_ROM_BASE_ADDR_REG0x340x34DBI_Slave.PF0_TYPE0_HDR.PCI_CAP_PTR_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.PCI_CAP_PTR_REG0x380x3B0x3C0x3CDBI_Slave.PF0_TYPE0_HDR.MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG0x400x47DBI_Slave.PF0_PM_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_PM_CAP0x400x40DBI_Slave.PF0_PM_CAP.CAP_ID_NXT_PTR_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PM_CAP.CAP_ID_NXT_PTR_REG0x440x44DBI_Slave.PF0_PM_CAP.CON_STATUS_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PM_CAP.CON_STATUS_REG0x480x4F0x500x67DBI_Slave.PF0_MSI_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP0x500x50DBI_Slave.PF0_MSI_CAP.PCI_MSI_CAP_ID_NEXT_CTRL_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.PCI_MSI_CAP_ID_NEXT_CTRL_REG0x540x54DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_04H_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_04H_REG0x580x58DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_08H_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_08H_REG0x5C0x5CDBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_0CH_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_0CH_REG0x600x60DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_10H_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_10H_REG0x640x64DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_14H_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_14H_REG0x680x6F0x700xABDBI_Slave.PF0_PCIE_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP0x700x70DBI_Slave.PF0_PCIE_CAP.PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG0x740x74DBI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES_REG0x780x78DBI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL_DEVICE_STATUSPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL_DEVICE_STATUS0x7C0x7CDBI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES_REG0x800x80DBI_Slave.PF0_PCIE_CAP.LINK_CONTROL_LINK_STATUS_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.LINK_CONTROL_LINK_STATUS_REG0x840x930x940x94DBI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES2_REG0x980x98DBI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL2_DEVICE_STATUS2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL2_DEVICE_STATUS2_REG0x9C0x9CDBI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES2_REG0xA00xA0DBI_Slave.PF0_PCIE_CAP.LINK_CONTROL2_LINK_STATUS2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.LINK_CONTROL2_LINK_STATUS2_REG0xA40xAB0xAC0xAF0xB00xBCDBI_Slave.PF0_MSIX_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP0xB00xB0DBI_Slave.PF0_MSIX_CAP.PCI_MSIX_CAP_ID_NEXT_CTRL_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP.PCI_MSIX_CAP_ID_NEXT_CTRL_REG0xB40xB4DBI_Slave.PF0_MSIX_CAP.MSIX_TABLE_OFFSET_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP.MSIX_TABLE_OFFSET_REG0xB80xB8DBI_Slave.PF0_MSIX_CAP.MSIX_PBA_OFFSET_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP.MSIX_PBA_OFFSET_REG0xBC0xBC0xBD0xFF0x1000x147DBI_Slave.PF0_AER_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP0x1000x100DBI_Slave.PF0_AER_CAP.AER_EXT_CAP_HDR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.AER_EXT_CAP_HDR_OFF0x1040x104DBI_Slave.PF0_AER_CAP.UNCORR_ERR_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.UNCORR_ERR_STATUS_OFF0x1080x108DBI_Slave.PF0_AER_CAP.UNCORR_ERR_MASK_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.UNCORR_ERR_MASK_OFF0x10C0x10CDBI_Slave.PF0_AER_CAP.UNCORR_ERR_SEV_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.UNCORR_ERR_SEV_OFF0x1100x110DBI_Slave.PF0_AER_CAP.CORR_ERR_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.CORR_ERR_STATUS_OFF0x1140x114DBI_Slave.PF0_AER_CAP.CORR_ERR_MASK_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.CORR_ERR_MASK_OFF0x1180x118DBI_Slave.PF0_AER_CAP.ADV_ERR_CAP_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.ADV_ERR_CAP_CTRL_OFF0x11C0x11CDBI_Slave.PF0_AER_CAP.HDR_LOG_0_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.HDR_LOG_0_OFF0x1200x120DBI_Slave.PF0_AER_CAP.HDR_LOG_1_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.HDR_LOG_1_OFF0x1240x124DBI_Slave.PF0_AER_CAP.HDR_LOG_2_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.HDR_LOG_2_OFF0x1280x128DBI_Slave.PF0_AER_CAP.HDR_LOG_3_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.HDR_LOG_3_OFF0x12C0x1370x1380x138DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_1_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_1_OFF0x13C0x13CDBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_2_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_2_OFF0x1400x140DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_3_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_3_OFF0x1440x144DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_4_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_4_OFF0x1480x197DBI_Slave.PF0_VC_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP0x1480x148DBI_Slave.PF0_VC_CAP.VC_BASEPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.VC_BASE0x14C0x14CDBI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_10x1500x150DBI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_20x1540x154DBI_Slave.PF0_VC_CAP.VC_STATUS_CONTROL_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.VC_STATUS_CONTROL_REG0x1580x158DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC0PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC00x15C0x15CDBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC0PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC00x1600x160DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC0PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC00x1640x164DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC1PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC10x1680x168DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC1PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC10x16C0x16CDBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC1PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC10x1700x170DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC2PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC20x1740x174DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC2PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC20x1780x178DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC2PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC20x17C0x17CDBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC3PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC30x1800x180DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC3PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC30x1840x184DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC3PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC30x1880x1970x1980x1B7DBI_Slave.PF0_SPCIE_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP0x1980x198DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_HEADER_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_HEADER_REG0x19C0x19CDBI_Slave.PF0_SPCIE_CAP.LINK_CONTROL3_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.LINK_CONTROL3_REG0x1A00x1A0DBI_Slave.PF0_SPCIE_CAP.LANE_ERR_STATUS_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.LANE_ERR_STATUS_REG0x1A40x1A4DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_0CH_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_0CH_REG0x1A80x1A8DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_10H_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_10H_REG0x1AC0x1ACDBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_14H_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_14H_REG0x1B00x1B0DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_18H_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_18H_REG0x1B40x1B70x1B80x1DFDBI_Slave.PF0_PL16G_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP0x1B80x1B8DBI_Slave.PF0_PL16G_CAP.PL16G_EXT_CAP_HDR_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_EXT_CAP_HDR_REG0x1BC0x1BCDBI_Slave.PF0_PL16G_CAP.PL16G_CAPABILITY_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_CAPABILITY_REG0x1C00x1C0DBI_Slave.PF0_PL16G_CAP.PL16G_CONTROL_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_CONTROL_REG0x1C40x1C4DBI_Slave.PF0_PL16G_CAP.PL16G_STATUS_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_STATUS_REG0x1C80x1C8DBI_Slave.PF0_PL16G_CAP.PL16G_LC_DPAR_STATUS_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_LC_DPAR_STATUS_REG0x1CC0x1CCDBI_Slave.PF0_PL16G_CAP.PL16G_FIRST_RETIMER_DPAR_STATUS_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_FIRST_RETIMER_DPAR_STATUS_REG0x1D00x1D0DBI_Slave.PF0_PL16G_CAP.PL16G_SECOND_RETIMER_DPAR_STATUS_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_SECOND_RETIMER_DPAR_STATUS_REG0x1D40x1D70x1D80x1D8DBI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_20H_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_20H_REG0x1DC0x1DCDBI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_24H_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_24H_REG0x1E00x207DBI_Slave.PF0_MARGIN_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP0x1E00x1E0DBI_Slave.PF0_MARGIN_CAP.MARGIN_EXT_CAP_HDR_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_EXT_CAP_HDR_REG0x1E40x1E4DBI_Slave.PF0_MARGIN_CAP.MARGIN_PORT_CAPABILITIES_STATUS_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_PORT_CAPABILITIES_STATUS_REG0x1E80x1E8DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS0_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS0_REG0x1EC0x1ECDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS1_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS1_REG0x1F00x1F0DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS2_REG0x1F40x1F4DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS3_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS3_REG0x1F80x1F8DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS4_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS4_REG0x1FC0x1FCDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS5_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS5_REG0x2000x200DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS6_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS6_REG0x2040x204DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS7_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS7_REG0x2080x293DBI_Slave.PF0_TPH_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP0x2080x208DBI_Slave.PF0_TPH_CAP.TPH_EXT_CAP_HDR_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP.TPH_EXT_CAP_HDR_REG0x20C0x20CDBI_Slave.PF0_TPH_CAP.TPH_REQ_CAP_REG_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP.TPH_REQ_CAP_REG_REG0x2100x210DBI_Slave.PF0_TPH_CAP.TPH_REQ_CONTROL_REG_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP.TPH_REQ_CONTROL_REG_REG0x2140x214DBI_Slave.PF0_TPH_CAP.TPH_ST_TABLE_REG_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP.TPH_ST_TABLE_REG_00x2180x2930x2940x29BDBI_Slave.PF0_LTR_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_LTR_CAP0x2940x294DBI_Slave.PF0_LTR_CAP.LTR_CAP_HDR_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_LTR_CAP.LTR_CAP_HDR_REG0x2980x298DBI_Slave.PF0_LTR_CAP.LTR_LATENCY_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_LTR_CAP.LTR_LATENCY_REG0x29C0x2ABDBI_Slave.PF0_L1SUB_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAP0x29C0x29CDBI_Slave.PF0_L1SUB_CAP.L1SUB_CAP_HEADER_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAP.L1SUB_CAP_HEADER_REG0x2A00x2A0DBI_Slave.PF0_L1SUB_CAP.L1SUB_CAPABILITY_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAP.L1SUB_CAPABILITY_REG0x2A40x2A4DBI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL1_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL1_REG0x2A80x2A8DBI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL2_REG0x2AC0x2BB0x2BC0x2C3DBI_Slave.PF0_LNR_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_LNR_CAP0x2BC0x2BCDBI_Slave.PF0_LNR_CAP.LNR_EXT_CAP_HDR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_LNR_CAP.LNR_EXT_CAP_HDR_OFF0x2C00x2C0DBI_Slave.PF0_LNR_CAP.LNR_CAP_CONTROL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_LNR_CAP.LNR_CAP_CONTROL_OFF0x2C40x3C3DBI_Slave.PF0_RAS_DES_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP0x2C40x2C4DBI_Slave.PF0_RAS_DES_CAP.RAS_DES_CAP_HEADER_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.RAS_DES_CAP_HEADER_REG0x2C80x2C8DBI_Slave.PF0_RAS_DES_CAP.VENDOR_SPECIFIC_HEADER_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.VENDOR_SPECIFIC_HEADER_REG0x2CC0x2CCDBI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_CONTROL_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_CONTROL_REG0x2D00x2D0DBI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_DATA_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_DATA_REG0x2D40x2D4DBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_CONTROL_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_CONTROL_REG0x2D80x2D8DBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_REG0x2DC0x2DCDBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_63_32_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_63_32_REG0x2E00x2F30x2F40x2F4DBI_Slave.PF0_RAS_DES_CAP.EINJ_ENABLE_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ_ENABLE_REG0x2F80x2F8DBI_Slave.PF0_RAS_DES_CAP.EINJ0_CRC_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ0_CRC_REG0x2FC0x2FCDBI_Slave.PF0_RAS_DES_CAP.EINJ1_SEQNUM_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ1_SEQNUM_REG0x3000x300DBI_Slave.PF0_RAS_DES_CAP.EINJ2_DLLP_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ2_DLLP_REG0x3040x304DBI_Slave.PF0_RAS_DES_CAP.EINJ3_SYMBOL_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ3_SYMBOL_REG0x3080x308DBI_Slave.PF0_RAS_DES_CAP.EINJ4_FC_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ4_FC_REG0x30C0x30CDBI_Slave.PF0_RAS_DES_CAP.EINJ5_SP_TLP_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ5_SP_TLP_REG0x3100x310DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H0_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H0_REG0x3140x314DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H1_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H1_REG0x3180x318DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H2_REG0x31C0x31CDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H3_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H3_REG0x3200x320DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H0_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H0_REG0x3240x324DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H1_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H1_REG0x3280x328DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H2_REG0x32C0x32CDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H3_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H3_REG0x3300x330DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H0_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H0_REG0x3340x334DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H1_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H1_REG0x3380x338DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H2_REG0x33C0x33CDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H3_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H3_REG0x3400x340DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H0_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H0_REG0x3440x344DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H1_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H1_REG0x3480x348DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H2_REG0x34C0x34CDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H3_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H3_REG0x3500x350DBI_Slave.PF0_RAS_DES_CAP.EINJ6_TLP_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_TLP_REG0x3540x3630x3640x364DBI_Slave.PF0_RAS_DES_CAP.SD_CONTROL1_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_CONTROL1_REG0x3680x368DBI_Slave.PF0_RAS_DES_CAP.SD_CONTROL2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_CONTROL2_REG0x36C0x3730x3740x374DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LANE_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LANE_REG0x3780x378DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LTSSM_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LTSSM_REG0x37C0x37CDBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_PM_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_PM_REG0x3800x380DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L2_REG0x3840x384DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3FC_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3FC_REG0x3880x388DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3_REG0x38C0x3930x3940x394DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL1_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL1_REG0x3980x398DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL2_REG0x39C0x39CDBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL3_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL3_REG0x3A00x3A30x3A40x3A4DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS1_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS1_REG0x3A80x3A8DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS2_REG0x3AC0x3ACDBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS3_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS3_REG0x3B00x3C30x3C40x3FBDBI_Slave.PF0_VSECRAS_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP0x3C40x3C4DBI_Slave.PF0_VSECRAS_CAP.RASDP_EXT_CAP_HDR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_EXT_CAP_HDR_OFF0x3C80x3C8DBI_Slave.PF0_VSECRAS_CAP.RASDP_VENDOR_SPECIFIC_HDR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_VENDOR_SPECIFIC_HDR_OFF0x3CC0x3CCDBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_PROT_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_PROT_CTRL_OFF0x3D00x3D0DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNTER_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNTER_CTRL_OFF0x3D40x3D4DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNT_REPORT_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNT_REPORT_OFF0x3D80x3D8DBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNTER_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNTER_CTRL_OFF0x3DC0x3DCDBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNT_REPORT_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNT_REPORT_OFF0x3E00x3E0DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_INJ_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_INJ_CTRL_OFF0x3E40x3E4DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_ERROR_LOCATION_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_ERROR_LOCATION_OFF0x3E80x3E8DBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_ERROR_LOCATION_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_ERROR_LOCATION_OFF0x3EC0x3ECDBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_EN_OFF0x3F00x3F0DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_CLEAR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_CLEAR_OFF0x3F40x3F4DBI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_CORR_ERROR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_CORR_ERROR_OFF0x3F80x3F8DBI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_UNCORR_ERROR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_UNCORR_ERROR_OFF0x3FC0x407DBI_Slave.PF0_DLINK_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_DLINK_CAP0x3FC0x3FCDBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_EXT_HDR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_EXT_HDR_OFF0x4000x400DBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_CAP_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_CAP_OFF0x4040x404DBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_STATUS_OFF0x4080x43BDBI_Slave.PF0_RESBAR_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_RESBAR_CAP0x4080x408DBI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_HDR_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_HDR_REG0x40C0x40CDBI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_REG_0_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_REG_0_REG0x4100x410DBI_Slave.PF0_RESBAR_CAP.RESBAR_CTRL_REG_0_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RESBAR_CAP.RESBAR_CTRL_REG_0_REG0x4140x43B0x43C0x4470x4480x47BDBI_Slave.PF0_VF_RESBAR_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_VF_RESBAR_CAP0x4480x448DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_HDR_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_HDR_REG0x44C0x44CDBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_0_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_0_REG0x4500x450DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_0_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_0_REG0x4540x454DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_1_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_1_REG0x4580x458DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_1_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_1_REG0x45C0x45CDBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_2_REG0x4600x460DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_2_REG0x4640x47B0x47C0x6FF0x7000xCFFDBI_Slave.PF0_PORT_LOGICPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC0x7000x700DBI_Slave.PF0_PORT_LOGIC.ACK_LATENCY_TIMER_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.ACK_LATENCY_TIMER_OFF0x7040x704DBI_Slave.PF0_PORT_LOGIC.VENDOR_SPEC_DLLP_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VENDOR_SPEC_DLLP_OFF0x7080x708DBI_Slave.PF0_PORT_LOGIC.PORT_FORCE_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PORT_FORCE_OFF0x70C0x70CDBI_Slave.PF0_PORT_LOGIC.ACK_F_ASPM_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.ACK_F_ASPM_CTRL_OFF0x7100x710DBI_Slave.PF0_PORT_LOGIC.PORT_LINK_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PORT_LINK_CTRL_OFF0x7140x714DBI_Slave.PF0_PORT_LOGIC.LANE_SKEW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.LANE_SKEW_OFF0x7180x718DBI_Slave.PF0_PORT_LOGIC.TIMER_CTRL_MAX_FUNC_NUM_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TIMER_CTRL_MAX_FUNC_NUM_OFF0x71C0x71CDBI_Slave.PF0_PORT_LOGIC.SYMBOL_TIMER_FILTER_1_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.SYMBOL_TIMER_FILTER_1_OFF0x7200x720DBI_Slave.PF0_PORT_LOGIC.FILTER_MASK_2_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.FILTER_MASK_2_OFF0x7240x724DBI_Slave.PF0_PORT_LOGIC.AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF0x7280x728DBI_Slave.PF0_PORT_LOGIC.PL_DEBUG0_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PL_DEBUG0_OFF0x72C0x72CDBI_Slave.PF0_PORT_LOGIC.PL_DEBUG1_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PL_DEBUG1_OFF0x7300x730DBI_Slave.PF0_PORT_LOGIC.TX_P_FC_CREDIT_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TX_P_FC_CREDIT_STATUS_OFF0x7340x734DBI_Slave.PF0_PORT_LOGIC.TX_NP_FC_CREDIT_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TX_NP_FC_CREDIT_STATUS_OFF0x7380x738DBI_Slave.PF0_PORT_LOGIC.TX_CPL_FC_CREDIT_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TX_CPL_FC_CREDIT_STATUS_OFF0x73C0x73CDBI_Slave.PF0_PORT_LOGIC.QUEUE_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.QUEUE_STATUS_OFF0x7400x740DBI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_1_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_1_OFF0x7440x744DBI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_2_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_2_OFF0x7480x748DBI_Slave.PF0_PORT_LOGIC.VC0_P_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC0_P_RX_Q_CTRL_OFF0x74C0x74CDBI_Slave.PF0_PORT_LOGIC.VC0_NP_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC0_NP_RX_Q_CTRL_OFF0x7500x750DBI_Slave.PF0_PORT_LOGIC.VC0_CPL_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC0_CPL_RX_Q_CTRL_OFF0x7540x754DBI_Slave.PF0_PORT_LOGIC.VC1_P_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC1_P_RX_Q_CTRL_OFF0x7580x758DBI_Slave.PF0_PORT_LOGIC.VC1_NP_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC1_NP_RX_Q_CTRL_OFF0x75C0x75CDBI_Slave.PF0_PORT_LOGIC.VC1_CPL_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC1_CPL_RX_Q_CTRL_OFF0x7600x760DBI_Slave.PF0_PORT_LOGIC.VC2_P_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC2_P_RX_Q_CTRL_OFF0x7640x764DBI_Slave.PF0_PORT_LOGIC.VC2_NP_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC2_NP_RX_Q_CTRL_OFF0x7680x768DBI_Slave.PF0_PORT_LOGIC.VC2_CPL_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC2_CPL_RX_Q_CTRL_OFF0x76C0x76CDBI_Slave.PF0_PORT_LOGIC.VC3_P_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC3_P_RX_Q_CTRL_OFF0x7700x770DBI_Slave.PF0_PORT_LOGIC.VC3_NP_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC3_NP_RX_Q_CTRL_OFF0x7740x774DBI_Slave.PF0_PORT_LOGIC.VC3_CPL_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC3_CPL_RX_Q_CTRL_OFF0x7780x80B0x80C0x80CDBI_Slave.PF0_PORT_LOGIC.GEN2_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN2_CTRL_OFF0x8100x810DBI_Slave.PF0_PORT_LOGIC.PHY_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PHY_STATUS_OFF0x8140x814DBI_Slave.PF0_PORT_LOGIC.PHY_CONTROL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PHY_CONTROL_OFF0x8180x81B0x81C0x81CDBI_Slave.PF0_PORT_LOGIC.TRGT_MAP_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TRGT_MAP_CTRL_OFF0x8200x820DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_ADDR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_ADDR_OFF0x8240x824DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_UPPER_ADDR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_UPPER_ADDR_OFF0x8280x828DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_EN_OFF0x82C0x82CDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_MASK_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_MASK_OFF0x8300x830DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_STATUS_OFF0x8340x834DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_EN_OFF0x8380x838DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_MASK_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_MASK_OFF0x83C0x83CDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_STATUS_OFF0x8400x840DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_EN_OFF0x8440x844DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_MASK_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_MASK_OFF0x8480x848DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_STATUS_OFF0x84C0x84CDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_EN_OFF0x8500x850DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_MASK_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_MASK_OFF0x8540x854DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_STATUS_OFF0x8580x858DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_EN_OFF0x85C0x85CDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_MASK_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_MASK_OFF0x8600x860DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_STATUS_OFF0x8640x864DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_EN_OFF0x8680x868DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_MASK_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_MASK_OFF0x86C0x86CDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_STATUS_OFF0x8700x870DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_EN_OFF0x8740x874DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_MASK_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_MASK_OFF0x8780x878DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_STATUS_OFF0x87C0x87CDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_EN_OFF0x8800x880DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_MASK_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_MASK_OFF0x8840x884DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_STATUS_OFF0x8880x888DBI_Slave.PF0_PORT_LOGIC.MSI_GPIO_IO_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_GPIO_IO_OFF0x88C0x88CDBI_Slave.PF0_PORT_LOGIC.CLOCK_GATING_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.CLOCK_GATING_CTRL_OFF0x8900x890DBI_Slave.PF0_PORT_LOGIC.GEN3_RELATED_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN3_RELATED_OFF0x8940x8A70x8A80x8A8DBI_Slave.PF0_PORT_LOGIC.GEN3_EQ_CONTROL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN3_EQ_CONTROL_OFF0x8AC0x8ACDBI_Slave.PF0_PORT_LOGIC.GEN3_EQ_FB_MODE_DIR_CHANGE_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN3_EQ_FB_MODE_DIR_CHANGE_OFF0x8B00x8B30x8B40x8B4DBI_Slave.PF0_PORT_LOGIC.ORDER_RULE_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.ORDER_RULE_CTRL_OFF0x8B80x8B8DBI_Slave.PF0_PORT_LOGIC.PIPE_LOOPBACK_CONTROL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PIPE_LOOPBACK_CONTROL_OFF0x8BC0x8BCDBI_Slave.PF0_PORT_LOGIC.MISC_CONTROL_1_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MISC_CONTROL_1_OFF0x8C00x8C0DBI_Slave.PF0_PORT_LOGIC.MULTI_LANE_CONTROL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MULTI_LANE_CONTROL_OFF0x8C40x8C4DBI_Slave.PF0_PORT_LOGIC.PHY_INTEROP_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PHY_INTEROP_CTRL_OFF0x8C80x8C8DBI_Slave.PF0_PORT_LOGIC.TRGT_CPL_LUT_DELETE_ENTRY_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TRGT_CPL_LUT_DELETE_ENTRY_OFF0x8CC0x8CCDBI_Slave.PF0_PORT_LOGIC.LINK_FLUSH_CONTROL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.LINK_FLUSH_CONTROL_OFF0x8D00x8D0DBI_Slave.PF0_PORT_LOGIC.AMBA_ERROR_RESPONSE_DEFAULT_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AMBA_ERROR_RESPONSE_DEFAULT_OFF0x8D40x8D4DBI_Slave.PF0_PORT_LOGIC.AMBA_LINK_TIMEOUT_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AMBA_LINK_TIMEOUT_OFF0x8D80x8D8DBI_Slave.PF0_PORT_LOGIC.AMBA_ORDERING_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AMBA_ORDERING_CTRL_OFF0x8DC0x8DF0x8E00x8E0DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_1_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_1_OFF0x8E40x8E4DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_2_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_2_OFF0x8E80x8E8DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_3_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_3_OFF0x8EC0x8EF0x8F00x8F0DBI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_LOW_OFF0x8F40x8F4DBI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_HIGH_OFF0x8F80x8F8DBI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_NUMBER_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_NUMBER_OFF0x8FC0x8FCDBI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_TYPE_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_TYPE_OFF0x9000x93F0x9400x940DBI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_LOW_OFF0x9440x944DBI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_HIGH_OFF0x9480x948DBI_Slave.PF0_PORT_LOGIC.MSIX_DOORBELL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSIX_DOORBELL_OFF0x94C0x94CDBI_Slave.PF0_PORT_LOGIC.MSIX_RAM_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSIX_RAM_CTRL_OFF0x9500xB2F0xB300xB30DBI_Slave.PF0_PORT_LOGIC.PL_LTR_LATENCY_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PL_LTR_LATENCY_OFF0xB340xB3F0xB400xB40DBI_Slave.PF0_PORT_LOGIC.AUX_CLK_FREQ_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AUX_CLK_FREQ_OFF0xB440xB44DBI_Slave.PF0_PORT_LOGIC.L1_SUBSTATES_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.L1_SUBSTATES_OFF0xB480xB48DBI_Slave.PF0_PORT_LOGIC.POWERDOWN_CTRL_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.POWERDOWN_CTRL_STATUS_OFF0xB4C0xB7F0xB800xB80DBI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_1_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_1_OFF0xB840xB84DBI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_2_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_2_OFF0xB880xB8F0xB900xB90DBI_Slave.PF0_PORT_LOGIC.PIPE_RELATED_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PIPE_RELATED_OFF0xB940xCFF0xD000xFFFFF0x1000000x10003FDBI_Slave.PF0_TYPE0_HDR_DBI2PE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR_DBI20x1000000x10000F0x1000100x100010DBI_Slave.PF0_TYPE0_HDR_DBI2.BAR0_MASK_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR_DBI2.BAR0_MASK_REG0x1000140x100014DBI_Slave.PF0_TYPE0_HDR_DBI2.BAR1_MASK_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR_DBI2.BAR1_MASK_REG0x1000180x100018DBI_Slave.PF0_TYPE0_HDR_DBI2.BAR2_MASK_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR_DBI2.BAR2_MASK_REG0x10001C0x10001CDBI_Slave.PF0_TYPE0_HDR_DBI2.BAR3_MASK_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR_DBI2.BAR3_MASK_REG0x1000200x100020DBI_Slave.PF0_TYPE0_HDR_DBI2.BAR4_MASK_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR_DBI2.BAR4_MASK_REG0x1000240x100024DBI_Slave.PF0_TYPE0_HDR_DBI2.BAR5_MASK_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR_DBI2.BAR5_MASK_REG0x1000280x10002F0x1000300x100030DBI_Slave.PF0_TYPE0_HDR_DBI2.EXP_ROM_BAR_MASK_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR_DBI2.EXP_ROM_BAR_MASK_REG0x1000340x10003F0x1000400x10006F0x1000700x1000ABDBI_Slave.PF0_PCIE_CAP_DBI2PE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP_DBI20x1000AC0x1000AF0x1000B00x1000BCDBI_Slave.PF0_MSIX_CAP_DBI2PE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP_DBI20x1000B00x1000B0DBI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG0x1000B40x1000B4DBI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_TABLE_OFFSET_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_TABLE_OFFSET_REG0x1000B80x1000B8DBI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_PBA_OFFSET_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_PBA_OFFSET_REG0x1000BC0x1000BC0x1000BD0x1002070x1002080x100293DBI_Slave.PF0_TPH_CAP_DBI2PE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP_DBI20x1002080x10020B0x10020C0x10020CDBI_Slave.PF0_TPH_CAP_DBI2.SHADOW_TPH_REQ_CAP_REG_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP_DBI2.SHADOW_TPH_REQ_CAP_REG_REG0x1002100x1002930x1002940x2FFFFF0x3000000x31FF23DBI_Slave.PF0_ATU_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP0x3000000x300000DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_00x3000040x300004DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_00x3000080x300008DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_00x30000C0x30000CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_00x3000100x300010DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_00x3000140x300014DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_00x3000180x300018DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_00x30001C0x30001F0x3000200x300020DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_00x3000240x3000FF0x3001000x300100DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_00x3001040x300104DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_00x3001080x300108DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_00x30010C0x30010CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_00x3001100x300110DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_00x3001140x300114DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_00x3001180x300118DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_00x30011C0x30011F0x3001200x300120DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_00x3001240x3001FF0x3002000x300200DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_10x3002040x300204DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_10x3002080x300208DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10x30020C0x30020CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10x3002100x300210DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_10x3002140x300214DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10x3002180x300218DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10x30021C0x30021F0x3002200x300220DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10x3002240x3002FF0x3003000x300300DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_10x3003040x300304DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_10x3003080x300308DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_10x30030C0x30030CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_10x3003100x300310DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_10x3003140x300314DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_10x3003180x300318DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10x30031C0x30031F0x3003200x300320DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10x3003240x3003FF0x3004000x300400DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_20x3004040x300404DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_20x3004080x300408DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_20x30040C0x30040CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_20x3004100x300410DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_20x3004140x300414DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_20x3004180x300418DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_20x30041C0x30041F0x3004200x300420DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_20x3004240x3004FF0x3005000x300500DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_20x3005040x300504DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_20x3005080x300508DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_20x30050C0x30050CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_20x3005100x300510DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_20x3005140x300514DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_20x3005180x300518DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20x30051C0x30051F0x3005200x300520DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20x3005240x3005FF0x3006000x300600DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_30x3006040x300604DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_30x3006080x300608DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_30x30060C0x30060CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_30x3006100x300610DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_30x3006140x300614DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_30x3006180x300618DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_30x30061C0x30061F0x3006200x300620DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_30x3006240x3006FF0x3007000x300700DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_30x3007040x300704DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_30x3007080x300708DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_30x30070C0x30070CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_30x3007100x300710DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_30x3007140x300714DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_30x3007180x300718DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30x30071C0x30071F0x3007200x300720DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30x3007240x3007FF0x3008000x300800DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_40x3008040x300804DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_40x3008080x300808DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_40x30080C0x30080CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_40x3008100x300810DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_40x3008140x300814DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_40x3008180x300818DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_40x30081C0x30081F0x3008200x300820DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_40x3008240x3008FF0x3009000x300900DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_40x3009040x300904DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_40x3009080x300908DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_40x30090C0x30090CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_40x3009100x300910DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_40x3009140x300914DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_40x3009180x300918DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_40x30091C0x30091F0x3009200x300920DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_40x3009240x3009FF0x300A000x300A00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_50x300A040x300A04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_50x300A080x300A08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_50x300A0C0x300A0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_50x300A100x300A10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_50x300A140x300A14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_50x300A180x300A18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_50x300A1C0x300A1F0x300A200x300A20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_50x300A240x300AFF0x300B000x300B00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_50x300B040x300B04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_50x300B080x300B08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_50x300B0C0x300B0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_50x300B100x300B10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_50x300B140x300B14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_50x300B180x300B18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_50x300B1C0x300B1F0x300B200x300B20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_50x300B240x300BFF0x300C000x300C00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_60x300C040x300C04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_60x300C080x300C08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_60x300C0C0x300C0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_60x300C100x300C10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_60x300C140x300C14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_60x300C180x300C18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_60x300C1C0x300C1F0x300C200x300C20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_60x300C240x300CFF0x300D000x300D00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_60x300D040x300D04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_60x300D080x300D08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_60x300D0C0x300D0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_60x300D100x300D10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_60x300D140x300D14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_60x300D180x300D18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_60x300D1C0x300D1F0x300D200x300D20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_60x300D240x300DFF0x300E000x300E00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_70x300E040x300E04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_70x300E080x300E08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_70x300E0C0x300E0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_70x300E100x300E10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_70x300E140x300E14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_70x300E180x300E18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_70x300E1C0x300E1F0x300E200x300E20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_70x300E240x300EFF0x300F000x300F00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_70x300F040x300F04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_70x300F080x300F08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_70x300F0C0x300F0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_70x300F100x300F10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_70x300F140x300F14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_70x300F180x300F18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_70x300F1C0x300F1F0x300F200x300F20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_70x300F240x300FFF0x3010000x301000DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_80x3010040x301004DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_80x3010080x301008DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_80x30100C0x30100CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_80x3010100x301010DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_80x3010140x301014DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_80x3010180x301018DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_80x30101C0x30101F0x3010200x301020DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_80x3010240x3010FF0x3011000x301100DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_80x3011040x301104DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_80x3011080x301108DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_80x30110C0x30110CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_80x3011100x301110DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_80x3011140x301114DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_80x3011180x301118DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_80x30111C0x30111F0x3011200x301120DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_80x3011240x3011FF0x3012000x301200DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_90x3012040x301204DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_90x3012080x301208DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_90x30120C0x30120CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_90x3012100x301210DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_90x3012140x301214DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_90x3012180x301218DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_90x30121C0x30121F0x3012200x301220DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_90x3012240x3012FF0x3013000x301300DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_90x3013040x301304DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_90x3013080x301308DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_90x30130C0x30130CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_90x3013100x301310DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_90x3013140x301314DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_90x3013180x301318DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_90x30131C0x30131F0x3013200x301320DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_90x3013240x3013FF0x3014000x301400DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_100x3014040x301404DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_100x3014080x301408DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_100x30140C0x30140CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_100x3014100x301410DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_100x3014140x301414DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_100x3014180x301418DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_100x30141C0x30141F0x3014200x301420DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_100x3014240x3014FF0x3015000x301500DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_100x3015040x301504DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_100x3015080x301508DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_100x30150C0x30150CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_100x3015100x301510DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_100x3015140x301514DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_100x3015180x301518DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_100x30151C0x30151F0x3015200x301520DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_100x3015240x3015FF0x3016000x301600DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_110x3016040x301604DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_110x3016080x301608DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_110x30160C0x30160CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_110x3016100x301610DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_110x3016140x301614DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_110x3016180x301618DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_110x30161C0x30161F0x3016200x301620DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_110x3016240x3016FF0x3017000x301700DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_110x3017040x301704DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_110x3017080x301708DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_110x30170C0x30170CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_110x3017100x301710DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_110x3017140x301714DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_110x3017180x301718DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_110x30171C0x30171F0x3017200x301720DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_110x3017240x3017FF0x3018000x301800DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_120x3018040x301804DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_120x3018080x301808DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_120x30180C0x30180CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_120x3018100x301810DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_120x3018140x301814DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_120x3018180x301818DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_120x30181C0x30181F0x3018200x301820DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_120x3018240x3018FF0x3019000x301900DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_120x3019040x301904DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_120x3019080x301908DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_120x30190C0x30190CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_120x3019100x301910DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_120x3019140x301914DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_120x3019180x301918DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_120x30191C0x30191F0x3019200x301920DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_120x3019240x3019FF0x301A000x301A00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_130x301A040x301A04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_130x301A080x301A08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_130x301A0C0x301A0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_130x301A100x301A10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_130x301A140x301A14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_130x301A180x301A18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_130x301A1C0x301A1F0x301A200x301A20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_130x301A240x301AFF0x301B000x301B00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_130x301B040x301B04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_130x301B080x301B08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_130x301B0C0x301B0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_130x301B100x301B10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_130x301B140x301B14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_130x301B180x301B18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_130x301B1C0x301B1F0x301B200x301B20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_130x301B240x301BFF0x301C000x301C00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_140x301C040x301C04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_140x301C080x301C08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_140x301C0C0x301C0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_140x301C100x301C10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_140x301C140x301C14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_140x301C180x301C18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_140x301C1C0x301C1F0x301C200x301C20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_140x301C240x301CFF0x301D000x301D00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_140x301D040x301D04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_140x301D080x301D08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_140x301D0C0x301D0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_140x301D100x301D10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_140x301D140x301D14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_140x301D180x301D18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_140x301D1C0x301D1F0x301D200x301D20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_140x301D240x301DFF0x301E000x301E00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_150x301E040x301E04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_150x301E080x301E08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_150x301E0C0x301E0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_150x301E100x301E10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_150x301E140x301E14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_150x301E180x301E18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_150x301E1C0x301E1F0x301E200x301E20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_150x301E240x301EFF0x301F000x301F00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_150x301F040x301F04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_150x301F080x301F08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_150x301F0C0x301F0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_150x301F100x301F10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_150x301F140x301F14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_150x301F180x301F18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_150x301F1C0x301F1F0x301F200x301F20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_150x301F240x3020FF0x3021000x302100DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_16PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_160x3021040x302104DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_16PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_160x3021080x302108DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_160x30210C0x30210CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_160x3021100x302110DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_160x3021140x302114DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_160x3021180x302118DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_160x30211C0x30211F0x3021200x302120DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_160x3021240x3022FF0x3023000x302300DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_17PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_170x3023040x302304DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_17PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_170x3023080x302308DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_170x30230C0x30230CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_170x3023100x302310DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_170x3023140x302314DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_170x3023180x302318DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_170x30231C0x30231F0x3023200x302320DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_170x3023240x3024FF0x3025000x302500DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_18PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_180x3025040x302504DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_18PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_180x3025080x302508DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_180x30250C0x30250CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_180x3025100x302510DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_180x3025140x302514DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_180x3025180x302518DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_180x30251C0x30251F0x3025200x302520DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_180x3025240x3026FF0x3027000x302700DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_19PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_190x3027040x302704DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_19PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_190x3027080x302708DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_190x30270C0x30270CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_190x3027100x302710DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_190x3027140x302714DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_190x3027180x302718DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_190x30271C0x30271F0x3027200x302720DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_190x3027240x3028FF0x3029000x302900DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_20PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_200x3029040x302904DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_20PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_200x3029080x302908DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_200x30290C0x30290CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_200x3029100x302910DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_200x3029140x302914DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_200x3029180x302918DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_200x30291C0x30291F0x3029200x302920DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_200x3029240x302AFF0x302B000x302B00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_21PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_210x302B040x302B04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_21PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_210x302B080x302B08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_210x302B0C0x302B0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_210x302B100x302B10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_210x302B140x302B14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_210x302B180x302B18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_210x302B1C0x302B1F0x302B200x302B20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_210x302B240x302CFF0x302D000x302D00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_22PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_220x302D040x302D04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_22PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_220x302D080x302D08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_220x302D0C0x302D0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_220x302D100x302D10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_220x302D140x302D14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_220x302D180x302D18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_220x302D1C0x302D1F0x302D200x302D20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_220x302D240x302EFF0x302F000x302F00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_23PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_230x302F040x302F04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_23PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_230x302F080x302F08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_230x302F0C0x302F0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_230x302F100x302F10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_230x302F140x302F14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_230x302F180x302F18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_230x302F1C0x302F1F0x302F200x302F20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_230x302F240x3030FF0x3031000x303100DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_24PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_240x3031040x303104DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_24PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_240x3031080x303108DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_240x30310C0x30310CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_240x3031100x303110DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_240x3031140x303114DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_240x3031180x303118DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_240x30311C0x30311F0x3031200x303120DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_240x3031240x3032FF0x3033000x303300DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_25PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_250x3033040x303304DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_25PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_250x3033080x303308DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_250x30330C0x30330CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_250x3033100x303310DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_250x3033140x303314DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_250x3033180x303318DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_250x30331C0x30331F0x3033200x303320DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_250x3033240x3034FF0x3035000x303500DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_26PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_260x3035040x303504DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_26PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_260x3035080x303508DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_260x30350C0x30350CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_260x3035100x303510DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_260x3035140x303514DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_260x3035180x303518DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_260x30351C0x30351F0x3035200x303520DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_260x3035240x3036FF0x3037000x303700DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_27PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_270x3037040x303704DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_27PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_270x3037080x303708DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_270x30370C0x30370CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_270x3037100x303710DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_270x3037140x303714DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_270x3037180x303718DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_270x30371C0x30371F0x3037200x303720DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_270x3037240x3038FF0x3039000x303900DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_28PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_280x3039040x303904DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_28PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_280x3039080x303908DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_280x30390C0x30390CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_280x3039100x303910DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_280x3039140x303914DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_280x3039180x303918DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_280x30391C0x30391F0x3039200x303920DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_280x3039240x303AFF0x303B000x303B00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_29PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_290x303B040x303B04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_29PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_290x303B080x303B08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_290x303B0C0x303B0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_290x303B100x303B10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_290x303B140x303B14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_290x303B180x303B18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_290x303B1C0x303B1F0x303B200x303B20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_290x303B240x303CFF0x303D000x303D00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_30PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_300x303D040x303D04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_30PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_300x303D080x303D08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_300x303D0C0x303D0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_300x303D100x303D10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_300x303D140x303D14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_300x303D180x303D18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_300x303D1C0x303D1F0x303D200x303D20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_300x303D240x303EFF0x303F000x303F00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_31PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_310x303F040x303F04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_31PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_310x303F080x303F08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_310x303F0C0x303F0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_310x303F100x303F10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_310x303F140x303F14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_310x303F180x303F18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_310x303F1C0x303F1F0x303F200x303F20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_310x303F240x31FF230x31FF240x37FFFF0x3800000x381123DBI_Slave.PF0_DMA_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP0x3800000x380000DBI_Slave.PF0_DMA_CAP.DMA_CTRL_DATA_ARB_PRIOR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CTRL_DATA_ARB_PRIOR_OFF0x3800040x3800070x3800080x380008DBI_Slave.PF0_DMA_CAP.DMA_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CTRL_OFF0x38000C0x38000CDBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_EN_OFF0x3800100x380010DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DOORBELL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DOORBELL_OFF0x3800140x3800170x3800180x380018DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF0x38001C0x38001CDBI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF0x3800200x38002B0x38002C0x38002CDBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_EN_OFF0x3800300x380030DBI_Slave.PF0_DMA_CAP.DMA_READ_DOORBELL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DOORBELL_OFF0x3800340x3800370x3800380x380038DBI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF0x38003C0x38003CDBI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF0x3800400x38004B0x38004C0x38004CDBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_STATUS_OFF0x3800500x3800530x3800540x380054DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_MASK_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_MASK_OFF0x3800580x380058DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_CLEAR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_CLEAR_OFF0x38005C0x38005CDBI_Slave.PF0_DMA_CAP.DMA_WRITE_ERR_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ERR_STATUS_OFF0x3800600x380060DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_LOW_OFF0x3800640x380064DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_HIGH_OFF0x3800680x380068DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_LOW_OFF0x38006C0x38006CDBI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_HIGH_OFF0x3800700x380070DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH01_IMWR_DATA_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH01_IMWR_DATA_OFF0x3800740x380074DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH23_IMWR_DATA_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH23_IMWR_DATA_OFF0x3800780x380078DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH45_IMWR_DATA_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH45_IMWR_DATA_OFF0x38007C0x38007CDBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH67_IMWR_DATA_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH67_IMWR_DATA_OFF0x3800800x38008F0x3800900x380090DBI_Slave.PF0_DMA_CAP.DMA_WRITE_LINKED_LIST_ERR_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_LINKED_LIST_ERR_EN_OFF0x3800940x38009F0x3800A00x3800A0DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_STATUS_OFF0x3800A40x3800A70x3800A80x3800A8DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_MASK_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_MASK_OFF0x3800AC0x3800ACDBI_Slave.PF0_DMA_CAP.DMA_READ_INT_CLEAR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_CLEAR_OFF0x3800B00x3800B30x3800B40x3800B4DBI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_LOW_OFF0x3800B80x3800B8DBI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_HIGH_OFF0x3800BC0x3800C30x3800C40x3800C4DBI_Slave.PF0_DMA_CAP.DMA_READ_LINKED_LIST_ERR_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_LINKED_LIST_ERR_EN_OFF0x3800C80x3800CB0x3800CC0x3800CCDBI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_LOW_OFF0x3800D00x3800D0DBI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_HIGH_OFF0x3800D40x3800D4DBI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_LOW_OFF0x3800D80x3800D8DBI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_HIGH_OFF0x3800DC0x3800DCDBI_Slave.PF0_DMA_CAP.DMA_READ_CH01_IMWR_DATA_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH01_IMWR_DATA_OFF0x3800E00x3800E0DBI_Slave.PF0_DMA_CAP.DMA_READ_CH23_IMWR_DATA_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH23_IMWR_DATA_OFF0x3800E40x3800E4DBI_Slave.PF0_DMA_CAP.DMA_READ_CH45_IMWR_DATA_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH45_IMWR_DATA_OFF0x3800E80x3800E8DBI_Slave.PF0_DMA_CAP.DMA_READ_CH67_IMWR_DATA_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH67_IMWR_DATA_OFF0x3800EC0x3801070x3801080x380108DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF0x38010C0x38010CDBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF0x3801100x3801170x3801180x380118DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF0x38011C0x38011CDBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF0x3801200x3801FF0x3802000x380200DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_00x3802040x380204DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_00x3802080x380208DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_00x38020C0x38020CDBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_00x3802100x380210DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_00x3802140x380214DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_00x3802180x380218DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_00x38021C0x38021CDBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_00x3802200x380220DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_00x3802240x3802FF0x3803000x380300DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_00x3803040x380304DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_00x3803080x380308DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_00x38030C0x38030CDBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_00x3803100x380310DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_00x3803140x380314DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_00x3803180x380318DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_00x38031C0x38031CDBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_00x3803200x380320DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_00x3803240x3803FF0x3804000x380400DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_10x3804040x380404DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_10x3804080x380408DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_10x38040C0x38040CDBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_10x3804100x380410DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_10x3804140x380414DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_10x3804180x380418DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_10x38041C0x38041CDBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_10x3804200x380420DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_10x3804240x3804FF0x3805000x380500DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_10x3805040x380504DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_10x3805080x380508DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_10x38050C0x38050CDBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_10x3805100x380510DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_10x3805140x380514DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_10x3805180x380518DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_10x38051C0x38051CDBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_10x3805200x380520DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_10x3805240x3805FF0x3806000x380600DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_20x3806040x380604DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_20x3806080x380608DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_20x38060C0x38060CDBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_20x3806100x380610DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_20x3806140x380614DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_20x3806180x380618DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_20x38061C0x38061CDBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_20x3806200x380620DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_20x3806240x3806FF0x3807000x380700DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_20x3807040x380704DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_20x3807080x380708DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_20x38070C0x38070CDBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_20x3807100x380710DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_20x3807140x380714DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_20x3807180x380718DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_20x38071C0x38071CDBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_20x3807200x380720DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_20x3807240x3807FF0x3808000x380800DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_30x3808040x380804DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_30x3808080x380808DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_30x38080C0x38080CDBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_30x3808100x380810DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_30x3808140x380814DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_30x3808180x380818DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_30x38081C0x38081CDBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_30x3808200x380820DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_30x3808240x3808FF0x3809000x380900DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_30x3809040x380904DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_30x3809080x380908DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_30x38090C0x38090CDBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_30x3809100x380910DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_30x3809140x380914DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_30x3809180x380918DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_30x38091C0x38091CDBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_30x3809200x380920DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_30x3809240x381123groupPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDRPF0_TYPE0_HDRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr584890x0R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE0_HDRPF PCI-Compatible Configuration Space Header Type0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.DEVICE_ID_VENDOR_ID_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.STATUS_COMMAND_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.CLASS_CODE_REVISION_IDregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.BAR0_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.BAR1_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.BAR2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.BAR3_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.BAR4_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.BAR5_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.CARDBUS_CIS_PTR_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.EXP_ROM_BASE_ADDR_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.PCI_CAP_PTR_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.DEVICE_ID_VENDOR_ID_REGDEVICE_ID_VENDOR_ID_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr571470x0R0xeb011e0aPE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REGDevice ID and Vendor ID Register.falsefalsefalsefalsePCI_TYPE0_VENDOR_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57130Vendor ID.The Vendor ID register identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to populate this register with a value of FFFFh, which is an invalid value for Vendor ID.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x1e0aRPCI_TYPE0_DEVICE_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57146Device ID. The Device ID register identifies the particular Function. This identifier is allocated by the vendor.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31160xeb01RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.STATUS_COMMAND_REGSTATUS_COMMAND_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr574830x4R/W0x00100000PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE0_HDR_STATUS_COMMAND_REGStatus and Command Register.falsefalsefalsefalsePCI_TYPE0_IO_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57169IO Space Enable.Controls a Function's response to I/O Space accesses. - When this bit is set, the Function is enabled to decode the address and further process I/O Space accesses. - When this bit is clear, all received I/O accesses are caused to be handled as Unsupported Requests.For a Function that does not support I/O Space accesses, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: !has_io_bar ? RO : RW - Dbi: !has_io_bar ? RO : RW 000x0R/WPCI_TYPE0_MEM_SPACE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57188Memory Space Enable.Controls a Function's response to Memory Space accesses. - When this bit is set, the Function is enabled to decode the address and further process Memory Space accesses. - When this bit is clear, all received Memory Space accesses are caused to be handled as Unsupported Requests.For a Function does not support Memory Space accesses, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: !has_mem_bar ? RO : RW - Dbi: !has_mem_bar ? RO : RW 110x0R/WPCI_TYPE0_BUS_MASTER_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57211Bus Master Enable.Controls the ability of a Function to issue Memory and I/O Read/Write requests. - When this bit is set, the Function is allowed to issue Memory or I/O Requests. - When this bit is clear, the Function is not allowed to issue any Memory or I/O Requests.Requests other than Memory or I/O Requests are not controlled by this bit.Note: MSI/MSI-X interrupt Messages are in-band memory writes, setting the Bus Master Enable bit to 0b disables MSI/MSI-X interrupt Messages as well.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WPCI_TYPE0_SPECIAL_CYCLE_OPERATIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57222Special Cycle Enable.This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.330x0RPCI_TYPE_MWI_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57235Memory Write and Invalidate.This bit was originally described in the PCI Local Bus Specification and thePCI-to-PCI Bridge architecture specification. Its functionality does not applyto PCI Express, the controller hardwires this bit to 0b.440x0RPCI_TYPE_VGA_PALETTE_SNOOPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57247VGA Palette Snoop.This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge architecture specification. Its functionality does not apply to PCI Express, the controller hardwires this bit to 0b.550x0RPCI_TYPE0_PARITY_ERR_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57259Parity Error Response.This bit controls the logging of poisoned TLPs in the Master Data Parity Errorbit in the Status register. For more details see the "Error Registers" section of the PCI Express Base Specification.660x0R/WPCI_TYPE_IDSEL_STEPPINGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57270IDSEL Stepping/Wait Cycle Control.This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.770x0RPCI_TYPE0_SERRENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57286SERR# Enable.When set, this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function.Note: The errors are reported if enabled either through this bit orthrough the PCI Express specific bits in the Device Control register. For moredetails see the "Error Registers" section of the PCI Express Base Specification.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57294Reserved for future use.990x0RPCI_TYPE0_INT_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57316Interrupt Disable.Controls the ability of a Function to generate INTx emulation interrupts. - When set, Functions are prevented from asserting INTx interrupts.Note: - Any INTx emulation interrupts already asserted by the Function must be deasserted when this bit is Set. INTx interrupts use virtual wires that must, if asserted, be deasserted using the appropriate Deassert_INTx message(s) when this bit is set. - Only the INTx virtual wire interrupt(s) associated with the Function(s) for which this bit is set are affected. - For functions that generate INTx interrupts, this bit is required. For functions that do not generate INTx interrupts, this bit is optional.10100x0R/WPCI_TYPE_RESERVPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57325Reserved.15110x00R--16160x0rRSVDP_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57333Reserved for future use.18170x0RINT_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57347Emulation interrupt pending.When set, indicates that an INTx emulation interrupt is pending internally in the Function. Setting the Interrupt Disable bit has no effect on the state of this bit. For Functions that do not generate INTx interrupts, the controller hardwires this bit to 0b.1919RCAP_LISTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57359Capabilities List.Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure, the controller hardwires this bit to 1b.20200x1RFAST_66MHZ_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5737066MHz Capable.This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.21210x0RRSVDP_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57378Reserved for future use.22220x0RFAST_B2B_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57389Fast Back to Back Transaction Capable.This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.23230x0RMASTER_DPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57405Master Data Parity Error.This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Function receives a Poisoned Completion - Function transmits a Poisoned RequestIf the Parity Error Response bit is 0b, this bit is never set.24240x0R/W1CDEV_SEL_TIMINGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57416DEVSEL Timing.This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this field to 00b.26250x0RSIGNALED_TARGET_ABORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57429Signaled Target Abort.This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. The controller hardwires this bit to 0b for Functions that do not signal Completer Abort.27270x0R/W1CRCVD_TARGET_ABORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57442Received Target Abort.This bit is set when a Requester receives a Completion with Completer Abort Completion Status. For Functions that do not make Non-Posted Requests on their own behalf, the controller hardwires this bit to 0b.28280x0R/W1CRCVD_MASTER_ABORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57456Received Master Abort.This bit is set when a Requester receives a Completion with Unsupported Request Completion Status. For Functions that do not make Non-Posted Requests on their own behalf, the controller hardwires this bit to 0b.29290x0R/W1CSIGNALED_SYS_ERRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57470Signaled System Error.This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL message, and the SERR# Enable bit in the Command register is 1b. For Functions that do not send ERR_FATAL or ERR_NONFATAL messages, the controller hardwires this bit to 0b.30300x0R/W1CDETECTED_PARITY_ERRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57482Detected Parity Error.This bit is set by a Function whenever it receives a Poisoned TLP, regardless of the state the Parity Error Response bit in the Command register.31310x0R/W1CregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.CLASS_CODE_REVISION_IDCLASS_CODE_REVISION_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr575640x8R0x00000001PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE0_HDR_CLASS_CODE_REVISION_IDClass Code and Revision ID Register.falsefalsefalsefalseREVISION_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57505Revision ID.The value in this register specifies a Function specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should be viewed as a vendor defined extension to the Device ID.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.700x01RPROGRAM_INTERFACEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57525Programming Interface.This field identifies a specific register-level programming interface (if any) so that device independent software can interact with the Function.Encodings for interface are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are Reserved.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1580x00RSUBCLASS_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57544Sub-Class Code.Specifies a base class sub-class, which identifies more specifically the operation of the Function.Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are Reserved.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23160x00RBASE_CLASS_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57563Base Class Code.A code that broadly classifies the type of operation the Function performs.Encodings for base class, are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are Reserved.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REGBIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr576660xCR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REGBIST, Header Type, Latency Timer, and Cache Line Size Register.falsefalsefalsefalseCACHE_LINE_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57584Cache Line Size.The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However, legacy conventional PCI software may not always be able to program this register correctly especially in the case of Hot-Plug devices. This read-write register is implemented for legacy compatibility purposes but has no effect on any PCI Express devicebehavior.700x00R/WLATENCY_MASTER_TIMERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57597Latency Timer.The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this register to 00h.1580x00RHEADER_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57608Header Layout.This field identifies the layout of the second part of the predefined header.The controller uses 000 0000b encoding.22160x00RMULTI_FUNCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57632Multi-Function Device. - When set, indicates that the Device may contain multiple Functions, but not necessarily. Software is permitted to probe for Functions other than Function 0. - When clear, software must not probe for Functions other than Function 0 unless explicitly indicated by another mechanism, such as an ARI or SR-IOV Capability structure.Except where stated otherwise, it is recommended that this bit be set if there are multiple Functions, and clear if there is only one Function.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0RBISTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57665BIST.This register is used for control and status of BIST. For Functions that do not support BIST the controller hardwires the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link.Bit descriptions: - [31]: BIST Capable.When Set, this bit indicates that the Function supports BIST. When Clear, the Function does not support BIST. - [30]: Start BIST.If BIST Capable is Set, Set this bit to invoke BIST. The Function resets the bit when BIST is complete. Software is permitted to fail the device if this bit is not Clear (BIST is not complete) 2 seconds after it had been Set. Writing this bit to 0b has no effect. This bit must be hardwired to 0b if BIST Capable is Clear. - [29:28]: Reserved. - [27:24]: Completion Code.This field encodes the status of the most recent test. A value of 0000b means that the Function has passed its test. Non-zero values mean the Function failed. Function-specific failure codes can be encoded in the non-zero values. This field's value is only meaningful when BIST Capable is Set and Start BIST is Clear. This field must be hardwired to 0000b if BIST Capable is clear.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.BAR0_REGBAR0_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr577690x10R/W0x00000004PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE0_HDR_BAR0_REGBAR0 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR0_MEM_IOPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57701BAR0 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0RBAR0_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57729BAR0 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x2RBAR0_PREFETCHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57751BAR0 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0RBAR0_STARTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57768BAR0 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.BAR1_REGBAR1_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr578660x14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE0_HDR_BAR1_REGBAR1 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR1_MEM_IOPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57802BAR1 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0R/WBAR1_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57828BAR1 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x0R/WBAR1_PREFETCHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57848BAR1 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0R/WBAR1_STARTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57865BAR1 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.BAR2_REGBAR2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr579690x18R/W0x00000004PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE0_HDR_BAR2_REGBAR2 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR2_MEM_IOPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57901BAR2 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0RBAR2_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57929BAR2 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x2RBAR2_PREFETCHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57951BAR2 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0RBAR2_STARTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_SETDWC_pcie_dbi_cpcie_usp_4x8.csr57968BAR2 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.BAR3_REGBAR3_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr580660x1CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE0_HDR_BAR3_REGBAR3 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR3_MEM_IOPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58002BAR3 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0R/WBAR3_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58028BAR3 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x0R/WBAR3_PREFETCHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58048BAR3 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0R/WBAR3_STARTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58065BAR3 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.BAR4_REGBAR4_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr581690x20R/W0x00000004PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE0_HDR_BAR4_REGBAR4 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR4_MEM_IOPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58101BAR4 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0RBAR4_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58129BAR4 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x2RBAR4_PREFETCHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58151BAR4 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0RBAR4_STARTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58168BAR4 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.BAR5_REGBAR5_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr582660x24R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE0_HDR_BAR5_REGBAR5 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR5_MEM_IOPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58202BAR5 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0R/WBAR5_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58228BAR5 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x0R/WBAR5_PREFETCHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58248BAR5 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0R/WBAR5_STARTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58265BAR5 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.CARDBUS_CIS_PTR_REGCARDBUS_CIS_PTR_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr582870x28R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REGCardBus CIS Pointer Register.falsefalsefalsefalseCARDBUS_CIS_POINTERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58286CardBus CIS Pointer.Its functionality does not apply to PCI Express. It must be hardwired to 0000 0000h.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.3100x00000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REGSUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr583310x2CR0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REGSubsystem ID and Subsystem Vendor ID Register.These registers are used to uniquely identify the add-in card or subsystem where the PCI Express component resides. They provide a mechanism for vendors to distinguish their products from one another even though the assemblies may have the same PCI Express component on them (and, therefore, the same Vendor ID and Device ID).falsefalsefalsefalseSUBSYS_VENDOR_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58315Subsystem Vendor ID.Subsystem Vendor IDs can be obtained from the PCI SIG and are used to identify the vendor of the add-in card or subsystem. Values for the Subsystem ID are vendor-specific.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0000RSUBSYS_DEV_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58330Subsystem ID.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31160x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.EXP_ROM_BASE_ADDR_REGEXP_ROM_BASE_ADDR_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr583880x30R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REGExpansion ROM BAR Register. This register handles the base address and size information for this expansion ROM.falsefalsefalsefalseROM_BAR_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58361Expansion ROM Enable.This bit controls whether or not the Function accepts accesses to its expansion ROM. - When this bit is 0b, the Function's expansion ROM address space is disabled. - When the bit is 1b, address decoding is enabled using the parameters in the other part of the Expansion ROM Base Address register.The Memory Space Enable bit in the Command register has precedence over the Expansion ROM Enable bit. A Function must claim accesses to its expansion ROM only if both the Memory Space Enable bit and the Expansion ROM Enable bit are set.Note: The access attributes of this field are as follows: - Wire: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R - Dbi: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R 000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58369Reserved for future use.1010x000REXP_ROM_BASE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58387Expansion ROM Base Address.Upper 21 bits of the Expansion ROM base address.The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires.Note: The access attributes of this field are as follows: - Wire: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R - Dbi: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R 31110x000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.PCI_CAP_PTR_REGPCI_CAP_PTR_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr584220x34R0x00000040PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE0_HDR_PCI_CAP_PTR_REGCapabilities Pointer Register. This register is used to point to a linked list of capabilities implemented by a Function.falsefalsefalsefalseCAP_POINTERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58414Capabilities Pointer. This register points to a valid capability structure. Either this structure is the PCI Express Capability structure, or a subsequent list item points to the PCI Express Capability structure. The bottom two bits are reserved, the controller sets it to 00b. Software must mask these bits off before using this register as a pointer in Configuration Space to the first entry of a linked list of new capabilities.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.700x40RRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58421Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR.MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REGMAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr584880x3CR/W0x000001ffPE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REGMax_Lat, Min_Gnt, Interrupt Pin, and Interrupt Line Register. The Interrupt Line register communicates interrupt line routing information. The Interrupt Pin register identifies the legacy interrupt Message(s) the Function uses.falsefalsefalsefalseINT_LINEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58442Interrupt Line.The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin.Values in this register are programmed by system software and are system architecture specific. The Function itself does not use this value; rather the value in this register is used by device drivers and operating systems.700xffR/WINT_PINPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58479Interrupt Pin.The Interrupt Pin register identifies the legacy interrupt Message(s) the Function uses.The valid values are: - 01h, 02h, 03h, and 04h: Map to legacy interrupt Messages for INTA, INTB, INTC, and INTD respectively. - 00h: Indicates that the Function uses no legacy interrupt Message(s). - 05h through FFh: Reserved.PCI Express defines one legacy interrupt Message for a single Function device and up to four legacy interrupt Messages for a multi-Function device. For a single Function device, only INTA may be used.Any Function on a multi-Function device can use any of the INTx Messages. If a device implements a single legacy interrupt Message, it must be INTA; if it implements two legacy interrupt Messages, they must be INTA and INTB; and so forth.For a multi-Function device, all Functions may use the same INTx Message or each may have its own (up to a maximum of four Functions) or any combination thereof. A single Function can never generate an interrupt request on more than one INTx Message.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580x01RRSVDP_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58487Reserved for future use.31160x0000RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_PM_CAPPF0_PM_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr588750x40R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_PM_CAPPF PCI Power Management Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PM_CAP.CAP_ID_NXT_PTR_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PM_CAP.CON_STATUS_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PM_CAP.CAP_ID_NXT_PTR_REGCAP_ID_NXT_PTR_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr586810x0R0x03c35001PE0_DWC_pcie_ctl_DBI_Slave_PF0_PM_CAP_CAP_ID_NXT_PTR_REGPower Management Capabilities Register.falsefalsefalsefalsePM_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58508Capability ID.This field returns 01h to indicate that this is the PCI Power Management Capability. Each function may have only one item in its capability list with Capability ID set to 01h.700x01RPM_NEXT_POINTERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58525Next Capability Pointer.This field provides an offset into the function's configuration space pointing to the location of next item in the capabilities list. If there are no additional items in the capabilities list, this field is set to 00h.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580x50RPM_SPEC_VERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58542Version.This field provides the Power Management specification version. The controller hardwires this field to 011b for functions compliant to PCI Express Base Specification, Revision 4.0, Version 1.0>.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.18160x3RPME_CLKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58553PME Clock.Does not apply to PCI Express, the controller hardwires it to 0b.Note: This register field is sticky.19190x0R--20200x0rDSIPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58572Device Specific Initialization.The DSI bit indicates whether special initialization of this function is required.When set, indicates that the function requires a device specific initialization sequence following a transition to the D0uninitialized state.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.21210x0RAUX_CURRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58605Aux_Current.This 3 bit field reports the Vaux auxiliary current requirements for the function.If this function implements the Data Register, the controller hardwires this field to 000b.If PME_Support is 0 xxxxb (PME assertion from D3cold is not supported), the controller hardwires this field to 0000b.For functions where PME_Support is 1 xxxxb (PME assertion from D3cold is supported), and which do not implement the Data field, the following encodings apply: - b111 375mA Vaux Max. Current Required - b110 320mA Vaux Max. Current Required - b101 270mA Vaux Max. Current Required - b100 220mA Vaux Max. Current Required - b011 160mA Vaux Max. Current Required - b010 100mA Vaux Max. Current Required - b001 55mA Vaux Max. Current Required - b000 0 self poweredNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.24220x7RD1_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58621D1_Support.If this bit is set, this function supports the D1 Power Management state. Functions that do not support D1 must always return a value of 0b for this bit.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.25250x1RD2_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58637D2_Support.If this bit is set, this function supports the D2 Power Management state. Functions that do not support D2 must always return a value of 0b for this bit.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.26260x0RPME_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58680PME_Support.This 5-bit field indicates the power states in which the function may generate a PME and/or forward PME messages.A value of 0b for any bit indicates that the function is not capable of asserting PME while in that power state. - bit(27) X XXX1b - PME can be generated from D0 - bit(28) X XX1Xb - PME can be generated from D1 - bit(29) X X1XXb - PME can be generated from D2 - bit(30) X 1XXXb - PME can be generated from D3hot - bit(31) 1 XXXXb - PME can be generated from D3coldBit 31 (PME can be asserted from D3cold) represents a special case. Functions that set this bit require some sort of auxiliary power source. Implementation specific mechanisms are recommended to validate that the power source is available before setting this bit.Each bit that corresponds to a supported D-state must be set for PCI-PCI Bridge structures representing Ports on Root Complexes/Switches to indicate that the Bridge will forward PME Messages. Bit 31 must only be set if the Port is still able to forward PME Messages when main power is not available.The read value from this field is the write value && (sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1), where D1_SUPPORT and D2_SUPPORT are fields in this register.The reset value PME_SUPPORT_n && (sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1), where PME_SUPPORT_n is a configuration parameter.Note: The access attributes of this field are as follows: - Wire: R - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.3127RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PM_CAP.CON_STATUS_REGCON_STATUS_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr588740x4R/W0x00000008PE0_DWC_pcie_ctl_DBI_Slave_PF0_PM_CAP_CON_STATUS_REGPower Management Control and Status Register.This register is used to manage the PCI function's power management state as well as to enable/monitor PMEs.falsefalsefalsefalsePOWER_STATEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58725PowerState.This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below.You can write to this register; however, the read-back value is the actual power state, not the write value. If you attempt to write an unsupported, optional state to this field, the write operation completes normally; however, the data is discarded and no state change occurs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 10R/WfalsetruefalseD00x0D0 power stateD10x1D1 power stateD20x2D2 power stateD3hot0x3D3hot D3hot power stateRSVDP_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58733Reserved for future use.220x0RNO_SOFT_RSTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58759No_Soft_Reset.This bit indicates the state of the function after writing the PowerState field to transition the function from D3hot to D0. - When set, this transition preserves internal function state. The function is in D0Active and no additional software intervention is required. - When clear, this transition results in undefined internal function state.Regardless of this bit, functions that transition from D3hot to D0 by Fundamental Reset will return to D0Uninitialized with only PME context preserved if PME is supported and enabled.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.330x1RRSVDP_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58767Reserved for future use.740x0RPME_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58788PME_En. - When set, the function is permitted to generate a PME. - When clear, the function is not permitted to generate a PME.If PME_Support is 1 xxxxb (PME generation from D3cold) or the function consumes Aux power and Aux power is available this bit is RWS and the bit is not modified by Conventional Reset or FLR.If PME_Support is 0 xxxxb, this field is not sticky (RW).If PME_Support is 0 0000b, the controller hardwires this bit to 0b.Note: This register field is sticky.88R/WDATA_SELECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58800Data_Select.This 4-bit field is used to select which data is to be reported through the Data and Data_Scale field. If the Data field is not implemented, this field must be hardwired to 0000b.1290x0RDATA_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58814Data_Scale.This field indicates the scaling factor to be used when interpreting the value of the Data field. The value and meaning of this field varies depending on which data value has been selected by the Data_Select field. For more details, see 7.5.2.3 section of PCI Express Base Specification.14130x0RPME_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58833PME_Status.This bit is set when the function normally generates a PME signal. The value of this bit is not affected by the value of the PME_En bit.If PME_Support bit 31 of the Power Management Capabilities register is clear, this bit is permitted to be hardwired to 0b.Functions that consume Aux power must preserve the value of this sticky register when Aux power is available. In such functions, this register value is not modified by Conventional Reset or FLR.15150x0R/W1CRSVDP_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58841Reserved for future use.21160x00RB2_B3_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58851B2B3 Support for D3hot.For a description of this standard PCIe register field, see the PCI Express Base Specification.22220x0RBUS_PWR_CLK_CON_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58861Bus Power/Clock Control Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.23230x0RDATA_REG_ADD_INFOPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58873Data.This field is used to report the state dependent data requested by the Data_Select field. The value of this field is scaled by the value reported by the Data_Scale field.31240x00RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAPPF0_MSI_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr592730x50R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_MSI_CAPPF MSI Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.PCI_MSI_CAP_ID_NEXT_CTRL_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_04H_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_08H_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_0CH_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_10H_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_14H_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.PCI_MSI_CAP_ID_NEXT_CTRL_REGPCI_MSI_CAP_ID_NEXT_CTRL_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr590540x0R/W0x038a7005PE0_DWC_pcie_ctl_DBI_Slave_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REGMSI Capability Header and Message Control Register.falsefalsefalsefalsePCI_MSI_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58893Capability ID.Indicates the MSI Capability structure. This field returns a Capability ID of 05h indicating that this is an MSI Capability structure.700x05RPCI_MSI_CAP_NEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58910Next Capability Pointer.This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580x70RPCI_MSI_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58927MSI Enable. - If set and the MSI-X Enable bit in the MSI-X Message Control register is clear, the function is permitted to use MSI to request service and is prohibited from using INTx interrupts. System configuration software sets this bit to enable MSI. A device driver is prohibited from writing this bit to mask a function's service request. For more details on control of INTx interrupts, see section 7.5.1.1 of PCI Express Base Specification. - If clear, the function is prohibited from using MSI to request service.16160x0R/WPCI_MSI_MULTIPLE_MSG_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58953Multiple Message Capable.System software reads this field to determine the number of requested vectors. The number of requested vectors must be aligned to a power of two (if a function requires three vectors, it requests four by initializing this field to 010b). The encoding is defined as: - 000b: 1 vector requested - 001b: 2 vectors requested - 010b: 4 vectors requested - 011b: 8 vectors requested - 100b: 16 vectors requested - 101b: 32 vectors requested - 110b: Reserved - 111b: ReservedNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.19170x5RPCI_MSI_MULTIPLE_MSG_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr58978Multiple Message Enable.Software writes to this field to indicate the number of allocated vectors (equal to or less than the number of requested vectors). The number of allocated vectors is aligned to a power of two. If a function requests four vectors (indicated by a Multiple Message Capable encoding of 010b), system software can allocate either four, two, or one vector by writing a 010b, 001b, or 000b to this field, respectively. When MSI is enabled, a function will be allocated at least 1 vector. The encoding is defined as: - 000b: 1 vector allocated - 001b: 2 vectors allocated - 010b: 4 vectors allocated - 011b: 8 vectors allocated - 100b: 16 vectors allocated - 101b: 32 vectors allocated - 110b: Reserved - 111b: Reserved22200x0R/WPCI_MSI_64_BIT_ADDR_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr5899864 bit address capable. - If set, the function is capable of sending a 64-bit message address. - If clear, the function is not capable of sending a 64-bit message address.This bit must be set if the function is a PCI Express Endpoint.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.23230x1RPCI_PVM_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59011Per-Vector Masking Capable. - If set, the function supports MSI Per-Vector Masking. - If clear, the function does not support MSI Per-Vector Masking.This bit must be set if the function is a PF or VF within an SR-IOV Device.24240x1RPCI_MSI_EXT_DATA_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59028Extended Message Data Capable. - If set, the function is capable of providing Extended Message Data. - If clear, the function does not support providing Extended Message Data.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.25250x1RPCI_MSI_EXT_DATA_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59045Extended Message Data Enable. - If set, the function is enabled to provide Extended Message Data. - If clear, the function is not enabled to provide Extended Message Data.Note: The access attributes of this field are as follows: - Wire: PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_MSI_EXT_DATA_CAP ? RW : RO - Dbi: PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_MSI_EXT_DATA_CAP ? RW : RO 26260x0R/WRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59053Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_04H_REGMSI_CAP_OFF_04H_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr590820x4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_04H_REGMessage Address Register for MSI (Offset 04h).falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59065Reserved for future use.100x0RPCI_MSI_CAP_OFF_04HPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59081Message Address - System-specified message address.If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG register) is set, the contents of this field specify the DWORD-aligned address (Address[31:02]) for the MSI transaction. Address[1:0] are set to 00b.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3120x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_08H_REGMSI_CAP_OFF_08H_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr591620x8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_08H_REGFor a function that supports a 32-bit message address, - bits[31:16] of this register represent the Extended Message Data, and - bits[15:0] of this register represent the Message DataFor a function that supports a 64-bit message address (bit 23 in PCI_MSI_CAP_ID_NEXT_CTRL_REG register set), this register represents the Message Upper Address Register for MSI (Offset 08h). It specifies the Message Upper Address (System-specified message upper address). This register is required for PCI Express Endpoints and is optional for other function types. If the Message Enable bit (bit 0 of the Message Control register) is set, the contents of this register (if non-zero) specify the upper 32-bits of a 64-bit message address (Address[63:32]). If the contents of this register are zero, the Function uses the 32 bit address specified by the Message Address register.falsefalsefalsefalsePCI_MSI_CAP_OFF_08HPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59132For a function that supports a 32-bit message address, this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set, the function sends a DWORD Memory Write transaction using Message Data for the lower 16 bits. All 4 Byte Enables are set. The Multiple Message Enable field (bits 22:20 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) defines the number of low order message data bits the function is permitted to modify to generate its system software allocated vectors. For example, a Multiple Message Enable encoding of 010b indicates the function has been allocated four vectors and is permitted to modify message data bits 1 and 0 (a function modifies the lower message data bits to generate the allocated number of vectors). If the Multiple Message Enable field is 000b, the Function is not permitted to modify the message data.For a function that supports a 64-bit message address, it contains lower 16 bits of the Message Upper Address.Note: The access attributes of this field are as follows: - Wire: PCI_MSI_64_BIT_ADDR_CAP ? R/W : R - Dbi: PCI_MSI_64_BIT_ADDR_CAP ? R/W : R 1500x0000R/WPCI_MSI_CAP_OFF_0AHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59161For a function that supports a 32-bit message address, this field contains Extended Message Data (System-specified message data). For the MSI Capability structures without per-vector masking, it must be implemented if the Extended Message Data Capable bit is set; otherwise, it is outside the MSI Capability structure and undefined. For the MSI Capability structures with Per-vector Masking, it must be implemented if the Extended Message Data Capable bit is set; otherwise, it is RsvdP. If the Extended Message Data Enable bit (bit 26 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set, the DWORD Memory Write transaction uses Extended Message Data for the upper 16 bits; otherwise, it uses 0000h for the upper 16 bits.For a function that supports a 64-bit message address, it contains upper 16 bits of the Message Upper Address.Note: The access attributes of this field are as follows: - Wire: PCI_MSI_64_BIT_ADDR_CAP || `DEFAULT_EXT_MSI_DATA_CAPABLE ? R/W : R - Dbi: PCI_MSI_64_BIT_ADDR_CAP || `DEFAULT_EXT_MSI_DATA_CAPABLE ? R/W : R 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_0CH_REGMSI_CAP_OFF_0CH_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr592270xCR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REGFor a function that supports a 32-bit message address, this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message address, this register contains Message Data.falsefalsefalsefalsePCI_MSI_CAP_OFF_0CHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59205For a function that supports a 32-bit message address, this field contains the lower Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set.For a function that supports a 64-bit message address, this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set, the function sends a DWORD Memory Write transaction using Message Data for the lower 16 bits. All 4 Byte Enables are set. The Multiple Message Enable field (bits 22:20 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) defines the number of low order message data bits the function is permitted to modify to generate its system software allocated vectors. For example, a Multiple Message Enable encoding of 010b indicates the function has been allocated four vectors and is permitted to modify message data bits 1 and 0 (a function modifies the lower message data bits to generate the allocated number of vectors). If the Multiple Message Enable field is 000b, the Function is not permitted to modify the message data.Note: The access attributes of this field are as follows: - Wire: PCI_MSI_64_BIT_ADDR_CAP || MSI_PVM_EN ? R/W : R - Dbi: PCI_MSI_64_BIT_ADDR_CAP || MSI_PVM_EN ? R/W : R 1500x0000R/WPCI_MSI_CAP_OFF_0EHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59226For a function that supports a 32-bit message address, this field contains the upper Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set.For a function that supports a 64-bit message address, this field contains Message Data (System-specified message data).Note: The access attributes of this field are as follows: - Wire: (!MSI_64_EN && MSI_PVM_EN_VALUE) ? RW: MSI_64_EN && DEFAULT_EXT_MSI_DATA_CAPABLE ? RW : RO - Dbi: (!MSI_64_EN && MSI_PVM_EN_VALUE) ? RW: MSI_64_EN && DEFAULT_EXT_MSI_DATA_CAPABLE ? RW : RO 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_10H_REGMSI_CAP_OFF_10H_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr592560x10R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_10H_REGFor a function that supports a 32-bit message address, this register contains the Pending Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message address, this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set.falsefalsefalsefalsePCI_MSI_CAP_OFF_10HPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59255Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For 32-bit contains Pending Bits. For 64-bit, contains Mask Bits.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: PCI_MSI_64_BIT_ADDR_CAP && MSI_PVM_EN ? R/W : R - Dbi: PCI_MSI_64_BIT_ADDR_CAP && MSI_PVM_EN ? R/W : R 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_14H_REGMSI_CAP_OFF_14H_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr592720x14R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_14H_REGPending Bits Register for MSI. This register is used for a function that supports a 64-bit message address when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set.falsefalsefalsefalsePCI_MSI_CAP_OFF_14HPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59271Pending Bits. For each pending bit that is set, the function has a pending associated message.3100x00000000RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAPPF0_PCIE_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr620530x70R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_PCIE_CAPPF PCI Express Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL_DEVICE_STATUSregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.LINK_CONTROL_LINK_STATUS_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL2_DEVICE_STATUS2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.LINK_CONTROL2_LINK_STATUS2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGPCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr594300x0R0x0002b010PE0_DWC_pcie_ctl_DBI_Slave_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGPCI Express Capabilities, ID, Next Pointer Register.falsefalsefalsefalsePCIE_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59291Capability ID. Indicates the PCI Express Capability structure. This field must return a Capability ID of 10h indicating that this is a PCI Express Capability structure.700x10RPCIE_CAP_NEXT_PTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59306Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580xb0RPCIE_CAP_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59330Capability Version. Indicates PCI-SIG defined PCI Express Capability structure version number.A version of the specification that changes the PCI Express Capability structure in a way that is not otherwise identifiable (for example, through a new Capability field) is permitted to increment this field. All such changes to the PCI Express Capability structure must be software-compatible. Software must check for Capability Version numbers that are greater than or equal to the highest number defined when the software is written, as functions reporting any such Capability Version numbers will contain a PCI Express Capability structure that is compatible with that piece of software.The controller hardwires this field to 2h for functions compliant to PCI Express Base Specification, Revision 4.0, Version 1.0.Note: This register field is sticky.19160x2RPCIE_DEV_PORT_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59357Device/Port Type. Indicates the specific type of this PCI Express function.Note: Different functions in a Multi-Function Device can generally be of different types.Defined encodings for functions that implement a Type 00h PCI Configuration Space header are: - 0000b PCI Express Endpoint - 0001b Legacy PCI Express EndpointDefined encodings for functions that implement a Type 01h PCI Configuration Space header are: - 0100b Root Port of PCI Express Root Complex - 0101b Upstream Port of PCI Express Switch - 0110b Downstream Port of PCI Express SwitchAll other encodings are Reserved.Note: Different Endpoint types have notably different requirements in Section 1.3.2 of PCI Express Base Specification regarding I/O resources, Extended Configuration Space, and other capabilities.2320RPCIE_SLOT_IMPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59373Slot Implemented. When set, this bit indicates that the Link associated with this Port is connected to a slot (as compared to being connected to a system-integrated device or being disabled). This bit is valid for Downstream Ports. This bit is undefined for Upstream Ports.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 24240x0RPCIE_INT_MSG_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59415PCIE Interrupt Message Number.For a description of this standard PCIe register field, see the PCI Express Base Specification.Interrupt Message Number. This field indicates which MSI/MSI-X vector is used for the interrupt message generated in association with any of the status bits of this Capability structure.For MSI, the value in this field indicates the offset between the base Message Data and the interrupt message that is generated. Hardware is required to update this field so that it is correct if the number of MSI Messages assigned to the Function changes when software writes to the Multiple Message Enable field in the MSI Message Control register.For MSI-X, the value in this field indicates which MSI-X Table entry is used to generate the interrupt message. The entry must be one of the first 32 entries even if the Function implements more than 32 entries. For a given MSI-X implementation, the entry must remain constant.If both MSI and MSI-X are implemented, they are permitted to use different vectors, though software is permitted to enable only one mechanism at a time. If MSI-X is enabled, the value in this field must indicate the vector for MSI-X. If MSI is enabled or neither is enabled, the value in this field must indicate the vector for MSI. If software enables both MSI and MSI-X at the same time, the value in this field is undefined.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.29250x00RRSVDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59422Reserved.30300x0RRSVDP_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59429Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES_REGDEVICE_CAPABILITIES_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr597200x4R0x00008fe1PE0_DWC_pcie_ctl_DBI_Slave_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REGDevice Capabilities Register.The Device Capabilities register identifies PCI Express device function specific capabilities.falsefalsefalsefalsePCIE_CAP_MAX_PAYLOAD_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59462Max_Payload_Size Supported.This field indicates the maximum payload size that the function can support for TLPs.Defined encodings are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max payload size - 011b: 1024 bytes max payload size - 100b: 2048 bytes max payload size - 101b: 4096 bytes max payload size - 110b: Reserved - 111b: ReservedThe functions of a Multi-Function Device are permitted to report different values for this field.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.200x1RPCIE_CAP_PHANTOM_FUNC_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59516Phantom Functions Supported.This field indicates the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called Phantom Functions) with the Tag identifier (see Section 2.2.6.2 of PCI Express Base Specification for a description of Tag Extensions).With every Function in an ARI Device, the Phantom Functions Supported field must be set to 00b. The remainder of this field description applies only to non-ARI Multi-Function Devices.This field indicates the number of most significant bits of the Function Number portion of Requester ID that are logically combined with the Tag identifier.Defined encodings are: - 00b: No Function Number bits are used for Phantom Functions. Multi-Function Devices are permitted to implement up to 8 independent functions. - 01b: The most significant bit of the Function number in Requester ID is used for Phantom Functions; a Multi-Function Device is permitted to implement Functions 0-3. Functions 0, 1, 2, and 3 are permitted to use Function Numbers 4, 5, 6, and 7 respectively as Phantom Functions. - 10b: The two most significant bits of Function Number in Requester ID are used for Phantom Functions; a Multi-Function Device is permitted to implement Functions 0-1. Function 0 is permitted to use Function Numbers 2, 4, and 6 for Phantom Functions. Function 1 is permitted to use Function Numbers 3, 5, and 7 as Phantom Functions. - 11b: All 3 bits of Function Number in Requester ID used for Phantom Functions. The device must have a single Function 0 that is permitted to use all other Function Numbers as Phantom Functions.Note: Phantom Function support for the function must be enabled by the Phantom Functions Enable field in the Device Control register before the Function is permitted to use the Function Number field in the Requester ID for Phantom Functions.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.430x0RPCIE_CAP_EXT_TAG_SUPPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59543Extended Tag Field Supported.This bit, in combination with the 10-Bit Tag Requester Supported bit in the Device Capabilities 2 register, indicates the maximum supported size of the Tag field as a Requester. This bit must be set if the 10-Bit Tag Requester Supported bit is set.Defined encodings are: - 0b: 5-bit Tag field supported - 1b: 8-bit Tag field supportedNote: 8-bit Tag field generation must be enabled by the Extended Tag Field Enable bit in the Device Control register of the Requester Function before 8-bit Tags can be generated by the Requester. See Section 2.2.6.2 of PCI Express Base Specificationfor interactions with enabling the use of 10-Bit Tags.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.550x1RPCIE_CAP_EP_L0S_ACCPT_LATENCYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59578Endpoint L0s Acceptable Latency. This field indicates the acceptable total latency that an Endpoint can withstand due to the transition from L0s state to the L0 state. It is essentially an indirect measure of the Endpoint’s internal buffering.Power management software uses the reported L0s Acceptable Latency number to compare against the L0s exit latencies reported by all components comprising the data path from this Endpoint to the Root Complex Root Port to determine whether ASPM L0s entry can be used with no loss of performance.Defined encodings are: - 000b: Maximum of 64 ns - 001b: Maximum of 128 ns - 010b: Maximum of 256 ns - 011b: Maximum of 512 ns - 100b: Maximum of 1 us - 101b: Maximum of 2 us - 110b: Maximum of 4 us - 111b: No limitFor functions other than Endpoints, this field is Reserved and the controller hardwires it to 000b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.860x7RPCIE_CAP_EP_L1_ACCPT_LATENCYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59613Endpoint L1 Acceptable Latency. This field indicates the acceptable latency that an Endpoint can withstand due to the transition from L1 state to the L0 state. It is essentially an indirect measure of the Endpoint’s internal buffering.Power management software uses the reported L1 Acceptable Latency number to compare against the L1 Exit Latencies reported (see below) by all components comprising the data path from this Endpoint to the Root Complex Root Port to determine whether ASPM L1 entry can be used with no loss of performance.Defined encodings are: - 000b: Maximum of 1 us - 001b Maximum of 2 us - 010b Maximum of 4 us - 011b Maximum of 8 us - 100b Maximum of 16 us - 101b Maximum of 32 us - 110b Maximum of 64 us - 111b No limitFor functions other than Endpoints, this field is Reserved and the controller hardwires it to 000b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W (Sticky) else R(Sticky) Note: This register field is sticky.1190x7RRSVDP_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59620Reserved for future use.14120x0RPCIE_CAP_ROLE_BASED_ERR_REPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59640Role-Based Error Reporting. When set, this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification, Revision 1.0a, and later incorporated into PCI Express Base Specification, Revision 1.1. This bit must be set by all functions conforming to the ECN, PCI Express Base Specification, Revision 1.1., or subsequent PCI Express Base Specification revisions.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.15150x1RRSVDP_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59647Reserved for future use.17160x0RPCIE_CAP_CAP_SLOT_PWR_LMT_VALUEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59673Captured Slot Power Limit Value.For a description of this standard PCIe register field, see the PCI Express Base Specification.Captured Slot Power Limit Value (Upstream Ports only). In combination with the Captured Slot Power Limit Scale value, specifies the upper limit on power available to the adapter.Power limit (in Watts) is calculated by multiplying the value in this field by the value in the Captured Slot Power Limit Scale field except when the Captured Slot Power Limit Scale field equals 00b (1.0x) and the Captured Slot Power Limit Value exceeds EFh, then alternative encodings are used (for more details, see section 7.5.3.9 of PCI Express Base Specification).This value is set by the Set_Slot_Power_Limit Message or hardwired to 00h (for more details, see section 6.9 of PCI Express Base Specification).2518RPCIE_CAP_CAP_SLOT_PWR_LMT_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59693Captured Slot Power Limit Scale.For a description of this standard PCIe register field, see the PCI Express Base Specification.Captured Slot Power Limit Scale (Upstream Ports only). Specifies the scale used for the Slot Power Limit Value.Range of Values: - 00b: 1.0x - 01b: 0.1x - 10b: 0.01x - 11b: 0.001xThis value is set by the Set_Slot_Power_Limit Message or hardwired to 00b (for more details, see section 6.9 of PCI Express Base Specification).2726RPCIE_CAP_FLR_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59712Function Level Reset Capability. A value of 1b indicates the function supports the optional Function Level Reset mechanism described in section 6.6.2 of of PCI Express Base Specification.This bit applies to Endpoints only. For all other function types the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.28280x0RRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59719Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL_DEVICE_STATUSDEVICE_CONTROL_DEVICE_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr600690x8R/W0x00002010PE0_DWC_pcie_ctl_DBI_Slave_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUSDevice Control and Device Status Register.This register controls PCI Express device specific parameters and provides information about PCI Express device (function) specific parameters.falsefalsefalsefalsePCIE_CAP_CORR_ERR_REPORT_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59743Correctable Error Reporting Enable.This bit, in conjunction with other bits, controls sending ERR_COR Messages (for more details, see section 6.2.5, section 6.2.6, and section 6.2.10.2 of PCI Express Base Specification). For a Multi-Function device, this bit controls error reporting for each function from point-of-view of the respective function.For a Root Port, the reporting of correctable errors is internal to the root. No external ERR_COR Message is generated.000x0R/WPCIE_CAP_NON_FATAL_ERR_REPORT_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59760Non-Fatal Error Reporting Enable.This bit, in conjunction with other bits, controls sending ERR_NONFATAL Messages (for more details, see section 6.2.5 and Section 6.2.6 of PCI Express Base Specification). For a Multi-Function Device, this bit controls error reporting for each function from point-of-view of the respective Function.For a Root Port, the reporting of Non-fatal errors is internal to the root. No external ERR_NONFATAL Message is generated.110x0R/WPCIE_CAP_FATAL_ERR_REPORT_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59776Fatal Error Reporting Enable.This bit, in conjunction with other bits, controls sending ERR_FATAL Messages (for more details, see section 6.2.5 and section 6.2.6 of of PCI Express Base Specification). For a Multi-Function device, this bit controls error reporting for each function from point-of-view of the respective function.For a Root Port, the reporting of Fatal errors is internal to the root. No external ERR_FATAL Message is generated.220x0R/WPCIE_CAP_UNSUPPORT_REQ_REP_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59790Unsupported Request Reporting Enable.This bit, in conjunction with other bits, controls the signaling of Unsupported Request Errors by sending error Messages (for more details, see section 6.2.5 and section 6.2.6 of PCI Express Base Specification). For a Multi-Function Device, this bit controls error reporting for each Function from point-of-view of the respective Function.330x0R/WPCIE_CAP_EN_REL_ORDERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59810Enable Relaxed Ordering.If this bit is set, the function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering (for more details, see section 2.2.6.4 and section 2.4 of PCI Express Base Specification).For a function that never sets the Relaxed Ordering attribute in transactions it initiates as a Requester, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x1R/WPCIE_CAP_MAX_PAYLOAD_SIZE_CSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59847Max_Payload_Size.This field sets maximum TLP payload size for the Function. As a Receiver, the Function must handle TLPs as large as the set value. As a Transmitter, the Function must not generate TLPs exceeding the set value. Permissible values that can be programmed are indicated by the Max_Payload_Size Supported field (PCIE_CAP_MAX_PAYLOAD_SIZE) in the Device Capabilities (DEVICE_CAPABILITIES_REG) register (for more details, see section 7.5.3.3 of PCI Express Base Specification).Defined encodings for this field are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max payload size - 011b: 1024 bytes max payload size - 100b: 2048 bytes max payload size - 101b: 4096 bytes max payload size - 110b: Reserved - 111b: ReservedFor Functions that support only the 128-byte max payload size, the controller hardwires this field to 000b.System software is not required to program the same value for this field for all the Functions of a Multi-Function device (for more details, see section 2.2.2 of PCI Express Base Specification).For ARI Devices, Max_Payload_Size is determined solely by the setting in Function0. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component.750x0R/WPCIE_CAP_EXT_TAG_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59880Extended Tag Field Enable.This bit, in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register, determines how many Tag field bits a Requester is permitted to use.When the 10-Bit Tag Requester Enable bit is clear, - If the Extended Tag Field Enable bit is set, the function is permitted to use an 8-bit Tag field as a Requester - If the Extended Tag Field Enable bit is clear, the Function is restricted to a 5-bit Tag fieldSee section 2.2.6.2 of PCI Express Base Specification for required behavior when the 10-Bit Tag Requester Enable bit is set.If software changes the value of the Extended Tag Field Enable bit while the function has outstanding Non-Posted Requests, the result is undefined.For functions that do not implement this capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: DEVICE_CAPABILITIES_REG.PCIE_CAP_EXT_TAG_SUPP ? RW : RO - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_EXT_TAG_SUPP ? RW : RO 88R/WPCIE_CAP_PHANTOM_FUNC_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59916Phantom Functions Enable.This bit, in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register, determines how many Tag field bits a Requester is permitted to use.When the 10-Bit Tag Requester Enable bit is clear, - If this bit is set, it enables a function to use unclaimed functions as Phantom functions to extend the number of outstanding transaction identifiers - If this bit is clear, the function is not allowed to use Phantom functionsFor more details, see section 2.2.6.2 of PCI Express Base Specification.Software should not change the value of this bit while the function has outstanding Non-Posted Requests; otherwise, the result is undefined.For functions that do not implement this capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: DEVICE_CAPABILITIES_REG.PCIE_CAP_PHANTOM_FUNC_SUPPORT ? RW : RO - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_PHANTOM_FUNC_SUPPORT ? RW : RO 99RPCIE_CAP_AUX_POWER_PM_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59943Aux Power PM Enable.This bit is derived by sampling the sys_aux_pwr_det input.When set this bit, enables a function to draw Aux power independent of PME Aux power. Functions that require Aux power on legacy operating systems should continue to indicate PME Aux power requirements. Aux power is allocated as requested in the Aux_Current field of the Power Management Capabilities register (PMC), independent of the PME_En bit in the Power Management Control/Status register (PMCSR). For Multi-Function devices, a component is allowed to draw Aux power if at least one of the functions has this bit set.Note: Functions that consume Aux power must preserve the value of this sticky register when Aux power is available. In such functions, this bit is not modified by Conventional Reset.For functions that do not implement this capability, the controller hardwires this bit to 0b.Note: This register field is sticky.1010R/WPCIE_CAP_EN_NO_SNOOPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59970Enable No Snoop.If this bit is set, the function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency (see section 2.2.6.5 in PCI Express Base Specification).Note: Setting this bit to 1b should not cause a function to set the No Snoop attribute on all transactions that it initiates. Even when this bit is set, a function is only permitted to set the No Snoop attribute on a transaction when it can guarantee that the address of the transaction is not stored in any cache in the system.The controller hardwires this bit 0b if a function would never set the No Snoop attribute in transactions it initiates.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 11110x0RPCIE_CAP_MAX_READ_REQ_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr59993Max_Read_Request_Size.This field sets the maximum Read Request size for the function as a Requester. The function must not generate Read Requests with a size exceeding the set value. Defined encodings for this field are: - 000b: 128 bytes maximum Read Request size - 001b: 256 bytes maximum Read Request size - 010b: 512 bytes maximum Read Request size - 011b: 1024 bytes maximum Read Request size - 100b: 2048 bytes maximum Read Request size - 101b: 4096 bytes maximum Read Request size - 110b: Reserved - 111b: ReservedFor functions that do not generate Read Requests larger than 128 bytes and functions that do not generate Read Requests on their own behalf, the controller implements this field as Read Only (RO) with a value of 000b.14120x2R/W--16150x0rPCIE_CAP_NON_FATAL_ERR_DETECTEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60011Non-Fatal Error Detected. This bit indicates status of Non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function device, each function indicates status of errors as perceived by the respective Function.For functions supporting Advanced Error Handling, errors are logged in this register regardless of the settings of the Uncorrectable Error Mask register.17170x0R/W1C--18180x0rPCIE_CAP_UNSUPPORTED_REQ_DETECTEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60026Unsupported Request Detected.This bit indicates that the function received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function Device, each function indicates status of errors as perceived by the respective function.19190x0R/W1CPCIE_CAP_AUX_POWER_DETECTEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60039AUX Power Detected.Functions that require Aux power report this bit as set if Aux power is detected by the function.This bit is derived by sampling the sys_aux_pwr_det input.2020RPCIE_CAP_TRANS_PENDINGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60060Transactions Pending.Endpoints:When set, this bit indicates that the function has issued Non-Posted Requests that have not been completed. A Function reports this bit cleared only when all outstanding Non-Posted Requests have completed or have been terminated by the Completion Timeout mechanism. This bit must also be cleared upon the completion of an FLR.Root and Switch Ports:The controller hardwires this bit to 0b.2121RRSVDP_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60068Reserved for future use.31220x000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES_REGLINK_CAPABILITIES_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr604200xCR0x00400c84PE0_DWC_pcie_ctl_DBI_Slave_PF0_PCIE_CAP_LINK_CAPABILITIES_REGLink Capabilities Register.The Link Capabilities register identifies PCI Express Link specific capabilities.falsefalsefalsefalsePCIE_CAP_MAX_LINK_SPEEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60109Max Link Speed.This field indicates the maximum Link speed of the associated Port.The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the maximum Link speed.Defined encodings are: - 0001b: Supported Link Speeds Vector field bit 0 - 0010b: Supported Link Speeds Vector field bit 1 - 0011b: Supported Link Speeds Vector field bit 2 - 0100b: Supported Link Speeds Vector field bit 3 - 0101b: Supported Link Speeds Vector field bit 4 - 0110b: Supported Link Speeds Vector field bit 5 - 0111b: Supported Link Speeds Vector field bit 6All other encodings are reserved.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.In M-PCIe mode, the reset and dynamic values of this field are calculated by the controller.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.300x4RPCIE_CAP_MAX_LINK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60145Maximum Link Width.This field indicates the maximum Link width (xN – corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port), adapter connector (Upstream Port), or in the case of component-to-component connections, the actual wired connection width.Defined encodings are: - 00 0001b x1 - 00 0010b x2 - 00 0100b x4 - 00 1000b x8 - 00 1100b x12 - 01 0000b x16 - 10 0000b x32All other encodings are Reserved.Multi-Function devices associated with an Upstream Port must report the same value in this field for all functions.For a description of this standard PCIe register field, see the PCI Express Base Specification.In M-PCIe mode, the reset and dynamic values of this field are calculated by the controller.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.940x08RPCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60170Active State Power Management (ASPM) Support. This field indicates the level of ASPM supported on the given PCI Express Link. For more details on ASPM support requirements, see section 5.4.1 of PCI Express Base Specification.Defined encodings are: - 00b: No ASPM Support - 01b: L0s Supported - 10b: L1 Supported - 11b: L0s and L1 SupportedMulti-Function devices associated with an Upstream Port must report the same value in this field for all functions.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.11100x3RPCIE_CAP_L0S_EXIT_LATENCYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60228L0s Exit Latency.This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. If L0s is not supported, the value is undefined; however, see the Implementation Note "Potential Issues With Legacy Software When L0s is Not Supported" in section 5.4.1.1 of PCI Express Base Specification for the recommended value.Defined encodings are: - 000b: Less than 64 ns - 001b: 64 ns to less than 128 ns - 010b: 128 ns to less than 256 ns - 011b: 256 ns to less than 512 ns - 100b: 512 ns to less than 1 us - 101b: 1 us to less than 2 us - 110b: 2 us to 4 us - 111b: More than 4 usNote: Exit latencies may be influenced by PCI Express reference clock configuration depending upon whether a component uses a common or separate reference clock.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.There are two each of these register fields, this one and a shadow one at the same address.The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the controller and which one is accessed by a read request.Common Clock operation is supported (possible) in the controller when one or more of the following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCYCommon Clock operation is enabled in the controller when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG).The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1412RPCIE_CAP_L1_EXIT_LATENCYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60282L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from ASPM L1 to L0. If ASPM L1 is not supported, the value is undefined.Defined encodings are: - 000b: Less than 1us - 001b: 1 us to less than 2 us - 010b: 2 us to less than 4 us - 011b: 4 us to less than 8 us - 100b: 8 us to less than 16 us - 101b: 16 us to less than 32 us - 110b: 32 us to 64 us - 111b: More than 64 μsNote: Exit latencies may be influenced by PCI Express reference clock configuration depending upon whether a component uses a common or separate reference clock.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.There are two each of these register fields, this one and a shadow one at the same address.The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the controller and which one is accessed by a read request.Common Clock operation is supported (possible) in the controller when one or more of the following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCYCommon Clock operation is enabled in the controller when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG).The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1715RPCIE_CAP_CLOCK_POWER_MANPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60320Clock Power Management. For Upstream Ports, a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) via the "clock request" (CLKREQ#) mechanism when the Link is in the L1 and L2/L3 Ready Link states. A value of 0b indicates the component does not have this capability and that reference clock(s) must not be removed in these Link states.L1 PM Substates defines other semantics for the CLKREQ# signal, which are managed independently of Clock Power Management.This Capability is applicable only in form factors that support "clock request" (CLKREQ#) capability.For a Multi-Function device associated with an Upstream Port, each Function indicates its capability independently. Power Management configuration software must only permit reference clock removal if all functions of the Multi-Function device indicate a 1b in this bit. For ARI Devices, all Functions must indicate the same value in this bit.For Downstream Ports, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0RPCIE_CAP_SURPRISE_DOWN_ERR_REP_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60336Surprise Down Error Reporting Capable. For a Downstream Port, this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition.For Upstream Ports and components that do not support this optional capability, the controller hardwires this bit to 0b.Note: This register field is sticky.19190x0RPCIE_CAP_DLL_ACTIVE_REP_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60355Data Link Layer Link Active Reporting Capable. For a Downstream Port, the controller hardwires this bit to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine. For a hot-plug capable Downstream Port (as indicated by the Hot-Plug Capable bit of the Slot Capabilities register) or a Downstream Port that supports Link speeds greater than 5.0 GT/s, the controller hardwires this bit to 1b.For Upstream Ports and components that do not support this optional capability, the controller hardwires this bit to 0b.20200x0RPCIE_CAP_LINK_BW_NOT_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60377Link Bandwidth Notification Capability. A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting Links wider than x1 and/or multiple Link speeds.This field is not applicable and is Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability the controller hardwires this bit to 0b.Note: This register field is sticky.21210x0RPCIE_CAP_ASPM_OPT_COMPLIANCEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60396ASPM Optionality Compliance. This bit must be set to 1b in all functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b.Software is permitted to use the value of this bit to help determine whether to enable ASPM or whether to run ASPM compliance tests.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 22220x1RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60403Reserved for future use.23230x0RPCIE_CAP_PORT_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60419Port Number. This field indicates the PCI Express Port number for the given PCI Express Link.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.LINK_CONTROL_LINK_STATUS_REGLINK_CONTROL_LINK_STATUS_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr609720x10R/W0x10000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REGLink Control and Link Status Register.This register controls and provides information about PCI Express Link specific parameters.falsefalsefalsefalsePCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROLPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60470Active State Power Management (ASPM) Control.This field controls the level of ASPM enabled on the given PCI Express Link. See section 5.4.1.3 of PCI Express Base Specification for requirements on when and how to enable ASPM.Defined encodings are: - 00b: Disabled - 01b: L0s Entry Enabled - 10b: L1 Entry Enabled - 11b: L0s and L1 Entry EnabledNote: "L0s Entry Enabled" enables the Transmitter to enter L0s. If L0s is supported, the Receiver must be capable of entering L0s even when the Transmitter is disabled from entering L0s (00b or 10b).ASPM L1 must be enabled by software in the Upstream component on a Link prior to enabling ASPM L1 in the Downstream component on that Link. When disabling ASPM L1, software must disable ASPM L1 in the Downstream component on a Link prior to disabling ASPM L1 in the Upstream component on that Link. ASPM L1 must only be enabled on the Downstream component if both components on a Link support ASPM L1.For Multi-Function Devices (including ARI Devices), it is recommended that software program the same value for this field in all Functions. For non-ARI Multi-Function Devices, only capabilities enabled in all Functions are enabled for the component as a whole.For ARI Devices, ASPM Control is determined solely by the setting in Function0, regardless of Function 0's D-state. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component.Software must not enable L0s in either direction on a given Link unless components on both sides of the Link each support L0s; otherwise, the result is undefined.100x0R/WRSVDP_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60478Reserved for future use.220x0RPCIE_CAP_RCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60518Read Completion Boundary (RCB).Root Ports:Indicates the RCB value for the Root Port. Refer to section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB.Defined encodings are: - 0b: 64 byte - 1b: 128 byteThe controller hardwires this bit for a Root Port and returns its RCB support capabilities.Endpoints and Bridges:Optionally set by configuration software to indicate the RCB value of the Root Port Upstream from the Endpoint or Bridge. Refer to Section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB.Defined encodings are: - 0b 64 byte - 1b 128 byteConfiguration software must only set this bit if the Root Port Upstream from the Endpoint or Bridge reports an RCB value of 128 bytes (a value of 1b in the Read Completion Boundary bit).For functions that do not implement this feature, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WPCIE_CAP_LINK_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60548Link Disable.This bit disables the Link by directing the LTSSM to the Disabled state when set; this bit is Reserved on Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.Writes to this bit are immediately reflected in the value read from the bit, regardless of actual Link state.After clearing this bit, software must honor timing requirements defined in Section 6.6.1 with respect to the first Configuration Read following a Conventional Reset.In a DSP that supports crosslink, the controller gates the write value with the CROSS_LINK_EN field in PORT_LINK_CTRL_OFF.Note: The access attributes of this field are as follows: - Wire: CX_CROSSLINK_ENABLE=1 && PORT_LINK_CTRL_OFF.CROSS_LINK_EN=1||CX_CROSSLINK_ENABLE=0 && dsp=1 ? RW : RO - Dbi: CX_CROSSLINK_ENABLE=1 && PORT_LINK_CTRL_OFF.CROSS_LINK_EN=1||CX_CROSSLINK_ENABLE=0 && dsp=1? RW : RO 44R/WPCIE_CAP_RETRAIN_LINKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60579Retrain Link.A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration, re-entering Recovery is permitted but not required. If the Port is in DPC when a write of 1b to this bit occurs, the result is undefined. Reads of this bit always return 0b.It is permitted to write 1b to this bit while simultaneously writing modified values to other fields in this register. If the LTSSM is not already in Recovery or Configuration, the resulting Link training must use the modified values. If the LTSSM is already in Recovery or Configuration, the modified values are not required to affect the Link training that's already in progress.This bit is not applicable and is Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.This bit always returns 0b when read.Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description 55R/WPCIE_CAP_COMMON_CLK_CONFIGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60614Common Clock Configuration. When set, this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock.A value of 0b indicates that this component and the component at the opposite end of this Link are operating with asynchronous reference clock.For non-ARI Multi-Function Devices, software must program the same value for this bit in all Functions. If not all Functions are Set, then the component must as a whole assume that its reference clock is not common with the Upstream component.For ARI Devices, Common Clock Configuration is determined solely by the setting in Function 0. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component.Components utilize this common clock configuration information to report the correct L0s and L1 Exit Latencies.After changing the value in this bit in both components on a Link, software must trigger the Link to retrain by writing a 1b to the Retrain Link bit of the Downstream Port.660x0R/WPCIE_CAP_EXTENDED_SYNCHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60633Extended Synch. When set, this bit forces the transmission of additional Ordered Sets when exiting the L0s state (see section 4.2.4.5 of PCI Express Base Specification) and when in the Recovery state (see section 4.2.6.4.1 of PCI Express Base Specification). This mode provides external devices (for example, logic analyzers) monitoring the Link time to achieve bit and Symbol lock before the Link enters the L0 state and resumes communication.For Multi-Function devices if any function has this bit set, then the component must transmit the additional Ordered Sets when exiting L0s or when in Recovery.770x0R/WPCIE_CAP_EN_CLK_POWER_MANPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60678Enable Clock Power Management.Applicable only for Upstream Ports and with form factors that support a "Clock Request" (CLKREQ#) mechanism, this bit operates as follows: - 0b: Clock power management is disabled and device must hold CLKREQ# signal low. - 1b: When this bit is set, the device is permitted to use CLKREQ# signal to power manage Link clock according to protocol defined in appropriate form factor specification.For a non-ARI Multi-Function Device, power-management-configuration software must only Set this bit if all Functions of the Multi-Function Device indicate a 1b in the Clock Power Management bit of the Link Capabilities register. The component is permitted to use the CLKREQ# signal to power manage Link clock only if this bit is Set for all Functions.For ARI Devices, Clock Power Management is enabled solely by the setting in Function 0. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component.The CLKREQ# signal may also be controlled via the L1 PM Substates mechanism. Such control is not affected by the setting of this bit.For Downstream Ports and components that do not support Clock Power Management (as indicated by a 0b value in the Clock Power Management bit of the Link Capabilities register), the controller hardwires this bit to 0b.The write value is gated with the PCIE_CAP_CLOCK_POWER_MAN field in LINK_CAPABILITIES_REG.Note: The access attributes of this field are as follows: - Wire: LINK_CAPABILITIES_REG.PCIE_CAP_CLOCK_POWER_MAN ? RWS : ROS - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_CLOCK_POWER_MAN ? RWS : ROS Note: This register field is sticky.88R/WPCIE_CAP_HW_AUTO_WIDTH_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60701Hardware Autonomous Width Disable.When set, this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RW, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is of type RsvdP.For components that do not implement the ability autonomously to change Link width, the ciontroller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WPCIE_CAP_LINK_BW_MAN_INT_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60726Link Bandwidth Management Interrupt Enable. When set, this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO 1010R/WPCIE_CAP_LINK_AUTO_BW_INT_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60751Link Autonomous Bandwidth Management Interrupt Enable.When set, this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO 1111R/WRSVDP_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60759Reserved for future use.13120x0RPCIE_CAP_DRS_SIGNALING_CONTROLPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60794DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are: - 00b: DRS not ReportedIf DRS Supported is set, receiving a DRS Message will set DRS Message Received in the Link Status 2 Register but will otherwise have no effect - 01b: DRS Interrupt EnabledIf the DRS Message Received bit in the Link Status 2 Register transitions from 0 to 1, and either MSI or MSI-X is enabled, an MSI or MSI-X interrupt is generated using the vector in Interrupt Message Number (section 7.5.3.2) - 10b: DRS to FRS Signaling EnabledIf the DRS Message Received bit in the Link Status 2 Register transitions from 0 to 1, the Port must send an FRS Message Upstream with the FRS Reason field set to DRS Message Received.Behavior is undefined if this field is set to 10b and the FRS Supported bit in the Device Capabilities 2 Register is Clear.Behavior is undefined if this field is set to 11b.For Downstream Ports with the DRS Supported bit clear in the Link Capabilities 2 register, the controller hardwires this field to 00b.This field is Reserved for Upstream Ports.15140x0RPCIE_CAP_LINK_SPEEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60819Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link.The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the current Link speed.Defined encodings are: - 0001b: Supported Link Speeds Vector field bit 0 - 0010b: Supported Link Speeds Vector field bit 1 - 0011b: Supported Link Speeds Vector field bit 2 - 0100b: Supported Link Speeds Vector field bit 3 - 0101b: Supported Link Speeds Vector field bit 4 - 0110b: Supported Link Speeds Vector field bit 5 - 0111b: Supported Link Speeds Vector field bit 6All other encodings are Reserved.The value in this field is undefined when the Link is not up.1916RPCIE_CAP_NEGO_LINK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60839Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link.Defined encodings are: -00 0001b: x1 -00 0010b: x2 -00 0100b: x4 -00 1000b: x8 -00 1100b: x12 -01 0000b: x16 -10 0000b: x32All other encodings are Reserved. The value in this field is undefined when the Link is not up.2520RRSVDP_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60847Reserved for future use.26260x0RPCIE_CAP_LINK_TRAININGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60868Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state, or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when the LTSSM exits the Configuration/Recovery state.This bit is not applicable and Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches, and the controller hardwires it to 0b.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: R 2727RPCIE_CAP_SLOT_CLK_CONFIGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60888Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a reference clock on the connector, this bit must be clear.For a Multi-Function Device, each Function must report the same value for this bit.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 28280x1RPCIE_CAP_DLL_ACTIVEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60903Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state, 0b otherwise.This bit must be implemented if the Data Link Layer Link Active Reporting Capable bit is 1b. Otherwise, the controller hardwires it to 0b.29290x0RPCIE_CAP_LINK_BW_MAN_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60940Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: - A Link retraining has completed following a write of 1b to the Retrain Link bit.Note: This bit is set following any write of 1b to the Retrain Link bit, including when the Link is in the process of retraining for some other reason. - Hardware has changed Link speed or width to attempt to correct unreliable Link operation, either through an LTSSM timeout or a higher level process.This bit must be set if the Physical Layer reports a speed or width change was initiated by the Downstream component that was not indicated as an autonomous change.This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.The default value of this bit is 0b.The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: R 30300x0RPCIE_CAP_LINK_AUTO_BW_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr60971Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width, without the Port transitioning through DL_Down status, for reasons other than to attempt to correct unreliable Link operation.This bit must be set if the Physical Layer reports a speed or width change was initiated by the Downstream component that was indicated as an autonomous change.The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: R 31310x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES2_REGDEVICE_CAPABILITIES2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr612300x24R0x8001181fPE0_DWC_pcie_ctl_DBI_Slave_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REGDevice Capabilities 2 Register.falsefalsefalsefalsePCIE_CAP_CPL_TIMEOUT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61011Completion Timeout Ranges Supported. This field indicates device Function support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value.This field is applicable only to Root Ports, Endpoints that issue Requests on their own behalf, and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued on PCI Express. For all other Functions this field is Reserved and must be hardwired to 0000b.Four time value ranges are defined: - Range A: 50 us to 10 ms - Range B: 10 ms to 250 ms - Range C: 250 ms to 4 s - Range D: 4 s to 64 sBits are set according to the list below to show timeout value ranges supported. - 0000b Completion Timeout programming not supported – the Function must implement a timeout value in the range 50 μs to 50 ms. - 0001b Range A - 0010b Range B - 0011b Ranges A and B - 0110b Ranges B and C - 0111b Ranges A, B, and C - 1110b Ranges B, C, and D - 1111b Ranges A, B, C, and DAll other values are Reserved.It is strongly recommended that the Completion Timeout mechanism not expire in less than 10 ms.300xfRPCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61029Completion Timeout Disable Supported. A value of 1b indicates support for the Completion Timeout Disable mechanism.The Completion Timeout Disable mechanism is required for Endpoints that issue Requests on their own behalf and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued on PCI Express.This mechanism is optional for Root Ports.For all other Functions this field is Reserved and the controller hardwires this bit to 0b.440x1RPCIE_CAP_ARI_FORWARD_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61041ARI Forwarding Supported. Applicable only to Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability. For more details, see section 6.13 of PCI Express Base Specification.550x0RPCIE_CAP_ATOMIC_ROUTING_SUPPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61053AtomicOp Routing Supported. Applicable only to Switch Upstream Ports, Switch Downstream Ports, and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. For more details, see section 6.15 of PCI Express Base Specification.660x0RPCIE_CAP_32_ATOMIC_CPL_SUPPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6106632-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd, Swap, and CAS AtomicOps. This bit must be set to 1b if the Function supports this optional capability. For more details on additional RC requirements, see section 6.15.3.1 of PCI Express Base Specification.770x0RPCIE_CAP_64_ATOMIC_CPL_SUPPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6107964-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd, Swap, and CAS AtomicOps. This bit must be set to 1b if the Function supports this optional capability. For more details on additional RC requirements, see section 6.15.3.1 of PCI Express Base Specification.880x0RPCIE_CAP_128_CAS_CPL_SUPPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61090128-bit CAS Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. This bit must be set to 1b if the Function supports this optional capability. For more details, see section 6.15 of PCI Express Base Specification.990x0RPCIE_CAP_NO_RO_EN_PR2PR_PARPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61108No RO-enabled PR-PR Passing. If this bit is set, the routing element never carries out the passing permitted by Table 2-39 of PCI Express Base Specification entry A2b that is associated with the Relaxed Ordering Attribute field being Set.This bit applies only for Switches and RCs that support peer-to-peer traffic between Root Ports. This bit applies only to Posted Requests being forwarded through the Switch or RC and does not apply to traffic originating or terminating within the Switch or RC itself. All Ports on a Switch or RC must report the same value for this bit.For all other functions, this bit must be 0b.10100x0RPCIE_CAP_LTR_SUPPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61131LTR Mechanism Supported. A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism.Root Ports, Switches and Endpoints are permitted to implement this capability.For a Multi-Function Device associated with an Upstream Port, each Function must report the same value for this bit.For Bridges and other Functions that do not implement this capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(Sticky) else R(Sticky) Note: This register field is sticky.11110x1RPCIE_CAP_TPH_CMPLT_SUPPORT_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61150TPH Completer Supported Bit 0. Value of this bit along with TPH Completer Supported Bit 1 indicates Completer support for TPH or Extended TPH. Applicable only to Root Ports and Endpoints. For all other Functions, this field is Reserved.Defined Encodings are: - 00b: TPH and Extended TPH Completer not supported. - 01b: TPH Completer supported; Extended TPH Completer not supported. - 10b: Reserved. - 11b: Both TPH and Extended TPH Completer supported.For more details, see section 6.17 of PCI Express Base Specification.12120x1RPCIE_CAP_TPH_CMPLT_SUPPORT_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61157TPH Completer Supported Bit 1.13130x0RPCIE_CAP2_LN_SYS_CLSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61174LN System CLS. Applicable only to Root Ports and RCRBs; must be 00b for all other Function types. This field indicates if the Root Port or RCRB supports LN protocol as an LN Completer, and if so, what cacheline size is in effect.Encodings are: - 00b LN Completer either not supported or not in effect - 01b LN Completer with 64-byte cachelines in effect - 10b LN Completer with 128-byte cachelines in effect - 11b ReservedNote: This register field is sticky.15140x0RPCIE_CAP2_10_BIT_TAG_COMP_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6118410-Bit Tag Completer Supported. If this bit is set, the Function supports 10-Bit Tag Completer capability; otherwise, the Function does not. For more details, see section 2.2.6.2. of PCI Express Base Specification.16160x1RPCIE_CAP2_10_BIT_TAG_REQ_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr6120210-Bit Tag Requester Supported. If this bit is set, the Function supports 10-Bit Tag Requester capability; otherwise, the Function does not.This bit must not be set if the 10-Bit Tag Completer Supported bit is clear.Note: 10-Bit Tag field generation must be enabled by the 10-Bit Tag Requester Enable bit in the Device Control 2 register of the Requester Function before 10-Bit Tags can be generated by the Requester. For more details, see section 2.2.6.2. of PCI Express Base Specification.17170x0R--23180x0rRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61209Reserved for future use.30240x00RPCIE_CAP_FRS_SUPPORTEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61229FRS Supported. When set, indicates support for the optional Function Readiness Status (FRS) capability.Must be set for all Functions that support generation or reception capabilities of FRS Messages.Must not be set by Switch Functions that do not generate FRS Messages on their own behalf.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 31310x1RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL2_DEVICE_STATUS2_REGDEVICE_CONTROL2_DEVICE_STATUS2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr613600x28R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REGDevice Control 2 and Status 2 Register.falsefalsefalsefalsePCIE_CAP_CPL_TIMEOUT_VALUEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61288Completion Timeout Value. In device Functions that support Completion Timeout programmability, this field allows system software to modify the Completion Timeout value. This field is applicable to Root Ports, Endpoints that issue Requests on their own behalf, and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued on PCI Express. For all other Functions this field is Reserved and controller hardwires it to 0000b.A Function that does not support this optional capability must hardwire this field to 0000b and is required to implement a timeout value in the range 50 μs to 50 ms. Functions that support Completion Timeout programmability must support the values given below corresponding to the programmability ranges indicated in the Completion Timeout Ranges Supported field.Defined encodings: - 0000b Default range: 50 μs to 50 msIt is strongly recommended that the Completion Timeout mechanism not expire in less than 10 ms.Values available if Range A (50 μs to 10 ms) programmability range is supported: - 0001b: 50 μs to 100 μs - 0010b: 1 ms to 10 msValues available if Range B (10 ms to 250 ms) programmability range is supported: - 0101b 16 ms to 55 ms - 0110b 65 ms to 210 msValues available if Range C (250 ms to 4 s) programmability range is supported: - 1001b 260 ms to 900 ms - 1010b 1 s to 3.5 sValues available if the Range D (4 s to 64 s) programmability range is supported: - 1101b 4 s to 13 s - 1110b 17 s to 64 sValues not defined above are Reserved.Software is permitted to change the value in this field at any time. For Requests already pending when the Completion Timeout Value is changed, hardware is permitted to use either the new or the old value for the outstanding Requests, and is permitted to base the start time for each Request either on when this value was changed or on when each request was issued.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 300x0R/WPCIE_CAP_CPL_TIMEOUT_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61309Completion Timeout Disable. When set, this bit disables the Completion Timeout mechanism.This bit is required for all Functions that support the Completion Timeout Disable Capability. Functions that do not support this optional capability are permitted to hardwire this bit to 0bSoftware is permitted to set or clear this bit at any time. When set, the Completion Timeout detection mechanism is disabled. If there are outstanding Requests when the bit is cleared, it is permitted but not required for hardware to apply the completion timeout mechanism to the outstanding Requests. If this is done, it is permitted to base the start time for each Request on either the time this bit was cleared or the time each Request was issued.440x0R/WPCIE_CAP_ARI_FORWARD_SUPPORT_CSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61323ARI Forwarding Enable. When set, the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request, permitting access to Extended Functions in an ARI Device immediately below the Port. For more details, see Section 6.13 of PCI Express Base Specification.550x0R--960x0rPCIE_CAP_LTR_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61359LTR Mechanism Enable. When set to 1b, this bit enables Upstream Ports to send LTR messages and Downstream Ports to process LTR Messages.For a Multi-Function Device associated with an Upstream Port of a device that implements LTR, the bit in Function 0 is RW, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is RsvdP.Functions that do not implement the LTR mechanism are permitted to hardwire this bit to 0b.For Downstream Ports, this bit must be reset to the default value if the Port goes to DL_Down status.The write value is gated with the PCIE_CAP_LTR_SUPP field of DEVICE_CAPABILITIES2_REG.Note: RW for function #0 and RsdvP for all other functions.Note: The access attributes of this field are as follows: - Wire: if (pf=0 && DEVICE_CAPABILITIES2_REG.PCIE_CAP_LTR_SUPP) then R/W else R - Dbi: if (pf=0 && DEVICE_CAPABILITIES2_REG.PCIE_CAP_LTR_SUPP) then R/W else R 10100x0R/W--31110x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES2_REGLINK_CAPABILITIES2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr615260x2CR/W0x81800000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PCIE_CAP_LINK_CAPABILITIES2_REGLink Capabilities 2 Register.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61371Reserved for future use.000x0RPCIE_CAP_SUPPORT_LINK_SPEED_VECTORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61402Supported Link Speeds Vector. This field indicates the supported Link speed(s) of the associated Port. For each bit, a value of 1b indicates that the corresponding Link speed is supported; otherwise, the Link speed is not supported. For more details, see section 8.2.1 of PCI Express Base Specification.Bit definitions within this field are: - Bit 0 2.5 GT/s - Bit 1 5.0 GT/s - Bit 2 8.0 GT/s - Bit 3 16.0 GT/s - Bit 4 32.0 GT/s - Bits 6:5 RsvdPMulti-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.This field has a default of (PCIE_CAP_MAX_LINK_SPEED == 0101) ? 0011111 : (PCIE_CAP_MAX_LINK_SPEED == 0100) ? 0001111 : (PCIE_CAP_MAX_LINK_SPEED == 0011) ? 0000111 : (PCIE_CAP_MAX_LINK_SPEED == 0010) ? 0000011 : 0000001 where PCIE_CAP_MAX_LINK_SPEED is a field in the LINK_CAPABILITIES_REG register.71RPCIE_CAP_CROSS_LINK_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61431Crosslink Supported. When set to 1b, this bit indicates that the associated Port supports crosslinks (for more details, see section 4.2.6.3.1 of PCI Express Base Specification). When set to 0b on a Port that supports Link speeds of 8.0 GT/s or higher, this bit indicates that the associated Port does not support crosslinks. When set to 0b on a Port that only supports Link speeds of 2.5 GT/s or 5.0 GT/s, this bit provides no information regarding the Port’s level of crosslink support.It is recommended that this bit be Set in any Port that supports crosslinks even though doing so is only required for Ports that also support operating at 8.0 GT/s or higher Link speeds.Note: Software should use this bit when referencing fields whose definition depends on whether or not the Port supports crosslinks (for more details, see section 7.7.3.4 of PCI Express Base Specification).Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.880x0RRSVDP_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61439Reserved for future use.2290x0000RPCIE_CAP_RETIMER_PRE_DET_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61465Retimer Presence Detect Supported. When set to 1b, this bit indicates that the associated Port supports detection and reporting of Retimer presence.This bit must be set to 1b in a Port when the Supported Link Speeds Vector of the Link Capabilities 2 register indicates support for a Link speed of 16.0 GT/s or higher.It is permitted to be set to 1b regardless of the supported Link speeds.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 23230x1RPCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61491Two Retimers Presence Detect Supported. When set to 1b, this bit indicates that the associated Port supports detection and reporting of two Retimers presence.This bit must be set to 1b in a Port when the Supported Link Speeds Vector of the Link Capabilities 2 register indicates support for a Link speed of 16.0 GT/s or higher.It is permitted to be set to 1b regardless of the supported Link speeds if the Retimer Presence Detect Supported bit is also set to 1b.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 24240x1R/WRSVDP_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61499Reserved for future use.30250x00RDRS_SUPPORTEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61525DRS Supported. When set, indicates support for the optional Device Readiness Status (DRS) capability.Must be Set in Downstream Ports that support DRS.Must be Set in Downstream Ports that support FRS.For Upstream Ports that support DRS, it is strongly recommended that this bit be Set in Function 0. For all other Functions associated with an Upstream Port, this bit must be Clear.127Must be Clear in Functions that are not associated with a Port.RsvdP in all other Functions.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 31310x1RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.LINK_CONTROL2_LINK_STATUS2_REGLINK_CONTROL2_LINK_STATUS2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr620520x30R/W0x00010000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REGLink Control 2 and Status 2 Register.falsefalsefalsefalsePCIE_CAP_TARGET_LINK_SPEEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61590Target Link Speed. For Downstream Ports, this field sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences.The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the desired target Link speed.Defined encodings are: - 0001b: Supported Link Speeds Vector field bit 0 - 0010b: Supported Link Speeds Vector field bit 1 - 0011b: Supported Link Speeds Vector field bit 2 - 0100b: Supported Link Speeds Vector field bit 3 - 0101b: Supported Link Speeds Vector field bit 4 - 0110b: Supported Link Speeds Vector field bit 5 - 0111b: Supported Link Speeds Vector field bit 6All other encodings are Reserved.If a value is written to this field that does not correspond to a supported speed (as indicated by the Supported Link Speeds Vector), the result is undefined.If either of the Enter Compliance or Enter Modified Compliance bits are implemented, then this field must also be implemented.The default value of this field is the highest Link speed supported by the component (as reported in the Max Link Speed field of the Link Capabilities register) unless the corresponding platform/form factor requires a different default value.For both Upstream and Downstream Ports, this field is used to set the target compliance mode speed when software is using the Enter Compliance bit to force a Link into compliance mode.For Upstream Ports, if the Enter Compliance bit is Clear, this field is permitted to have no effect.For a Multi-Function Device associated with an Upstream Port, the field in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other Functions of that device, this field is of type RsvdP.Components that support only the 2.5 GT/s speed are permitted to hardwire this field to 0000b.For a description of this standard PCIe register field, see the PCI Express Base Specification. In M-PCIe mode, the contents of this field are derived from other registers.Note: This register field is sticky.30R/WPCIE_CAP_ENTER_COMPLIANCEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61623Enter Compliance. Software is permitted to force a Link to enter Compliance mode (at the speed indicated in the Target Link Speed field and the de-emphasis/preset level indicated by the Compliance Preset/De-emphasis field) by setting this bit to 1b in both components on a Link and then initiating a hot reset on the Link.Default value of this bit following Fundamental Reset is 0b.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other Functions of that device, this bit is of type RsvdP.Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.This bit is intended for debug, compliance testing purposes only. System firmware and software is allowed to modify this bit only during debug or compliance testing. In all other cases, the system must ensure that this bit is set to the default value.Note: This register field is sticky.440x0R/WPCIE_CAP_HW_AUTO_SPEED_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61648Hardware Autonomous Speed Disable. When set, this bit disables hardware from changing the Link speed for device-specific reasons other than attempting to correct unreliable Link operation by reducing Link speed. Initial transition to the highest supported common link speed is not blocked by this bit.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is of type RsvdP.Functions that do not implement the associated mechanism are permitted to hardwire this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.550x0R/WPCIE_CAP_SEL_DEEMPHASISPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61673Selectable De-emphasis. When the Link is operating at 5.0 GT/s speed, this bit is used to control the transmit de-emphasis of the link in specific situations. For more details, see section 4.2.6 of PCI Express Base Specification.Encodings: - 1b: -3.5 dB - 0b: -6 dBWhen the Link is not operating at 5.0 GT/s speed, the setting of this bit has no effect. Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.This bit is not applicable and Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.Note: This register field is sticky.660x0RPCIE_CAP_TX_MARGINPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61707Transmit Margin – This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate (see Chapter 4 of PCI Express Base Specification for details of how the Transmitter voltage level is determined in various states).Encodings: - 000b: Normal operating range - 001b-111b: As defined in Section 8.3.4 not all encodings are required to be implemented.For a Multi-Function Device associated with an Upstream Port, the field in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other Functions of that device, this field is of type RsvdP.For components that support only the 2.5 GT/s speed, the controller hardwires this bit to 000b.This field is intended for debug, compliance testing purposes only. System firmware and software is allowed to modify this field only during debug or compliance testing. In all other cases, the system must ensure that this field is set to the default value.Note: This register field is sticky.970x0R/WPCIE_CAP_ENTER_MODIFIED_COMPLIANCEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61734Enter Modified Compliance. When this bit is set to 1b, the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate.Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is of type RsvdP.This bit is intended for debug, compliance testing purposes only. System firmware and software is allowed to modify this bit only during debug or compliance testing. In all other cases, the system must ensure that this bit is set to the default value.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.10100x0R/WPCIE_CAP_COMPLIANCE_SOSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61761Compliance SOS. When set to 1b, the LTSSM is required to send SKP Ordered Sets between sequences when sending the Compliance Pattern or Modified Compliance Pattern.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other Functions of that device, this bit is of type RsvdP.This bit is applicable when the Link is operating at 2.5 GT/s or 5.0 GT/s data rates only.For components that support only the 2.5 GT/s speed, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.11110x0R/WPCIE_CAP_COMPLIANCE_PRESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61803Compliance Preset/De-emphasis.For 8.0 GT/s and higher Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The encodings are defined in section 4.2.3.2 of PCI Express Base Specification . Results are undefined if a reserved preset encoding is used when entering Polling.Compliance in this way.For 5.0 GT/s Data Rate: This field sets the de-emphasis level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b.Defined Encodings are: - 0001b: -3.5 dB - 0000b: -6 dBWhen the Link is operating at 2.5 GT/s, the setting of this field has no effect. Components that support only 2.5 GT/s speed are permitted to hardwire this field to 0000b.For a Multi-Function Device associated with an Upstream Port, the field in Function 0 is of type RWS, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this field is of type RsvdP.This field is intended for debug and compliance testing purposes. System firmware and software is allowed to modify this field only during debug or compliance testing. In all other cases, the system must ensure that this field is set to the default value.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.15120x0R/WPCIE_CAP_CURR_DEEMPHASISPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61829Current De-emphasis Level. When the Link is operating at 5.0 GT/s speed, this bit reflects the level of de-emphasis.Encodings: - 1b: -3.5 dB - 0b: -6 dBThe value in this bit is undefined when the Link is not operating at 5.0 GT/s speed.Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.For components that support speeds greater than 2.5 GT/s, Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions of the Port. In M-PCIe mode this register is always 0x0. In C-PCIe mode, its contents are derived by sampling the PIPE.16160x1RPCIE_CAP_EQ_CPLPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61851Equalization 8.0 GT/s Complete. When set to 1b, this bit indicates that the Transmitter Equalization procedure at the 8.0 GT/s data rate has completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.Note: This register field is sticky.17170x0RPCIE_CAP_EQ_CPL_P1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61873Equalization 8.0 GT/s Phase 1 Successful. When set to 1b, this bit indicates that Phase 1 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.Note: This register field is sticky.18180x0RPCIE_CAP_EQ_CPL_P2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61895Equalization 8.0 GT/s Phase 2 Successful. When set to 1b, this bit indicates that Phase 2 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.Note: This register field is sticky.19190x0RPCIE_CAP_EQ_CPL_P3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61917EEqualization 8.0 GT/s Phase 3 Successful. When set to 1b, this bit indicates that Phase 3 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.Note: This register field is sticky.20200x0RPCIE_CAP_LINK_EQ_REQPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61935Link Equalization Request 8.0 GT/s. This bit is set by hardware to request the 8.0 GT/s Link equalization process to be performed on the Link. For more details, see sections 4.2.3 and 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.21210x0R/W1CPCIE_CAP_RETIMER_PRE_DETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61961Retimer Presence Detected. When set to 1b, this bit indicates that a Retimer was present during the most recent Link negotiation. For more details, see section 4.2.6.3.5.1 of PCI Express Base Specification.This bit is required for Ports that have the Retimer Presence Detect Supported bit of the Link Capabilities 2 register set to 1b.For Ports that have the Retimer Presence Detect Supported bit set to 0b, the controller hardwires this bit to 0b.For Multi-Function Devices associated with an Upstream Port, this bit must be implemented in Function 0 and is RsvdZ in all other Functions.Note: This register field is sticky.22220x0RPCIE_CAP_TWO_RETIMERS_PRE_DETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61987Two Retimers Presence Detected. When set to 1b, this bit indicates that two Retimers were present during the most recent Link negotiation. For more details, see section 4.2.6.3.5.1 of PCI Express Base Specification.This bit is required for Ports that have the Two Retimers Presence Detect Supported bit of the Link Capabilities 2 register set to 1b.Ports that have the Two Retimers Presence Detect Supported bit set to 0b are permitted to hardwire this bit to 0b.For Multi-Function Devices associated with an Upstream Port, this bit must be implemented in Function 0 and RsvdZ in all other Functions.Note: This register field is sticky.23230x0R--25240x0rRSVDP_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_SETDWC_pcie_dbi_cpcie_usp_4x8.csr61995Reserved for future use.27260x0RDOWNSTREAM_COMPO_PRESENCEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62035Downstream Component Presence. This field indicates the presence and DRS status for the Downstream Component, if any, connected to the Link; defined values are: - 000b: Link Down – Presence Not Determined - 001b: Link Down – Component Not Present indicates the Downstream Port (DP) has determined that a Downstream Component is not present - 010b: Link Down – Component Present indicates the DP has determined that a Downstream Component is present, but the Data Link Layer is not active - 011b: Reserved - 100b: Link Up – Component Presentindicates the DP has determined that a Downstream Component is present, but no DRS Message has been received since the Data Link Layer became active - 101b: Link Up – Component Present and DRS Received indicates the DP has received a DRS Message since the Data Link Layer became active - 110b: Reserved - 111b: ReservedComponent Presence state must be determined by the logical "OR" of the Physical Layer in-band presence detect mechanism and, if present, any out-of-band presence detect mechanism implemented for the Link. If no out-of-band presence detect mechanism is implemented, then Component Presence state must be determined solely by the Physical Layer in-band presence detect mechanism.This field must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities 2 register.This field is RsvdZ for all other Functions.30280x0RDRS_MESSAGE_RECEIVEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62051DRS Message Received. This bit must be set whenever the Port receives a DRS Message.This bit must be cleared in DL_Down.This bit must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities 2 register.This bit is RsvdZ for all other Functions.31310x0RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAPPF0_MSIX_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr622550xB0R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_MSIX_CAPPF MSI-X Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP.PCI_MSIX_CAP_ID_NEXT_CTRL_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP.MSIX_TABLE_OFFSET_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP.MSIX_PBA_OFFSET_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP.PCI_MSIX_CAP_ID_NEXT_CTRL_REGPCI_MSIX_CAP_ID_NEXT_CTRL_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr621440x0R/W0x00800011PE0_DWC_pcie_ctl_DBI_Slave_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REGMSI-X Capability ID, Next Pointer, Control Registers.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCI_MSIX_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62072MSI-X Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x11RPCI_MSIX_CAP_NEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62088MSI-X Next Capability Pointer.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580x00RPCI_MSIX_TABLE_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62113MSI-X Table Size.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PCI_MSIX_TABLE_SIZE field in SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_TABLE_SIZE field in the PF PCI_MSIX_CAP_ID_NEXT_CTRL_REG register.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.26160x080RRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62121Reserved for future use.29270x0RPCI_MSIX_FUNCTION_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62134Function Mask.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30300x0R/WPCI_MSIX_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62143MSI-X Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP.MSIX_TABLE_OFFSET_REGMSIX_TABLE_OFFSET_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr621990x4R0x00000004PE0_DWC_pcie_ctl_DBI_Slave_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REGMSI-X Table Offset and BIR Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCI_MSIX_BIRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62174MSI-X Table BAR Indicator Register Field.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table BAR Indicator Register" (PCI_MSIX_BIR field in SHADOW_MSIX_TABLE_OFFSET_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_BIR field in the PF MSIX_TABLE_OFFSET_REG register.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.200x4RPCI_MSIX_TABLE_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62198MSI-X Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Offset" (PCI_MSIX_TABLE_OFFSET field in SHADOW_MSIX_TABLE_OFFSET_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_TABLE_OFFSET field in the PF MSIX_TABLE_OFFSET_REG register.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.3130x00000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP.MSIX_PBA_OFFSET_REGMSIX_PBA_OFFSET_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr622540x8R0x00008004PE0_DWC_pcie_ctl_DBI_Slave_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REGMSI-X PBA Offset and BIR Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCI_MSIX_PBA_BIRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62229MSI-X PBA BIR.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X PBA BIR" (PCI_MSIX_PBA_BIR field in SHADOW_MSIX_PBA_OFFSET_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_PBA_BIR field in the PF MSIX_PBA_OFFSET_REG register.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.200x4RPCI_MSIX_PBA_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62253MSI-X PBA Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X PBA Offset" (PCI_MSIX_PBA_OFFSET field in SHADOW_MSIX_PBA_OFFSET_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_PBA_OFFSET field in the PF MSIX_PBA_OFFSET_REG register.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.3130x00001000RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAPPF0_AER_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr636760x100R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAPPF Advanced Error Reporting Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.AER_EXT_CAP_HDR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.UNCORR_ERR_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.UNCORR_ERR_MASK_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.UNCORR_ERR_SEV_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.CORR_ERR_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.CORR_ERR_MASK_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.ADV_ERR_CAP_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.HDR_LOG_0_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.HDR_LOG_1_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.HDR_LOG_2_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.HDR_LOG_3_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_1_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_2_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_3_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_4_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.AER_EXT_CAP_HDR_OFFAER_EXT_CAP_HDR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr623140x0R0x14820001PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_AER_EXT_CAP_HDR_OFFAdvanced Error Reporting Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62281AER Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0001RCAP_VERSIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62297Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x2RNEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62313Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x148RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.UNCORR_ERR_STATUS_OFFUNCORR_ERR_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr624900x4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_UNCORR_ERR_STATUS_OFFUncorrectable Error Status Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62327Reserved for future use.300x0RDL_PROTOCOL_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62337Data Link Protocol Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.44R/W1CSURPRISE_DOWN_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62347Surprise Down Error Status (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.55R/W1CRSVDP_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62355Reserved for future use.1160x00RPOIS_TLP_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62366Poisoned TLP Status.For a description of this standard PCIe register field, see the PCI Express Specification.12120x0R/W1CFC_PROTOCOL_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62376Flow Control Protocol Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.1313R/W1CCMPLT_TIMEOUT_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62387Completion Timeout Status.For a description of this standard PCIe register field, see the PCI Express Specification.14140x0R/W1CCMPLT_ABORT_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62398Completer Abort Status.For a description of this standard PCIe register field, see the PCI Express Specification.15150x0R/W1CUNEXP_CMPLT_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62409Unexpected Completion Status.For a description of this standard PCIe register field, see the PCI Express Specification.16160x0R/W1CREC_OVERFLOW_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62419Receiver Overflow Status.For a description of this standard PCIe register field, see the PCI Express Specification.1717R/W1CMALF_TLP_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62429Malformed TLP Status.For a description of this standard PCIe register field, see the PCI Express Specification.1818R/W1CECRC_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62443ECRC Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.Note:If CX_ECRC_ENABLE=0 the register field always reads 0.19190x0R/W1CUNSUPPORTED_REQ_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62454Unsupported Request Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.20200x0R/W1C--21210x0rINTERNAL_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62473Uncorrectable Internal Error Status.For a description of this standard PCIe register field, see the PCI Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when it detects internal uncorrectable internal errors such as parity and ECC failures. You should use the outputs from these errors to drive the app_err_bus[9] input. For more details, see the "Data Integrity (Wire, Datapath, and RAM Protection)" section in the Databook.22220x0R/W1CRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62481Reserved for future use.23230x0R--26240x0rRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62489Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.UNCORR_ERR_MASK_OFFUNCORR_ERR_MASK_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr626990x8R/W0x00400000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_UNCORR_ERR_MASK_OFFUncorrectable Error Mask Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62503Reserved for future use.300x0RDL_PROTOCOL_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62514Data Link Protocol Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.440x0R/WSURPRISE_DOWN_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62526Surprise Down Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.550x0RRSVDP_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62534Reserved for future use.1160x00RPOIS_TLP_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62545Poisoned TLP Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.12120x0R/WFC_PROTOCOL_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62556Flow Control Protocol Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.13130x0R/WCMPLT_TIMEOUT_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62567Completion Timeout Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.14140x0R/WCMPLT_ABORT_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62578Completer Abort Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.15150x0R/WUNEXP_CMPLT_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62589Unexpected Completion Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.16160x0R/WREC_OVERFLOW_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62600Receiver Overflow Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.17170x0R/WMALF_TLP_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62611Malformed TLP Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.18180x0R/WECRC_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62625ECRC Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.19190x0R/WUNSUPPORTED_REQ_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62636Unsupported Request Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.20200x0R/WACS_VIOLATION_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62659ACS Violation Mask.Setting the ACS Violation Mask bit disables error logging and signaling for ACS Violation errors.The bit is Read-Only Zero for upstream ports, when ACS P2P Egress Control Enable is not set.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: if (acs_viol_svrity_mask_wr_en == 1) then R/W (Sticky) else R(Sticky) - Dbi: if (acs_viol_svrity_mask_wr_en == 1) then R/W (Sticky) else R(Sticky) Note: This register field is sticky.21210x0RINTERNAL_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62670Uncorrectable Internal Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.22220x1R/WRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62678Reserved for future use.23230x0RATOMIC_EGRESS_BLOCKED_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62690AtomicOp Egress Block Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.24240x0R--26250x0rRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62698Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.UNCORR_ERR_SEV_OFFUNCORR_ERR_SEV_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr628880xCR/W0x00462030PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_UNCORR_ERR_SEV_OFFUncorrectable Error Severity Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62712Reserved for future use.300x0RDL_PROTOCOL_ERR_SEVERITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62723Data Link Protocol Error Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.440x1R/WSURPRISE_DOWN_ERR_SVRITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62735Surprise Down Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.550x1RRSVDP_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62743Reserved for future use.1160x00RPOIS_TLP_ERR_SEVERITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62754Poisoned TLP Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.12120x0R/WFC_PROTOCOL_ERR_SEVERITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62765Flow Control Protocol Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.13130x1R/WCMPLT_TIMEOUT_ERR_SEVERITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62776Completion Timeout Error Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.14140x0R/WCMPLT_ABORT_ERR_SEVERITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62787Completer Abort Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.15150x0R/WUNEXP_CMPLT_ERR_SEVERITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62798Unexpected Completion Error Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.16160x0R/WREC_OVERFLOW_ERR_SEVERITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62809Receiver Overflow Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.17170x1R/WMALF_TLP_ERR_SEVERITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62820Malformed TLP Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.18180x1R/WECRC_ERR_SEVERITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62834ECRC Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.19190x0R/WUNSUPPORTED_REQ_ERR_SEVERITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62845Unsupported Request Error Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.20200x0R/W--21210x0rINTERNAL_ERR_SEVERITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62856Uncorrectable Internal Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.22220x1R/WRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62864Reserved for future use.23230x0RATOMIC_EGRESS_BLOCKED_ERR_SEVERITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62879AtomicOp Egress Blocked Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.24240x0R--26250x0rRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62887Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.CORR_ERR_STATUS_OFFCORR_ERR_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr630060x10R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_CORR_ERR_STATUS_OFFCorrectable Error Status Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRX_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62904Receiver Error Status (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.000x0R/W1CRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62912Reserved for future use.510x00RBAD_TLP_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62923Bad TLP Status.For a description of this standard PCIe register field, see the PCI Express Specification.660x0R/W1CBAD_DLLP_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62934Bad DLLP Status.For a description of this standard PCIe register field, see the PCI Express Specification.770x0R/W1CREPLAY_NO_ROLEOVER_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62945REPLAY_NUM Rollover Status.For a description of this standard PCIe register field, see the PCI Express Specification.880x0R/W1CRSVDP_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62953Reserved for future use.1190x0RRPL_TIMER_TIMEOUT_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62964Replay Timer Timeout Status.For a description of this standard PCIe register field, see the PCI Express Specification.12120x0R/W1CADVISORY_NON_FATAL_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62975Advisory Non-Fatal Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.13130x0R/W1CCORRECTED_INT_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62986Corrected Internal Error Status (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.14140x0R/W1CHEADER_LOG_OVERFLOW_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr62997Header Log Overflow Error Status (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.15150x0R/W1CRSVDP_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63005Reserved for future use.31160x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.CORR_ERR_MASK_OFFCORR_ERR_MASK_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr631240x14R/W0x0000e000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_CORR_ERR_MASK_OFFCorrectable Error Mask Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRX_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63022Receiver Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63030Reserved for future use.510x00RBAD_TLP_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63041Bad TLP Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.660x0R/WBAD_DLLP_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63052Bad DLLP Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.770x0R/WREPLAY_NO_ROLEOVER_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63063REPLAY_NUM Rollover Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63071Reserved for future use.1190x0RRPL_TIMER_TIMEOUT_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63082Replay Timer Timeout Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.12120x0R/WADVISORY_NON_FATAL_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63093Advisory Non-Fatal Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.13130x1R/WCORRECTED_INT_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63104Corrected Internal Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.14140x1R/WHEADER_LOG_OVERFLOW_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63115Header Log Overflow Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.15150x1R/WRSVDP_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63123Reserved for future use.31160x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.ADV_ERR_CAP_CTRL_OFFADV_ERR_CAP_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr632350x18R/W0x000000a0PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFFAdvanced Error Capabilities and Control Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseFIRST_ERR_POINTERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63143First Error Pointer.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.400x00RECRC_GEN_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63155ECRC Generation Capable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.550x1RECRC_GEN_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63166ECRC Generation Enable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.660x0R/WECRC_CHECK_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63178ECRC Check Capable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.770x1RECRC_CHECK_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63189ECRC Check Enable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.880x0R/WMULTIPLE_HEADER_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63201Multiple Header Recording Capable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.990x0RMULTIPLE_HEADER_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63216Multiple Header Recording Enable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.10100x0R--11110x0rCTO_PRFX_HDR_LOG_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63226TLP Prefix Log Present.For a description of this standard PCIe register field, see the PCI Express Specification.12120x0RRSVDP_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63234Reserved for future use.31130x00000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.HDR_LOG_0_OFFHDR_LOG_0_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr632940x1CR0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_HDR_LOG_0_OFFHeader Log Register 0.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseFIRST_DWORD_FIRST_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63254Byte 0 of Header log register of First 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RFIRST_DWORD_SECOND_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63267Byte 1 of Header log register of First 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RFIRST_DWORD_THIRD_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63280Byte 2 of Header log register of First 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RFIRST_DWORD_FOURTH_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63293Byte 3 of Header log register of First 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.HDR_LOG_1_OFFHDR_LOG_1_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr633530x20R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_HDR_LOG_1_OFFHeader Log Register 1.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseSECOND_DWORD_FIRST_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63313Byte 0 of Header log register of Second 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RSECOND_DWORD_SECOND_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63326Byte 1 of Header log register of Second 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RSECOND_DWORD_THIRD_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63339Byte 2 of Header log register of Second 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RSECOND_DWORD_FOURTH_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63352Byte 3 of Header log register of Second 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.HDR_LOG_2_OFFHDR_LOG_2_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr634120x24R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_HDR_LOG_2_OFFHeader Log Register 2.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseTHIRD_DWORD_FIRST_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63372Byte 0 of Header log register of Third 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RTHIRD_DWORD_SECOND_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63385Byte 1 of Header log register of Third 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RTHIRD_DWORD_THIRD_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63398Byte 2 of Header log register of Third 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RTHIRD_DWORD_FOURTH_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63411Byte 3 of Header log register of Third 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.HDR_LOG_3_OFFHDR_LOG_3_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr634710x28R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_HDR_LOG_3_OFFHeader Log Register 3.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseFOURTH_DWORD_FIRST_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63431Byte 0 of Header log register of Fourth 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RFOURTH_DWORD_SECOND_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63444Byte 1 of Header log register of Fourth 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RFOURTH_DWORD_THIRD_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63457Byte 2 of Header log register of Fourth 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RFOURTH_DWORD_FOURTH_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63470Byte 3 of Header log register of Fourth 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_1_OFFTLP_PREFIX_LOG_1_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr635220x38R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFFTLP Prefix Log Register 1.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCFG_TLP_PFX_LOG_1_FIRST_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63488Byte 0 of Error TLP Prefix Log 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RCFG_TLP_PFX_LOG_1_SECOND_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63499Byte 1 of Error TLP Prefix Log 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RCFG_TLP_PFX_LOG_1_THIRD_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63510Byte 2 of Error TLP Prefix Log 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RCFG_TLP_PFX_LOG_1_FOURTH_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63521Byte 3 of Error TLP Prefix Log 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_2_OFFTLP_PREFIX_LOG_2_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr635730x3CR0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFFTLP Prefix Log Register 2.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCFG_TLP_PFX_LOG_2_FIRST_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63539Byte 0 Error TLP Prefix Log 2.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RCFG_TLP_PFX_LOG_2_SECOND_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63550Byte 1 Error TLP Prefix Log 2.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RCFG_TLP_PFX_LOG_2_THIRD_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63561Byte 2 Error TLP Prefix Log 2.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RCFG_TLP_PFX_LOG_2_FOURTH_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63572Byte 3 Error TLP Prefix Log 2.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_3_OFFTLP_PREFIX_LOG_3_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr636240x40R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFFTLP Prefix Log Register 3.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCFG_TLP_PFX_LOG_3_FIRST_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63590Byte 0 Error TLP Prefix Log 3.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RCFG_TLP_PFX_LOG_3_SECOND_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63601Byte 1 Error TLP Prefix Log 3.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RCFG_TLP_PFX_LOG_3_THIRD_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63612Byte 2 Error TLP Prefix Log 3.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RCFG_TLP_PFX_LOG_3_FOURTH_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63623Byte 3 Error TLP Prefix Log 3.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_4_OFFTLP_PREFIX_LOG_4_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr636750x44R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFFTLP Prefix Log Register 4.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCFG_TLP_PFX_LOG_4_FIRST_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63641Byte 0 Error TLP Prefix Log 4.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RCFG_TLP_PFX_LOG_4_SECOND_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63652Byte 1 Error TLP Prefix Log 4.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RCFG_TLP_PFX_LOG_4_THIRD_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63663Byte 2 Error TLP Prefix Log 4.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RCFG_TLP_PFX_LOG_4_FOURTH_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63674Byte 3 Error TLP Prefix Log 4.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAPPF0_VC_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr646680x148R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAPVirtual Channel Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.VC_BASEregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.VC_STATUS_CONTROL_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.VC_BASEVC_BASEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr637350x0R0x19810002PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_VC_BASEVC Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PCIE_EXTENDED_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63702VC Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0002RVC_CAP_VERSIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63718Capability Version.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RVC_NEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63734Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x198RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_1VC_CAPABILITIES_REG_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr638050x4R0x00000003PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_VC_CAPABILITIES_REG_1Port VC Capability Register 1.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_EXT_VC_CNTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63750Extended VC Count.For a description of this standard PCIe register field, see the PCI Express Base Specification.200x3RRSVDP_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63757Reserved for future use.330x0RVC_LOW_PRI_EXT_VC_CNTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63772Low Priority Extended VC Count.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.640x0RRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63779Reserved for future use.770x0RVC_REFERENCE_CLOCKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63788Reference Clock.For a description of this standard PCIe register field, see the PCI Express Base Specification.980x0RVC_PORT_ARBI_TBL_ENTRY_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63797Port Arbitration Table Entry Size.For a description of this standard PCIe register field, see the PCI Express Base Specification.11100x0RRSVDP_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63804Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_2VC_CAPABILITIES_REG_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr638430x8R0x00000001PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_VC_CAPABILITIES_REG_2Port VC Capability Register 2.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_ARBI_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63826VC Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.300x1RRSVDP_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63833Reserved for future use.2340x00000RVC_ARBI_TABLE_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63842VC Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.VC_STATUS_CONTROL_REGVC_STATUS_CONTROL_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr638940xCR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_VC_STATUS_CONTROL_REGPort VC Control and Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_LOAD_VC_ARBI_TABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63858Requests Hardware to Load VC Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x0RVC_ARBI_SELECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63867VC Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.310x0R/WRSVDP_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63875Reserved for future use.1540x000RVC_ARBI_TABLE_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63885VC Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RRSVDP_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63893Reserved for future use.31170x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC0RESOURCE_CAP_REG_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr639590x10R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_RESOURCE_CAP_REG_VC0VC Resource Capability Register (0).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PORT_ARBI_CAP_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63909Port Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x00RRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63916Reserved for future use.1480x00RVC_REJECT_SNOOP_TRANS_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63929Reject Snoop Transactions.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 15150x0RVC_MAX_TIME_SLOT_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63942Maximum Time Slots-1 supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 21160x00RRSVDP_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63949Reserved for future use.23220x0RVC_PORT_ARBI_TABLE_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63958Port Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC0RESOURCE_CON_REG_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr640480x14R/W0x800000ffPE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_RESOURCE_CON_REG_VC0VC Resource Control Register (0).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_TC_MAP_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63974Bit 0 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x1RVC_TC_MAP_VC0_BIT1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63983Bits 7:1 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.710x7fR/WRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr63991Reserved for future use.1580x00RVC_LOAD_PORT_ARBI_TABLE_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64001Load Port Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0WVC_PORT_ARBI_SELECT_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64011Port Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.17170x0RRSVDP_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64019Reserved for future use.23180x00RVC_ID_VCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64029VC ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.26240x0RRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64037Reserved for future use.30270x0RVC_ENABLE_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64047VC Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x1RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC0RESOURCE_STATUS_REG_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr640880x18R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0VC Resource Status Register (0).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64061Reserved for future use.1500x0000RVC_PORT_ARBI_TABLE_STATUS_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64070Port Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RVC_NEGO_PENDING_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64080VC Negotiation Pending.For a description of this standard PCIe register field, see the PCI Express Base Specification.1717RRSVDP_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64087Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC1RESOURCE_CAP_REG_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr641530x1CR0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_RESOURCE_CAP_REG_VC1VC Resource Capability Register (1).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PORT_ARBI_CAP_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64103VC1 Port Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x00RRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64110Reserved for future use.1480x00RVC_REJECT_SNOOP_TRANS_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64123VC1 Reject Snoop Transactions.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 15150x0RVC_MAX_TIME_SLOT_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64136VC1 Maximum Time Slots-1 supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 21160x00RRSVDP_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64143Reserved for future use.23220x0RVC_PORT_ARBI_TABLE_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64152VC1 Port Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC1RESOURCE_CON_REG_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr642410x20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_RESOURCE_CON_REG_VC1VC Resource Control Register (1).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_TC_MAP_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64168VC1 Bit 0 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x0RVC_TC_MAP_VC1_BIT1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64177VC1 Bits 7:1 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.710x00R/WRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64185Reserved for future use.1580x00RVC_LOAD_PORT_ARBI_TABLE_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64195VC1 Load Port Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0WVC_PORT_ARBI_SELECT_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64205VC1 Port Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.19170x0RRSVDP_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64213Reserved for future use.23200x0RVC_ID_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64223VC1 VC ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.26240x0R/WRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64231Reserved for future use.30270x0RVC_ENABLE_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64240VC1 VC Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC1RESOURCE_STATUS_REG_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr642810x24R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1VC Resource Status Register (1).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64254Reserved for future use.1500x0000RVC_PORT_ARBI_TABLE_STATUS_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64263VC1 Port Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RVC_NEGO_PENDING_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64273VC1 VC Negotiation Pending.For a description of this standard PCIe register field, see the PCI Express Base Specification.1717RRSVDP_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64280Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC2RESOURCE_CAP_REG_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr643460x28R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_RESOURCE_CAP_REG_VC2VC Resource Capability Register (2).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PORT_ARBI_CAP_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64296VC2 Port Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x00RRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64303Reserved for future use.1480x00RVC_REJECT_SNOOP_TRANS_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64316VC2 Reject Snoop Transactions.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 15150x0RVC_MAX_TIME_SLOT_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64329VC2 Maximum Time Slots-1 supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 21160x00RRSVDP_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64336Reserved for future use.23220x0RVC_PORT_ARBI_TABLE_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64345VC2 Port Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC2RESOURCE_CON_REG_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr644340x2CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_RESOURCE_CON_REG_VC2VC Resource Control Register (2).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_TC_MAP_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64361VC2 Bit 0 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x0RVC_TC_MAP_VC2_BIT1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64370VC2 Bits 7:1 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.710x00R/WRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64378Reserved for future use.1580x00RVC_LOAD_PORT_ARBI_TABLE_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64388VC2 Load Port Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0WVC_PORT_ARBI_SELECT_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64398VC2 Port Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.19170x0RRSVDP_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64406Reserved for future use.23200x0RVC_ID_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64416VC2 VC ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.26240x0R/WRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64424Reserved for future use.30270x0RVC_ENABLE_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64433VC2 VC Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC2RESOURCE_STATUS_REG_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr644740x30R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2VC Resource Status Register (2).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64447Reserved for future use.1500x0000RVC_PORT_ARBI_TABLE_STATUS_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64456VC2 Port Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RVC_NEGO_PENDING_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64466VC2 VC Negotiation Pending.For a description of this standard PCIe register field, see the PCI Express Base Specification.1717RRSVDP_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64473Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC3RESOURCE_CAP_REG_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr645390x34R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_RESOURCE_CAP_REG_VC3VC Resource Capability Register (3).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PORT_ARBI_CAP_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64489VC3 Port Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x00RRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64496Reserved for future use.1480x00RVC_REJECT_SNOOP_TRANS_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64509VC3 Reject Snoop Transactions.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 15150x0RVC_MAX_TIME_SLOT_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64522VC3 Maximum Time Slots-1 supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 21160x00RRSVDP_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64529Reserved for future use.23220x0RVC_PORT_ARBI_TABLE_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64538VC3 Port Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC3RESOURCE_CON_REG_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr646270x38R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_RESOURCE_CON_REG_VC3VC Resource Control Register (3).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_TC_MAP_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64554VC3 Bit 0 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x0RVC_TC_MAP_VC3_BIT1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64563VC3 Bits 7:1 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.710x00R/WRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64571Reserved for future use.1580x00RVC_LOAD_PORT_ARBI_TABLE_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64581VC3 Load Port Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0WVC_PORT_ARBI_SELECT_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64591VC3 Port Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.19170x0RRSVDP_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64599Reserved for future use.23200x0RVC_ID_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64609VC3 VC ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.26240x0R/WRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64617Reserved for future use.30270x0RVC_ENABLE_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64626VC3 VC Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC3RESOURCE_STATUS_REG_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr646670x3CR0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3VC Resource Status Register (3).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64640Reserved for future use.1500x0000RVC_PORT_ARBI_TABLE_STATUS_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64649VC3 Port Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RVC_NEGO_PENDING_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64659VC3 VC Negotiation Pending.For a description of this standard PCIe register field, see the PCI Express Base Specification.1717RRSVDP_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64666Reserved for future use.31180x0000RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAPPF0_SPCIE_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr653650x198R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_SPCIE_CAPSecondary PCI Express Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_HEADER_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.LINK_CONTROL3_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.LANE_ERR_STATUS_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_0CH_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_10H_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_14H_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_18H_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_HEADER_REGSPCIE_CAP_HEADER_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr647270x0R0x1b810019PE0_DWC_pcie_ctl_DBI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REGSPCIE Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseEXTENDED_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64694Secondary PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0019RCAP_VERSIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64710Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64726Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x1b8RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.LINK_CONTROL3_REGLINK_CONTROL3_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr647680x4R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_SPCIE_CAP_LINK_CONTROL3_REGLink Control 3 Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalsePERFORM_EQPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64747Perform Equalization.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: RSVDP 00REQ_REQ_INT_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64760Link Equalization Request Interrupt Enable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: RSVDP 110x0RRSVDP_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64767Reserved for future use.3120x00000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.LANE_ERR_STATUS_REGLANE_ERR_STATUS_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr647930x8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_SPCIE_CAP_LANE_ERR_STATUS_REGLane Error Status Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseLANE_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64784Lane Error Status Bits per Lane.For a description of this standard PCIe register field, see the PCI Express Specification.700x00R/W1CRSVDP_LANE_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64792Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_0CH_REGSPCIE_CAP_OFF_0CH_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr649320xCR0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REGLane Equalization Control Register for lanes 1 and 0.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseDSP_TX_PRESET0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64809Downstream Port 8.0 GT/s Transmitter Preset 0.For a description of this standard PCIe register field, see the PCI Express Specification.300x0RDSP_RX_PRESET_HINT0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64819Downstream Port 8.0 GT/s Receiver Preset Hint 0.For a description of this standard PCIe register field, see the PCI Express Specification.640x0RRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64826Reserved for future use.770x0RUSP_TX_PRESET0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64842Upstream Port 8.0 GT/s Transmitter Preset 0.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.118RUSP_RX_PRESET_HINT0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64858Upstream Port 8.0 GT/s Receiver Preset Hint 0.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1412RRSVDP_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64865Reserved for future use.15150x0RDSP_TX_PRESET1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64875Downstream Port 8.0 GT/s Transmitter Preset 1.For a description of this standard PCIe register field, see the PCI Express Specification.19160x0RDSP_RX_PRESET_HINT1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64885Downstream Port 8.0 GT/s Receiver Preset Hint 1.For a description of this standard PCIe register field, see the PCI Express Specification.22200x0RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64892Reserved for future use.23230x0RUSP_TX_PRESET1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64908Upstream Port 8.0 GT/s Transmitter Preset 1.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.2724RUSP_RX_PRESET_HINT1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64924Upstream Port 8.0 GT/s Receiver Preset Hint 1.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.3028RRSVDP_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64931Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_10H_REGSPCIE_CAP_OFF_10H_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr650760x10R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REGLane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #2.The function of this register is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_NL. - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseDSP_TX_PRESET2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64953Downstream Port 8.0 GT/s Transmitter Preset2.For a description of this standard PCIe register, see the PCI Express Specification.300x0RDSP_RX_PRESET_HINT2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64963Downstream Port 8.0 GT/s Receiver Preset Hint2.For a description of this standard PCIe register, see the PCI Express Specification.640x0RRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64970Reserved for future use.770x0RUSP_TX_PRESET2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr64986Upstream Port 8.0 GT/s Transmitter Preset2.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.118RUSP_RX_PRESET_HINT2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65002Upstream Port 8.0 GT/s Receiver Preset Hint2.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.1412RRSVDP_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65009Reserved for future use.15150x0RDSP_TX_PRESET3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65019Downstream Port 8.0 GT/s Transmitter Preset3.For a description of this standard PCIe register, see the PCI Express Specification.19160x0RDSP_RX_PRESET_HINT3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65029Downstream Port 8.0 GT/s Receiver Preset Hint3.For a description of this standard PCIe register, see the PCI Express Specification.22200x0RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65036Reserved for future use.23230x0RUSP_TX_PRESET3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65052Upstream Port 8.0 GT/s Transmitter Preset3.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.2724RUSP_RX_PRESET_HINT3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65068Upstream Port 8.0 GT/s Receiver Preset Hint3.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.3028RRSVDP_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65075Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_14H_REGSPCIE_CAP_OFF_14H_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr652200x14R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REGLane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #4.The function of this register is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_NL. - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseDSP_TX_PRESET4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65097Downstream Port 8.0 GT/s Transmitter Preset4.For a description of this standard PCIe register, see the PCI Express Specification.300x0RDSP_RX_PRESET_HINT4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65107Downstream Port 8.0 GT/s Receiver Preset Hint4.For a description of this standard PCIe register, see the PCI Express Specification.640x0RRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65114Reserved for future use.770x0RUSP_TX_PRESET4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65130Upstream Port 8.0 GT/s Transmitter Preset4.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.118RUSP_RX_PRESET_HINT4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65146Upstream Port 8.0 GT/s Receiver Preset Hint4.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.1412RRSVDP_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65153Reserved for future use.15150x0RDSP_TX_PRESET5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65163Downstream Port 8.0 GT/s Transmitter Preset5.For a description of this standard PCIe register, see the PCI Express Specification.19160x0RDSP_RX_PRESET_HINT5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65173Downstream Port 8.0 GT/s Receiver Preset Hint5.For a description of this standard PCIe register, see the PCI Express Specification.22200x0RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65180Reserved for future use.23230x0RUSP_TX_PRESET5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65196Upstream Port 8.0 GT/s Transmitter Preset5.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.2724RUSP_RX_PRESET_HINT5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65212Upstream Port 8.0 GT/s Receiver Preset Hint5.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.3028RRSVDP_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65219Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_18H_REGSPCIE_CAP_OFF_18H_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr653640x18R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REGLane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #6.The function of this register is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_NL. - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseDSP_TX_PRESET6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65241Downstream Port 8.0 GT/s Transmitter Preset6.For a description of this standard PCIe register, see the PCI Express Specification.300x0RDSP_RX_PRESET_HINT6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65251Downstream Port 8.0 GT/s Receiver Preset Hint6.For a description of this standard PCIe register, see the PCI Express Specification.640x0RRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65258Reserved for future use.770x0RUSP_TX_PRESET6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65274Upstream Port 8.0 GT/s Transmitter Preset6.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.118RUSP_RX_PRESET_HINT6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65290Upstream Port 8.0 GT/s Receiver Preset Hint6.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.1412RRSVDP_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65297Reserved for future use.15150x0RDSP_TX_PRESET7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65307Downstream Port 8.0 GT/s Transmitter Preset7.For a description of this standard PCIe register, see the PCI Express Specification.19160x0RDSP_RX_PRESET_HINT7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65317Downstream Port 8.0 GT/s Receiver Preset Hint7.For a description of this standard PCIe register, see the PCI Express Specification.22200x0RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65324Reserved for future use.23230x0RUSP_TX_PRESET7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65340Upstream Port 8.0 GT/s Transmitter Preset7.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.2724RUSP_RX_PRESET_HINT7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65356Upstream Port 8.0 GT/s Receiver Preset Hint7.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.3028RRSVDP_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65363Reserved for future use.31310x0RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAPPF0_PL16G_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr657840x1B8R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_PL16G_CAPPhysical Layer 16.0 GT/s Extended Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_EXT_CAP_HDR_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_CAPABILITY_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_CONTROL_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_STATUS_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_LC_DPAR_STATUS_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_FIRST_RETIMER_DPAR_STATUS_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_SECOND_RETIMER_DPAR_STATUS_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_20H_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_24H_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_EXT_CAP_HDR_REGPL16G_EXT_CAP_HDR_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr654240x0R0x1e010026PE0_DWC_pcie_ctl_DBI_Slave_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REGPhysical Layer 16.0 GT/s Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseEXTENDED_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65391PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0026RCAP_VERSIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65407Capability Version.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65423Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x1e0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_CAPABILITY_REGPL16G_CAPABILITY_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr654380x4R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PL16G_CAP_PL16G_CAPABILITY_REG16.0 GT/s Capabilities Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65437Reserved for future use.3100x00000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_CONTROL_REGPL16G_CONTROL_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr654520x8R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PL16G_CAP_PL16G_CONTROL_REG16.0 GT/s Control Register .For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65451Reserved for future use.3100x00000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_STATUS_REGPL16G_STATUS_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr655330xCR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PL16G_CAP_PL16G_STATUS_REG16.0 GT/s Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseEQ_16G_CPLPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65471Equalization 16.0GT/s Complete.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: This register field is sticky.000x0REQ_16G_CPL_P1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65485Equalization 16.0GT/s Phase 1 Successful.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: This register field is sticky.110x0REQ_16G_CPL_P2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65499Equalization 16.0GT/s Phase 2 Successful.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: This register field is sticky.220x0REQ_16G_CPL_P3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65513Equalization 16.0GT/s Phase 3 Successful.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: This register field is sticky.330x0RLINK_EQ_16G_REQPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65524Link Equalization Request 16.0GT/s.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.440x0R/W1CRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65532Reserved for future use.3150x0000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_LC_DPAR_STATUS_REGPL16G_LC_DPAR_STATUS_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr655580x10R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG16.0 GT/s Local Data Parity Mismatch Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseLC_DPAR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65549Local Data Parity Mismatch Status.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.700x00R/W1CRSVDP_LC_DPAR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65557Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_FIRST_RETIMER_DPAR_STATUS_REGPL16G_FIRST_RETIMER_DPAR_STATUS_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr655830x14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG16.0 GT/s First Retimer Data Parity Mismatch Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseFIRST_RETIMER_DPAR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65574First Retimer Data Parity Mismatch Status.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.700x00R/W1CRSVDP_FIRST_RETIMER_DPAR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65582Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_SECOND_RETIMER_DPAR_STATUS_REGPL16G_SECOND_RETIMER_DPAR_STATUS_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr656090x18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG16.0 GT/s Second Retimer Data Parity Mismatch Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseSECOND_RETIMER_DPAR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65600Second Retimer Data Parity Mismatch Status .For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.700x00R/W1CRSVDP_SECOND_RETIMER_DPAR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65608Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_20H_REGPL16G_CAP_OFF_20H_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr656960x20R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG16.0 GT/s Lane Equalization Control Register for Lane 0-3.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseDSP_16G_TX_PRESET0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65625Downstream Port 16.0 GT/s Transmitter Preset0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.300x0RUSP_16G_TX_PRESET0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65635Upstream Port 16.0 GT/s Transmitter Preset0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.740x0RDSP_16G_TX_PRESET1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65645Downstream Port 16.0 GT/s Transmitter Preset1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1180x0RUSP_16G_TX_PRESET1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65655Upstream Port 16.0 GT/s Transmitter Preset1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.15120x0RDSP_16G_TX_PRESET2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65665Downstream Port 16.0 GT/s Transmitter Preset2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.19160x0RUSP_16G_TX_PRESET2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65675Upstream Port 16.0 GT/s Transmitter Preset2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.23200x0RDSP_16G_TX_PRESET3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65685Downstream Port 16.0 GT/s Transmitter Preset3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.27240x0RUSP_16G_TX_PRESET3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65695Upstream Port 16.0 GT/s Transmitter Preset3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31280x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_24H_REGPL16G_CAP_OFF_24H_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr657830x24R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG16.0 GT/s Lane Equalization Control Register for Lane 4-7.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseDSP_16G_TX_PRESET4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65712Downstream Port 16.0 GT/s Transmitter Preset4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.300x0RUSP_16G_TX_PRESET4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65722Upstream Port 16.0 GT/s Transmitter Preset4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.740x0RDSP_16G_TX_PRESET5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65732Downstream Port 16.0 GT/s Transmitter Preset5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1180x0RUSP_16G_TX_PRESET5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65742Upstream Port 16.0 GT/s Transmitter Preset5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.15120x0RDSP_16G_TX_PRESET6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65752Downstream Port 16.0 GT/s Transmitter Preset6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.19160x0RUSP_16G_TX_PRESET6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65762Upstream Port 16.0 GT/s Transmitter Preset6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.23200x0RDSP_16G_TX_PRESET7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65772Downstream Port 16.0 GT/s Transmitter Preset7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.27240x0RUSP_16G_TX_PRESET7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65782Upstream Port 16.0 GT/s Transmitter Preset7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31280x0RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAPPF0_MARGIN_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr667730x1E0R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_MARGIN_CAPMargining Extended Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_EXT_CAP_HDR_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_PORT_CAPABILITIES_STATUS_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS0_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS1_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS3_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS4_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS5_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS6_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS7_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_EXT_CAP_HDR_REGMARGIN_EXT_CAP_HDR_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr658430x0R0x20810027PE0_DWC_pcie_ctl_DBI_Slave_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REGMargining Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseEXTENDED_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65810PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0027RCAP_VERSIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65826Capability Version.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65842Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x208RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_PORT_CAPABILITIES_STATUS_REGMARGIN_PORT_CAPABILITIES_STATUS_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr659000x4R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REGMargining Port Capabilities and Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseMARGINING_USES_DRIVER_SOFTWAREPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65865Margining uses Driver Software.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.000x0RRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65872Reserved for future use.1510x0000RMARGINING_READYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65882Margining Ready.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.1616RMARGINING_SOFTWARE_READYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65892Margining Software Ready.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.1717RRSVDP_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65899Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS0_REGMARGIN_LANE_CNTRL_STATUS0_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr660090x8R/W0x00009c38PE0_DWC_pcie_ctl_DBI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REGMargining Lane Control and Status Register for Lane 0.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65914Receiver Number for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65924Margin Type for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65934Usage Model for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65942Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65952Margin Payload for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65964Receiver Number(Status) for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65976Margin Type(Status) for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65988Usage Model(Status) for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr65996Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66008Margin Payload(Status) for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS1_REGMARGIN_LANE_CNTRL_STATUS1_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr661180xCR/W0x00009c38PE0_DWC_pcie_ctl_DBI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REGMargining Lane Control and Status Register for Lane 1.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66023Receiver Number for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66033Margin Type for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66043Usage Model for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66051Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66061Margin Payload for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66073Receiver Number(Status) for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66085Margin Type(Status) for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66097Usage Model(Status) for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66105Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66117Margin Payload(Status) for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS2_REGMARGIN_LANE_CNTRL_STATUS2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr662270x10R/W0x00009c38PE0_DWC_pcie_ctl_DBI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REGMargining Lane Control and Status Register for Lane 2.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66132Receiver Number for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66142Margin Type for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66152Usage Model for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66160Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66170Margin Payload for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66182Receiver Number(Status) for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66194Margin Type(Status) for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66206Usage Model(Status) for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66214Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66226Margin Payload(Status) for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS3_REGMARGIN_LANE_CNTRL_STATUS3_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr663360x14R/W0x00009c38PE0_DWC_pcie_ctl_DBI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REGMargining Lane Control and Status Register for Lane 3.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66241Receiver Number for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66251Margin Type for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66261Usage Model for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66269Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66279Margin Payload for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66291Receiver Number(Status) for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66303Margin Type(Status) for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66315Usage Model(Status) for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66323Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66335Margin Payload(Status) for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS4_REGMARGIN_LANE_CNTRL_STATUS4_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr664450x18R/W0x00009c38PE0_DWC_pcie_ctl_DBI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REGMargining Lane Control and Status Register for Lane 4.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66350Receiver Number for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66360Margin Type for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66370Usage Model for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66378Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66388Margin Payload for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66400Receiver Number(Status) for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66412Margin Type(Status) for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66424Usage Model(Status) for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66432Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66444Margin Payload(Status) for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS5_REGMARGIN_LANE_CNTRL_STATUS5_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr665540x1CR/W0x00009c38PE0_DWC_pcie_ctl_DBI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REGMargining Lane Control and Status Register for Lane 5.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66459Receiver Number for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66469Margin Type for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66479Usage Model for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66487Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66497Margin Payload for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66509Receiver Number(Status) for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66521Margin Type(Status) for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66533Usage Model(Status) for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66541Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66553Margin Payload(Status) for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS6_REGMARGIN_LANE_CNTRL_STATUS6_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr666630x20R/W0x00009c38PE0_DWC_pcie_ctl_DBI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REGMargining Lane Control and Status Register for Lane 6.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66568Receiver Number for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66578Margin Type for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66588Usage Model for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66596Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66606Margin Payload for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66618Receiver Number(Status) for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66630Margin Type(Status) for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66642Usage Model(Status) for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66650Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66662Margin Payload(Status) for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS7_REGMARGIN_LANE_CNTRL_STATUS7_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr667720x24R/W0x00009c38PE0_DWC_pcie_ctl_DBI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REGMargining Lane Control and Status Register for Lane 7.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66677Receiver Number for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66687Margin Type for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66697Usage Model for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66705Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66715Margin Payload for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66727Receiver Number(Status) for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66739Margin Type(Status) for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66751Usage Model(Status) for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66759Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66771Margin Payload(Status) for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAPPF0_TPH_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr670560x208R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_TPH_CAPPF TLP Processing Hints Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP.TPH_EXT_CAP_HDR_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP.TPH_REQ_CAP_REG_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP.TPH_REQ_CONTROL_REG_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP.TPH_ST_TABLE_REG_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP.TPH_EXT_CAP_HDR_REGTPH_EXT_CAP_HDR_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr668320x0R0x29410017PE0_DWC_pcie_ctl_DBI_Slave_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REGTPH Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCIE_EXT_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66799TPH Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0017RTPH_REQ_CAP_VERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66815Capability Version.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RTPH_REQ_NEXT_PTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66831Next Capability Pointer.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x294RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP.TPH_REQ_CAP_REG_REGTPH_REQ_CAP_REG_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr669710x4R0x00000001PE0_DWC_pcie_ctl_DBI_Slave_PF0_TPH_CAP_TPH_REQ_CAP_REG_REGTPH Requestor Capability Register.For a description of this standard PCIe register, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same values for VF_TPH_REQ_CAP_REG_REG. To write this common register, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PF TPH_REQ_CAP_REG_REG register.falsefalsefalsefalseTPH_REQ_NO_ST_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66854No ST Mode Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x1RTPH_REQ_CAP_INT_VECPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66870Interrupt Vector Mode Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.110x0RTPH_REQ_DEVICE_SPECPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66886Device Specific Mode Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.220x0RRSVDP_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66893Reserved for future use.730x00RTPH_REQ_EXTENDED_TPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66909Extended TPH Requester Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.880x0RTPH_REQ_CAP_ST_TABLE_LOC_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66925ST Table Location Bit 0.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.990x0RTPH_REQ_CAP_ST_TABLE_LOC_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66941ST Table Location Bit 1.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.10100x0RRSVDP_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66948Reserved for future use.15110x00RTPH_REQ_CAP_ST_TABLE_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66963ST Table Size.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.26160x000RRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66970Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP.TPH_REQ_CONTROL_REG_REGTPH_REQ_CONTROL_REG_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr670160x8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REGTPH Requestor Control Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseTPH_REQ_ST_MODE_SELECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66990ST Mode Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 200x0RRSVDP_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr66998Reserved for future use.730x00RTPH_REQ_CTRL_REQ_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67007TPH Requester Enable Bit.For a description of this standard PCIe register field, see the PCI Express Base Specification.980x0R/WRSVDP_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67015Reserved for future use.31100x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP.TPH_ST_TABLE_REG_0TPH_ST_TABLE_REG_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr670550xCR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_TPH_CAP_TPH_ST_TABLE_REG_0TPH ST Table Register 0.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseTPH_REQ_ST_TABLE_LOWER_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67037ST Table 0 Lower Byte.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: this field is RW or Tie to 0 by table size configure - Dbi: this field is RW or Tie to 0 by table size configure 700x00R/WTPH_REQ_ST_TABLE_HIGHER_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67054ST Table 0 Upper Byte.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: this field is RW or Tie to 0 by table size configure - Dbi: this field is RW or Tie to 0 by table size configure 1580x00R--31160x0rgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_LTR_CAPPF0_LTR_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr672080x294R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_LTR_CAPPF Latency Tolerance Reporting Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_LTR_CAP.LTR_CAP_HDR_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_LTR_CAP.LTR_LATENCY_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_LTR_CAP.LTR_CAP_HDR_REGLTR_CAP_HDR_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr67122This register provides capbility ID, capability version and next offset value for LTR(Latency Tolerance Reporting).0x0R0x29c10018PE0_DWC_pcie_ctl_DBI_Slave_PF0_LTR_CAP_LTR_CAP_HDR_REGLTR Extended Capability Header.This register provides capbility ID, capability version and next offset value for LTR(Latency Tolerance Reporting).falsefalsefalsefalseCAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67087LTR Extended Capacity ID.This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability.PCI Express Extended Capability for the LTR Extended Capability is 0018h.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0018RCAP_VERSIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67104Capability Version.This field is a PCI-SIG defined version number that indicates the version of the Capability structure present.This field is depends on version of the specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67121Next Capability Offset.This field contains the offset to the next PCI Express Extended Capability structure or 000h if no other items exist in the linked list of Capabilities.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x29cRregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_LTR_CAP.LTR_LATENCY_REGLTR_LATENCY_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr67207This register indicates Latency scale and vlaue for Max Snoop and No-Snoop.0x4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_LTR_CAP_LTR_LATENCY_REGLTR Max Snoop and No-Snoop Latency Register.This register indicates Latency scale and vlaue for Max Snoop and No-Snoop.falsefalsefalsefalseMAX_SNOOP_LATPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67145Max Snoop Latency Value.Along with the Max Snoop LatencyScale field,this register specifies the maximum snoop latency that a device is permitted to request. Software should set this to the platform’s maximum supported latency or less.It is strongly recommended that any updates to this field are reflected in LTR Message(s) sent by the device within 1 ms.The default value for this field is 00 0000 0000b.900x000R/WMAX_SNOOP_LAT_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67160Max Snoop Latency Scale.This register provides a scale for the value contained within the Max Snoop LatencyValue field. Encoding is the same as the LatencyScale fields in the LTR Message.It is strongly recommended that any updates to this field are reflected in LTR Message(s) sent by the device within 1 ms.The default value for this field is 000b.Hardware operation is undefined if software writes a Not Permitted value to this field.12100x0R/WRSVDP_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67168Reserved for future use.15130x0RMAX_NO_SNOOP_LATPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67183Max No-Snoop Latency Value.Along with the Max No-Snoop LatencyScale field, this register specifies the maximum no-snoop latency that a device is permitted to request. Software should set this to the platform’s maximum supported latency or less.It is strongly recommended that any updates to this field are reflected in LTR Message(s) sent by the device within 1 ms.The default value for this field is 00 0000 0000b.25160x000R/WMAX_NO_SNOOP_LAT_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67198Max No-Snoop Latency Scale.This register provides a scale for the value contained within the Max No-Snoop LatencyValue field. Encoding is the same as the LatencyScale fields in the LTR Message.It is strongly recommended that any updates to this field are reflected in LTR Message(s) sent by the device within 1 ms.The default value for this field is 000b.Hardware operation is undefined if software writes a Not Permitted value to this field.28260x0R/WRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67206Reserved for future use.31290x0RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAPPF0_L1SUB_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr676540x29CR/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_L1SUB_CAPL1 Substates Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAP.L1SUB_CAP_HEADER_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAP.L1SUB_CAPABILITY_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL1_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAP.L1SUB_CAP_HEADER_REGL1SUB_CAP_HEADER_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr67282L1 Substates Extended Capability Header provides capbility ID, capability version and next offset value for L1 Substates.0x0R0x2bc1001ePE0_DWC_pcie_ctl_DBI_Slave_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REGL1 Substates Extended Capability Header.This register provides capbility ID, capability version and next offset value for L1 Substates.falsefalsefalsefalseEXTENDED_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67239L1SUB Extended Capability ID.This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability.Extended Capability ID for L1 PM Substates is 001Eh.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x001eRCAP_VERSIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67256Capability Version.This field is a PCI-SIG defined version number that indicates the version of the Capability structure present.This field is depends on version of the specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67281Next Capability Offset.This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities.For Extended Capabilities implemented in Configuration Space, this offset is relative to the beginning of PCI-compatible Configuration Space and thus must always be either 000h (for terminating list of Capabilities) or greater than 0FFh.The bottom 2 bits of this offset are Reserved and must be implemented as 00b although software must mask them to allow for future uses of these bits.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x2bcRregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAP.L1SUB_CAPABILITY_REGL1SUB_CAPABILITY_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr67447This register provides extended capability of L1 Substates.0x4R/W0x00380a1fPE0_DWC_pcie_ctl_DBI_Slave_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REGL1 Substates Capability Register.This register provides extended capability of L1 Substates.falsefalsefalsefalseL1_2_PCIPM_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67300PCI-PM L12 Supported.When Set this bit indicates that PCI-PM L1.2 is supported.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R/W (sticky) 000x1R/WL1_1_PCIPM_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67313PCI-PM L11 Supported.When Set this bit indicates that PCI-PM L1.1 is supported, and must be Set by all Ports implementing L1 PM Substates.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R/W (sticky) 110x1R/WL1_2_ASPM_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67325ASPM L12 Supported.When Set this bit indicates that ASPM L1.2 is supported.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R/W (sticky) 220x1R/WL1_1_ASPM_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67337ASPM L11 Supported.When Set this bit indicates that ASPM L1.1 is supported.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R/W (sticky) 330x1R/WL1_PMSUB_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67350L1 PM Substates ECN Supported.When Set this bit indicates that this Port supports L1 PM Substates.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R/W (sticky) 440x1R/WRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67358Reserved for future use.750x0RCOMM_MODE_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67377Port Common Mode Restore Time.Time (in us) required for this Port to re-establish common mode.Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set, ASPM L1.2 Supported bit is Set, or both are Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 1580x0aR/WPWR_ON_SCALE_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67404Port T Power On Scale.Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register.Range of values are given below.Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set, ASPM L1.2 Supported bit is Set, or both are Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 17160x0R/WfalsetruefalseReserved0x3Reserved.RSVDP_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67412Reserved for future use.18180x0RPWR_ON_VALUE_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67438Port T Power On Value.Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time (in us) that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.The value of Port T_POWER_ON is calculated by multiplying the value in this field by the scale value in the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register. Default value is 00101b.Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set, ASPM L1.2 Supported bit is Set, or both are Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 23190x07R/WRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67446Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL1_REGL1SUB_CONTROL1_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr67569This register provides Controls to extended capability.0x8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_L1SUB_CAP_L1SUB_CONTROL1_REGL1 Substates Control 1 Register.This register provides Controls to extended capability.falsefalsefalsefalseL1_2_PCIPM_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67463PCI-PM L12 Enable.When Set this bit enables PCI-PM L1.2.For Ports for which the PCI-PM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b.000x0R/WL1_1_PCIPM_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67472PCI-PM L11 Enable.When Set this bit enables PCI-PM L1.1. Default value is 0b.110x0R/WL1_2_ASPM_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67482ASPM L12 Enable.When Set this bit enables ASPM L1.2.For Ports for which the ASPM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b.220x0R/WL1_1_ASPM_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67492ASPM L11 Enable.When Set this bit enables ASPM L1.1.For Ports for which the ASPM L1.1 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b.330x0R/WRSVDP_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67500Reserved for future use.740x0RT_COMMON_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67519Common Mode Restore Time.Sets value of TCOMMONMODE (in μs), which must be used by the Downstream Ports for timing the re-establishment of common mode.This field is of type RsvdP for Upstream Ports.Default value is implementation specific.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RW : RSVDP 1580x00R/WL1_2_TH_VALPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67539LTR L12 Threshold Value.Along with the LTR_L1.2_THRESHOLD_Scale, this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 (if enabled) or L1.2 (if enabled). The default value for this field is 00 0000 0000b.Required for all Ports for which the ASPM L12 Supported bit is Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT ? RW : RSVDP - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT ? RW : RSVDP 25160x000R/WRSVDP_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67547Reserved for future use.28260x0RL1_2_TH_SCAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67568LTR L12 Threshold Scale.This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.The default value for this field is 000b.Hardware operation is undefined if software writes a Not-Permitted value to this field.Required for all Ports Ports for which the ASPM L12 Supported bit is Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT ? RW : RSVDP - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT ? RW : RSVDP 31290x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL2_REGL1SUB_CONTROL2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr67653This register provides Controls to extended capability.0xCR/W0x00000028PE0_DWC_pcie_ctl_DBI_Slave_PF0_L1SUB_CAP_L1SUB_CONTROL2_REGL1 Substates Control 2 Register.This register provides Controls to extended capability.falsefalsefalsefalseT_POWER_ON_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67607T Power On Scale.Specifies the scale used for T_POWER_ON Value.Range of values are given below.Required for all Ports that support L1.2, otherwise this field is of type RsvdP. This field must only be modified when the ASPM L1.2 Enable and PCI-PM L1.2 Enable bits are both Clear.The Port behavior is undefined if this field is modified when either the ASPM L1.2 Enable and/or PCI-PM L1.2 Enable bit(s) are Set.Note: The access attributes of this field are as follows: - Wire: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 100x0R/WfalsetruefalseReserved0x3Reserved.RSVDP_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67615Reserved for future use.220x0RT_POWER_ON_VALUEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67644T Power On Value.Along with the T_POWER_ON Scale sets the minimum amount of time (in μs) that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.Default value is 00101b.T_POWER_ON is calculated by multiplying the value in this field by the value in the T_POWER_ON Scale field.Required for all Ports that support L1.2, otherwise this field is of type RsvdP.This field must only be modified when the ASPM L1.2 Enable and PCI-PM L1.2 Enable bits are both Clear.The Port behavior is undefined if this field is modified when either the ASPM L1.2 Enable and/or PCI-PM L1.2 Enable bit(s) are Set.Note: The access attributes of this field are as follows: - Wire: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 730x05R/WRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67652Reserved for future use.3180x000000RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_LNR_CAPPF0_LNR_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr678300x2BCR/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_LNR_CAPPF LNR Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_LNR_CAP.LNR_EXT_CAP_HDR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_LNR_CAP.LNR_CAP_CONTROL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_LNR_CAP.LNR_EXT_CAP_HDR_OFFLNR_EXT_CAP_HDR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr677130x0R0x2c41001cPE0_DWC_pcie_ctl_DBI_Slave_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFFLNR Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseLNR_EXT_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67680PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x001cRLNR_CAP_VERSIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67696Capability Verison.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RLNR_NEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67712Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x2c4RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_LNR_CAP.LNR_CAP_CONTROL_OFFLNR_CAP_CONTROL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr678290x4R/W0x1f000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_LNR_CAP_LNR_CAP_CONTROL_OFFLNR Control Register and Capability Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseLNR_64_SUPPORTEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67735LNR-64 Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.000x0RLNR_128_SUPPORTEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67752LNR-128 Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.110x0RRSVDP_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67760Reserved for future use.720x00RLNR_REGISTRATION_MAXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67777LNR Registration Max.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67785Reserved for future use.15130x0RLNR_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67794LNR Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0R/WLNR_CLSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67803LNR CLS.For a description of this standard PCIe register field, see the PCI Express Base Specification.17170x0R/WRSVDP_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67811Reserved for future use.23180x00RLNR_REGISTRATION_LIMITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67820LNR Registration Limit.For a description of this standard PCIe register field, see the PCI Express Base Specification.28240x1fR/WRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67828Reserved for future use.31290x0RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAPPF0_RAS_DES_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr710700x2C4R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAPRAS D.E.S. Capability Structure (VSEC)registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.RAS_DES_CAP_HEADER_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.VENDOR_SPECIFIC_HEADER_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_CONTROL_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_DATA_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_CONTROL_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_63_32_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ_ENABLE_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ0_CRC_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ1_SEQNUM_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ2_DLLP_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ3_SYMBOL_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ4_FC_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ5_SP_TLP_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H0_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H1_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H3_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H0_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H1_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H3_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H0_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H1_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H3_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H0_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H1_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H3_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_TLP_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_CONTROL1_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_CONTROL2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LANE_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LTSSM_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_PM_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3FC_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL1_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL3_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS1_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS3_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.RAS_DES_CAP_HEADER_REGRAS_DES_CAP_HEADER_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr678890x0R0x3c41000bPE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REGVendor-Specific Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseEXTENDED_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67856PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x000bRCAP_VERSIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67872Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67888Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x3c4RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.VENDOR_SPECIFIC_HEADER_REGVENDOR_SPECIFIC_HEADER_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr679230x4R0x10040002PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REGVendor-Specific Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVSEC_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67904VSEC ID.For a description of this standard PCIe register field, see the PCI Express Specification.1500x0002RVSEC_REVPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67913VSEC Rev.For a description of this standard PCIe register field, see the PCI Express Specification.19160x4RVSEC_LENGTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67922VSEC Length.For a description of this standard PCIe register field, see the PCI Express Specification.31200x100RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_CONTROL_REGEVENT_COUNTER_CONTROL_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr680700x8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REGEvent Counter Control.This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG viewport register. - Setting the EVENT_COUNTER_ENABLE field in this register enables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. - Setting the EVENT_COUNTER_CLEAR field in this register clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. - Reading the EVENT_COUNTER_STATUS field in this register returns the Enable status of the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.falsefalsefalsefalseEVENT_COUNTER_CLEARPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67964Event Counter Clear.Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.You can clear the value of a specific Event Counter by writing the 'per clear' code and you can clear all event counters at once by writing the 'all clear' code.The read value is always '0'. - 00: no change - 01: per clear - 10: no change - 11: all clear - Other: reserved100x0WEVENT_COUNTER_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67990Event Counter Enable.Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.By default, all event counters are disabled.You can enable/disable a specific Event Counter by writing the 'per event off' or 'per event on' codes.You can enable/disable all event counters by writing the 'all on' or 'all off' codes.The read value is always '0'. - 000: no change - 001: per event off - 010: no change - 011: per event on - 100: no change - 101: all off - 110: no change - 111: all on420x0WRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr67998Reserved for future use.650x0REVENT_COUNTER_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68013Event Counter Status.This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECTNote: This register field is sticky.770x0REVENT_COUNTER_LANE_SELECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68030Event Counter Lane Select.This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15Note: This register field is sticky.1180x0R/WRSVDP_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68038Reserved for future use.15120x0REVENT_COUNTER_EVENT_SELECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68061Event Counter Data Select.This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event number(8-bit: 0..0x13) within the GroupFor example: - 0x000: Ebuf Overflow - 0x001: Ebuf Underrun - .. - 0x700: Tx Memory Write - 0x713: Rx Message TLPFor detailed definitions of Group number and Event number, see the RAS DES chapter in the Databook.Note: This register field is sticky.27160x000R/WRSVDP_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68069Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_DATA_REGEVENT_COUNTER_DATA_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr680950xCR0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REGEvent Counter Data.This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REGFor more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEVENT_COUNTER_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68094Event Counter Data.This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REGNote: This register field is sticky.3100x00000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_CONTROL_REGTIME_BASED_ANALYSIS_CONTROL_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr682110x10R/W0x00000100PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REGTime-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseTIMER_STARTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68119Timer Start. - 1: Start/Restart - 0: StopThis bit will be cleared automatically when the measurement is finished.Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop.Note: This register field is sticky.000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68127Reserved for future use.710x00RTIME_BASED_DURATION_SELECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68149Time-based Duration Select.Selects the duration of time-based analysis.When "manual control" is selected and TIMER_START is set to '1', this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1: 1ms - 0x2: 10ms - 0x3: 100ms - 0x4: 1s - 0x5: 2s - 0x6: 4s - 0xff: 4us (Debug purpose) - Else: ReservedNote: This register field is sticky.1580x01R/WRSVDP_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68157Reserved for future use.23160x00RTIME_BASED_REPORT_SELECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68210Time-based Report Select.Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT), and returned in TIME_BASED_ANALYSIS_DATA.Each type of data is measured using one of three types of units: - Core_clk Cycles for 2.5GT/s, 5.0GT/s, 8.0GT/s, 16.0GT/s, 32GT/s. Total time in ps is [Value of TIME_BASED_ANALYSIS_DATA returned when TIME_BASED_REPORT_SELECT=0x00] * TIME_BASED_ANALYSIS_DATA - Aux_clk Cycles. Total time in ps is [Period of platform specific clock] * TIME_BASED_ANALYSIS_DATA - Core_clk Cycles for 20GT/s, 25GT/s (CCIX ESM data rate). Total time in ps is [Value of TIME_BASED_ANALYSIS_DATA returned when TIME_BASED_REPORT_SELECT=0x10] * TIME_BASED_ANALYSIS_DATA - Data Bytes. Actual amount of bytes is 16 * TIME_BASED_ANALYSIS_DATACore_clk Cycles for 2.5GT/s, 5.0GT/s, 8.0GT/s, 16.0GT/s, 32GT/s - 0x00: Duration of 1 cycle - 0x01: TxL0s - 0x02: RxL0s - 0x03: L0 - 0x04: L1 - 0x07: Configuration/Recovery - 0x08: TxL0s and RxL0sAux_clk Cycles - 0x05: L1.1 - 0x06: L1.2 - 0x09: L1 auxCore_clk Cycles for 20GT/s, 25GT/s (CCIX ESM data rate) - 0x10: Duration of 1 cycle - 0x11: TxL0s - 0x12: RxL0s - 0x13: L0 - 0x14: L1 - 0x17: Configuration/Recovery - 0x18: TxL0s and RxL0sData Bytes - 0x20: Tx PCIe TLP data payload Bytes - 0x21: Rx PCIe TLP data payload Bytes - 0x22: Tx CCIX TLP data payload Bytes - 0x23: Rx CCIX TLP data payload Bytes - Else: RsvdNote: This register field is sticky.31240x00R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_REGTIME_BASED_ANALYSIS_DATA_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr682380x14R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REGTime-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state.This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseTIME_BASED_ANALYSIS_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68237Time Based Analysis Data.This register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG.The results are cleared when next measurement starts.Note: This register field is sticky.3100x00000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_63_32_REGTIME_BASED_ANALYSIS_DATA_63_32_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr682590x18R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REGUpper 32 bits of Time-based Analysis Data. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseTIME_BASED_ANALYSIS_DATA_63_32PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68258Upper 32 bits of Time Based Analysis Data.Note: This register field is sticky.3100x00000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ_ENABLE_REGEINJ_ENABLE_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr683960x30R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ_ENABLE_REGError Injection Enable.Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1: Sequence Number Error: EINJ1_SEQNUM_REG - 2: DLLP Error: EINJ2_DLLP_REG - 3: Symbol DataK Mask Error or Sync Header Error: EINJ3_SYMBOL_REG - 4: FC Credit Update Error: EINJ4_FC_REG - 5: TLP Duplicate/Nullify Error: EINJ5_SP_TLP_REG - 6: Specific TLP Error: EINJ6_COMPARE_*_REG/EINJ6_CHANGE_*_REG/EINJ6_TLP_REGAfter the errors have been inserted by controller, it will clear each bit here.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseERROR_INJECTION0_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68292Error Injection0 Enable (CRC Error).Enables insertion of errors into various CRC.For more details, see the EINJ0_CRC_REG register.Note: This register field is sticky.000x0R/WERROR_INJECTION1_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68306Error Injection1 Enable (Sequence Number Error).Enables insertion of errors into sequence numbers.For more details, see the EINJ1_SEQNUM_REG register.Note: This register field is sticky.110x0R/WERROR_INJECTION2_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68320Error Injection2 Enable (DLLP Error).Enables insertion of DLLP errors.For more details, see the EINJ2_DLLP_REG register.Note: This register field is sticky.220x0R/WERROR_INJECTION3_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68336Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error).Enables DataK masking of special symbols or the breaking of the sync header.For more details, see the EINJ3_SYMBOL_REG register.Note: This register field is sticky.330x0R/WERROR_INJECTION4_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68350Error Injection4 Enable (FC Credit Update Error).Enables insertion of errors into UpdateFCs.For more details, see the EINJ4_FC_REG register.Note: This register field is sticky.440x0R/WERROR_INJECTION5_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68364Error Injection5 Enable (TLP Duplicate/Nullify Error).Enables insertion of duplicate/nullified TLPs.For more details, see the EINJ5_SP_TLP_REG register.Note: This register field is sticky.550x0R/WERROR_INJECTION6_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68387Error Injection6 Enable (Specific TLP Error).Enables insertion of errors into the packets that you select.You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT =0.You can set this bit to '1' when you have disabled the address translation by setting ADDR_TRANSLATION_SUPPORT_EN=0.For more details, see the EINJ6_COMPARE_*_REG/EINJ6_CHANGE_*_REG/EINJ6_TLP_REG registers.Note: This register field is sticky.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68395Reserved for future use.3170x0000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ0_CRC_REGEINJ0_CRC_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr684660x34R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ0_CRC_REGError Injection Control 0 (CRC Error).Controls the insertion of errors into the CRC, and parity of ordered sets for the selected type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with NAK DLLP; Data Link Retry starts. - 16-bit CRC of ACK/NAK DLLPs. Bad DLLP occurs at the receiver side; Replay NUM Rollover occurs. - 16-bit CRC of UpdateFC DLLPs. Error insertion continues for the specific time; LTSSM transitions to the Recovery state because of the UpdateFC timeout (if the timeout is implemented at the receiver of the UpdateFCs). - ECRC. If ECRC check is enabled, ECRC error is detected at the receiver side. - FCRC. Framing error will be detected, TLP is discarded, and the LTSSM transitions to Recovery state. - Parity of TSOS. Error insertion continues for the specific time; LTSSM Recovery/Configuration timeout will occur. - Parity of SKPOS. Lane error will be detected at the receiver side.falsefalsefalsefalseEINJ0_COUNTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68434Error injection count.Indicates the number of errors.This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the counter value is 0x00 and ERROR_INJECTION0_ENABLE=1, the errors are inserted until ERROR_INJECTION0_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ0_CRC_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68457Error injection type.Selects the type of CRC error to be inserted.Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC error injection - 0100b: TLP's FCRC error injection (128b/130b) - 0101b: Parity error of TSOS (128b/130b) - 0110b: Parity error of SKPOS (128b/130b)Rx Path - 1000b: LCRC error injection - 1011b: ECRC error injection - Others: ReservedNote: This register field is sticky.1180x0R/WRSVDP_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68465Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ1_SEQNUM_REGEINJ1_SEQNUM_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr685640x38R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REGError Injection Control 1 (Sequence Number Error).Controls the sequence number of the specific TLPs and ACK/NAK DLLPs.Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true: - ((NEXT_TRANSMIT_SEQ -1) - AckNak_Seq_Num) mod 4096 > 2048 - (AckNak_Seq_Num - ACKD_SEQ) mod 4096 >= 2048TLP is treated as Duplicate TLP at the Rx side when all these conditions are true: - Sequence Number != NEXT_RCV_SEQ - (NEXT_RCV_SEQ - Sequence Number) mod 4096 <= 2048TLP is treated as Bad TLP at the Rx side when all these conditions are true: - Sequence Number != NEXT_RCV_SEQ and - (NEXT_RCV_SEQ - Sequence Number) mod 4096 > 2048falsefalsefalsefalseEINJ1_COUNTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68501Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION1_ENABLE=1, the errors are inserted until ERROR_INJECTION1_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ1_SEQNUM_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68513Sequence number type.Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# ErrorNote: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68521Reserved for future use.1590x00REINJ1_BAD_SEQNUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68555Bad sequence number.Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. - 0x1001: -4095For example: - Set Type, SEQ# and Count -- EINJ1_SEQNUM_TYPE =0 (Insert errors into new TLPs) -- EINJ1_BAD_SEQNUM =0x1FFD (represents -3) -- EINJ1_COUNT =1 - Enable Error Injection -- ERROR_INJECTION1_ENABLE =1 - Send a TLP From the Core's Application Interface -- Assume SEQ#5 is given to the TLP. - The SEQ# is Changed to #2 by the Error Injection Function in Layer2. -- 5 + (-3) = 2 - The TLP with SEQ#2 is Transmitted to PCIe Link.Note: This register field is sticky.28160x0000R/WRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68563Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ2_DLLP_REGEINJ2_DLLP_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr686240x3CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ2_DLLP_REGError Injection Control 2 (DLLP Error).Controls the transmission of DLLPs and inserts the following errors: - If "ACK/NAK DLLP's transmission block" is selected, replay timeout error will occur at the transmitter of the TLPs and then Data Link Retry will occur. - If "Update FC DLLP's transmission block" is selected, LTSSM will transition to the Recovery state because of the UpdateFC timeout (if the timeout is implemented at the receiver of the UpdateFCs). - If "Always Transmission for NAK DLLP" is selected, Data Link Retry will occur at the transmitter of the TLPs. Furthermore, Replay NUM Rollover will occur when the transmitter has been requested four times to send the TLP with the same sequence number.falsefalsefalsefalseEINJ2_COUNTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68601Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted, ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION2_ENABLE =1, the errors are inserted until ERROR_INJECTION2_ENABLE is set to '0'.This register is affected only when EINJ2_DLLP_TYPE =2'10b.Note: This register field is sticky.700x00R/WEINJ2_DLLP_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68615DLLP Type.Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: ReservedNote: This register field is sticky.980x0R/WRSVDP_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68623Reserved for future use.31100x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ3_SYMBOL_REGEINJ3_SYMBOL_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr686840x40R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REGError Injection Control 3 (Symbol Error).When 8b/10b encoding is used, this register controls error insertion into the special (K code) symbols. - If TS1/TS2/FTS/E-Idle/SKP is selected, it affects whole of the ordered set. It might cause timeout of the LTSSM. - If END/EDB/STP/SDP is selected, TLP/DLLP will be discarded at the receiver side.When 128b/130b encoding is used, this register controls error insertion into the sync-header.falsefalsefalsefalseEINJ3_COUNTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68652Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION3_ENABLE =1, the errors are inserted until ERROR_INJECTION3_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ3_SYMBOL_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68675Error Type.8b/10b encoding - Mask K symbol. It is not supported to insert errors into the first ordered-set after exiting from TxElecIdle when CX_FREQ_STEP_EN has been enabled. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b: COM/PAD(TS2 Order set) - 011b: COM/FTS(FTS Order set) - 100b: COM/IDL(E-Idle Order set) - 101b: END/EDB Symbol - 110b: STP/SDP Symbol - 111b: COM/SKP(SKP Order set)128b/130b encoding - Change sync header. - 000b: Invert sync header - Others: ReservedNote: This register field is sticky.1080x0R/WRSVDP_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68683Reserved for future use.31110x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ4_FC_REGEINJ4_FC_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr687890x44R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ4_FC_REGError Injection Control 4 (FC Credit Error).Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit - Completion TLP Header credit - Posted TLP Data credit - Non-Posted TLP Data credit - Completion TLP Data creditThese errors are not correctable while error insertion is enabled. Receiver buffer overflow error might occur.falsefalsefalsefalseEINJ4_COUNTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68715Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION4_ENABLE =1, the errors are inserted until ERROR_INJECTION4_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ4_UPDFC_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68733Update-FC type.Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit value control - 101b: Non-Posted TLP Data Credit value control - 110b: Completion TLP Data Credit value control - 111b: ReservedNote: This register field is sticky.1080x0R/WRSVDP_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68741Reserved for future use.11110x0REINJ4_VC_NUMBERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68752VC Number.Indicates target VC Number.Note: This register field is sticky.14120x0R/WRSVDP_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68760Reserved for future use.15150x0REINJ4_BAD_UPDFC_VALUEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68780Bad update-FC credit value.Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. - 0x1001: -4095Note: This register field is sticky.28160x0000R/WRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68788Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ5_SP_TLP_REGEINJ5_SP_TLP_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr688460x48R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REGError Injection Control 5 (Specific TLP Error).Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For Duplicate TLP, the controller initiates Data Link Retry by handling ACK DLLP as NAK DLLP. These TLPs will be duplicate TLPs at the receiver side. - For Nullified TLP, the TLPs that the controller transmits are changed into nullified TLPs and the original TLPs are stored in the retry buffer. The receiver of these TLPs will detect the lack of seq# and send NAK DLLP at the next TLP. Then the original TLPs are sent from retry buffer and the data controls are recovered. For 128 bit controller or more than 128 bit, the controller inserts errors the number of times of EINJ5_COUNT but doesn't ensure that the errors are continuously inserted into TLPs.falsefalsefalsefalseEINJ5_COUNTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68823Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION5_ENABLE =1, the errors are inserted until ERROR_INJECTION5_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ5_SPECIFIED_TLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68837Specified TLP.Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer).Note: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68845Reserved for future use.3190x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H0_REGEINJ6_COMPARE_POINT_H0_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr688840x4CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REGError Injection Control 6 (Compare Point Header DWORD #0).Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_POINT_H0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68883Packet Compare Point: 1st DWORD.Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H1_REGEINJ6_COMPARE_POINT_H1_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr689220x50R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REGError Injection Control 6 (Compare Point Header DWORD #1).Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_POINT_H1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68921Packet Compare Point: 2nd DWORD.Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H2_REGEINJ6_COMPARE_POINT_H2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr689580x54R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REGError Injection Control 6 (Compare Point Header DWORD #2).Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_POINT_H2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68957Packet Compare Point: 3rd DWORD.Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H3_REGEINJ6_COMPARE_POINT_H3_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr689960x58R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REGError Injection Control 6 (Compare Point Header DWORD #3).Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_POINT_H3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr68995Packet Compare Point: 4th DWORD.Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H0_REGEINJ6_COMPARE_VALUE_H0_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr690300x5CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REGError Injection Control 6 (Compare Value Header DWORD #0).Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_VALUE_H0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69029Packet Compare Value: 1st DWORD.Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H1_REGEINJ6_COMPARE_VALUE_H1_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr690640x60R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REGError Injection Control 6 (Compare Value Header DWORD #1).Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_VALUE_H1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69063Packet Compare Value: 2nd DWORD.Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H2_REGEINJ6_COMPARE_VALUE_H2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr690980x64R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REGError Injection Control 6 (Compare Value Header DWORD #2).Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_VALUE_H2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69097Packet Compare Value: 3rd DWORD.Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H3_REGEINJ6_COMPARE_VALUE_H3_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr691320x68R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REGError Injection Control 6 (Compare Value Header DWORD #3).Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_VALUE_H3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69131Packet Compare Value: 4th DWORD.Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H0_REGEINJ6_CHANGE_POINT_H0_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr691640x6CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REGError Injection Control 6 (Change Point Header DWORD #0).Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_POINT_H0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69163Packet Change Point: 1st DWORD.Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H1_REGEINJ6_CHANGE_POINT_H1_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr691960x70R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REGError Injection Control 6 (Change Point Header DWORD #1).Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_POINT_H1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69195Packet Change Point: 2nd DWORD.Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H2_REGEINJ6_CHANGE_POINT_H2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr692280x74R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REGError Injection Control 6 (Change Point Header DWORD #2).Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_POINT_H2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69227Packet Change Point: 3rd DWORD.Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H3_REGEINJ6_CHANGE_POINT_H3_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr692600x78R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REGError Injection Control 6 (Change Point Header DWORD #3).Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_POINT_H3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69259Packet Change Point: 4th DWORD.Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H0_REGEINJ6_CHANGE_VALUE_H0_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr692950x7CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REGError Injection Control 6 (Change Value Header DWORD #0).Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_VALUE_H0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69294Packet Change Value: 1st DWORD.Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H1_REGEINJ6_CHANGE_VALUE_H1_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr693300x80R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REGError Injection Control 6 (Change Value Header DWORD #1).Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_VALUE_H1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69329Packet Change Value: 2nd DWORD.Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H2_REGEINJ6_CHANGE_VALUE_H2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr693650x84R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REGError Injection Control 6 (Change Value Header DWORD #2).Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_VALUE_H2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69364Packet Change Value: 3rd DWORD.Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H3_REGEINJ6_CHANGE_VALUE_H3_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr694000x88R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REGError Injection Control 6 (Change Value Header DWORD #3).Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_VALUE_H3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69399Packet Change Value: 4th DWORD.Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_TLP_REGEINJ6_TLP_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr694810x8CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_TLP_REGError Injection Control 6 (Packet Error).The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the this register.The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the this register.Only applies when EINJ6_INVERTED_CONTROL in this register =0.The TLP into that errors are injected will not arrive at the transaction layer of the remote device when all of the following conditions are true. - Using 128b/130b encoding - Injecting errors into TLP Length field / TLP digest bitfalsefalsefalsefalseEINJ6_COUNTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69444Error Injection Count.Indicates the number of errors to insert.This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION6_ENABLE=1, errors are inserted until ERROR_INJECTION6_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ6_INVERTED_CONTROLPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69457Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3].Note: This register field is sticky.880x0R/WEINJ6_PACKET_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69472Packet type.Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: ReservedNote: This register field is sticky.1190x0R/WRSVDP_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69480Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_CONTROL1_REGSD_CONTROL1_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr695780xA0R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_CONTROL1_REGSilicon Debug Control 1.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseFORCE_DETECT_LANEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69504Force Detect Lane.When the FORCE_DETECT_LANE_EN field is set, the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15Note: This register field is sticky.1500x0000R/WFORCE_DETECT_LANE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69518Force Detect Lane Enable.When this bit is set, the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE.Note: This register field is sticky.16160x0R/WRSVDP_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69526Reserved for future use.19170x0RTX_EIOS_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69551Number of Tx EIOS.This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification.2.5GT/s, 8.0GT/s or higher: - 0x0: 1 - 0x1: 4 - 0x2: 8 - 0x3: 165.0GT/s: - 0x0: 2 - 0x1: 8 - 0x2: 16 - 0x3: 32Note: This register field is sticky.21200x0R/WLOW_POWER_INTERVALPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69569Low Power Entry Interval Time.Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to, RXELECIDLE assertion at the PHY. - 0x0: 40ns - 0x1: 160ns - 0x2: 320ns - 0x3: 640nsNote: This register field is sticky.23220x0R/WRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69577Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_CONTROL2_REGSD_CONTROL2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr697010xA4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_CONTROL2_REGSilicon Debug Control 2.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseHOLD_LTSSMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69596Hold and Release LTSSM.For as long as this register is '1', the controller stays in the current LTSSM.Note: This register field is sticky.000x0R/WRECOVERY_REQUESTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69609Recovery Request.When this bit is set to '1' in L0 or L0s, the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization.110x0WNOACK_FORCE_LINKDOWNPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69623Force LinkDown.When this bit is set and the controller detects REPLY_NUM rolling over 4 times, the LTSSM transitions to Detect State.Note: This register field is sticky.220x0R/WRSVDP_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69631Reserved for future use.730x00RDIRECT_RECIDLE_TO_CONFIGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69644Direct Recovery.Idle to Configuration.When this bit is set and the LTSSM is in Recovery Idle State, the LTSSM transitions to Configuration state.Note: This register field is sticky.880x0R/WDIRECT_POLCOMP_TO_DETECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69657Direct Polling.Compliance to Detect.When this bit is set and the LTSSM is in Polling Compliance State, the LTSSM transitions to Detect state.Note: This register field is sticky.990x0R/WDIRECT_LPBKSLV_TO_EXITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69671Direct Loopback Slave To Exit.When this bit is set and the LTSSM is in Loopback Slave Active State, the LTSSM transitions to Loopback Slave Exit state.Note: This register field is sticky.10100x0R/WRSVDP_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69679Reserved for future use.15110x00RFRAMING_ERR_RECOVERY_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69692Framing Error Recovery Disable.This bit disables a transition to Recovery state when a Framing Error is occurred.Note: This register field is sticky.16160x0R/WRSVDP_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69700Reserved for future use.31170x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LANE_REGSD_STATUS_L1LANE_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr698330xB0R/W0x00180000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REGSilicon Debug Status(Layer1 Per-lane).This viewport register returns the data selected by the following field: - LANE_SELECT in SD_STATUS_L1LANE_REGFor more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseLANE_SELECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69726Lane Select.Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15Note: This register field is sticky.300x0R/WRSVDP_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69734Reserved for future use.1540x000RPIPE_RXPOLARITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69749PIPE:RxPolarity.Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT).Note: This register field is sticky.16160x0RPIPE_DETECT_LANEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69764PIPE:Detect Lane.Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT).Note: This register field is sticky.17170x0RPIPE_RXVALIDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69779PIPE:RxValid.Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT).Note: This register field is sticky.18180x0RPIPE_RXELECIDLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69794PIPE:RxElecIdle.Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT).Note: This register field is sticky.19190x1RPIPE_TXELECIDLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69809PIPE:TxElecIdle.Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT).Note: This register field is sticky.20200x1RRSVDP_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69817Reserved for future use.23210x0RDESKEW_POINTERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69832Deskew Pointer.Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT).Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LTSSM_REGSD_STATUS_L1LTSSM_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr699820xB4R/W0x00000200PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REGSilicon Debug Status(Layer1 LTSSM).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseFRAMING_ERR_PTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69902First Framing Error Pointer.Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1.Received Unexpected Framing Token - 01h: When non- STP/SDP/IDL Token was received and it was not in TLP/DLLP reception - 02h: When current token was not a valid EDB token and previous token was an EDB. (128/256 bit controller only) - 03h: When SDP token was received but not expected. (128 bit & (x8 | x16) controller only) - 04h: When STP token was received but not expected. (128 bit & (x8 | x16) controller only) - 05h: When EDS token was expected but not received or whenever an EDS token was received but not expected. - 06h: When a framing error was detected in the deskew block while a packet has been in progress in token_finder.Received Unexpected STP Token - 11h: When Framing CRC in STP token did not match - 12h: When Framing Parity in STP token did not match. - 13h: When Framing TLP Length in STP token was smaller than 5 DWORDs.Received Unexpected Block - 21h: When Receiving an OS Block following SDS in Datastream state - 22h: When Data Block followed by OS Block different from SKP, EI, EIE in Datastream state - 23h: When Block with an undefined Block Type in Datastream state - 24h: When Data Stream without data over three cycles in Datastream state - 25h: When OS Block during Data Stream in Datastream state - 26h: When RxStatus Error was detected in Datastream state - 27h: When Not all active lanes receiving SKP OS starting at same cycle time in SKPOS state - 28h: When a 2-Block timeout occurs for SKP OS in SKPOS state - 29h: When Receiving consecutive OS Blocks within a Data Stream in SKPOS state - 2Ah: When Phy status error was detected in SKPOS state - 2Bh: When Not all active lanes receiving EIOS starting at same cycle time in EIOS state - 2Ch: When At least one Symbol from the first 4 Symbols is not EIOS Symbol in EIOS state (CX_NB=2 only) - 2Dh: When Not all active lanes receiving EIEOS starting at same cycle time in EIEOS state - 2Eh: When Not full 16 eieos symbols are received in EIEOS stateAll other values not listed above are Reserved.Note: This register field is sticky.600x00RFRAMING_ERRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69913Framing Error.Indicates Framing Error detection status.770x0R/W1CPIPE_POWER_DOWNPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69927PIPE:PowerDown.Indicates PIPE PowerDown signal.Note: This register field is sticky.1080x2RRSVDP_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69935Reserved for future use.14110x0RLANE_REVERSALPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69951Lane Reversal Operation.Receiver detected lane reversal.This field is only valid in the L0 LTSSM state.Note: This register field is sticky.15150x0RLTSSM_VARIABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr69981LTSSM Variable.Indicates internal LTSSM variables defined in the PCI Express Base Specification.C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if both ports advertised the UpConfigure capability in the last Config.Complete. - 4: select_deemphasis - 5: start_equalization_w_preset - 6: equalization_done_8GT_data_rate - 7: equalization_done_16GT_data_rate - 15:8: idle_to_rlock_transitionedM-PCIe Mode: - 0: idle_to_recovery - 1: recovery_to_configurationNote: This register field is sticky.31160x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_PM_REGSD_STATUS_PM_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr701230xB8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_STATUS_PM_REGSilicon Debug Status(PM).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseINTERNAL_PM_MSTATEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70024Internal PM State(Master).Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah: L1_WAIT_LAST_TLP_ACK - 0Bh: L1_WAIT_PMDLLP_ACK - 0Ch: L1_LINK_ENTR_L1 - 0Dh: L1_EXIT - 0Fh: PREP_4L1 - 10h: L23_BLOCK_TLP - 11h: L23_WAIT_LAST_TLP_ACK - 12h: L23_WAIT_PMDLLP_ACK - 13h: L23_ENTR_L23 - 14h: L23RDY - 15h: PREP_4L23 - 16h: L23RDY_WAIT4ALIVE - 17h: L0S_BLOCK_TLP - 18h: WAIT_LAST_PMDLLP - 19h: WAIT_DSTATE_UPDATENote: This register field is sticky.400x00RRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70032Reserved for future use.750x0RINTERNAL_PM_SSTATEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70059Internal PM State(Slave).Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h: S_L1_EXIT - 8h: S_L23RDY - 9h: S_LINK_ENTR_L23 - Ah: S_L23RDY_WAIT4ALIVE - Bh: S_ACK_WAIT4IDLE - Ch: S_WAIT_LAST_PMDLLPNote: This register field is sticky.1180x0RPME_RESEND_FLAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70073PME Re-send flag.When the DUT sends a PM_PME message TLP, the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%), the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent.12120x0R/W1CL1SUB_STATEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70099L1Sub State.Indicates internal state machine of L1Sub state. - 0h: S_L1_U : idle state - 1h: S_L1_0 : wait for aux_clk_active - 2h: S_L1_0_WAIT4_ACK : wait for pclkack - 3h: S_L1_0_WAIT4_CLKREQ : wait for clkreq - 4h: S_L1_N_ENTRY : check clkreq_in_n is de-asserted for t_power_off time (only for L1.2, reduces to one cycle for L1.1) - 5h: S_L1_N : L1 substate, turn off txcommonmode circuits (L1.2 only) and rx electrical idle detection circuits - 6h: S_L1_N_EXIT : locally/remotely initiated exit, assert pclkreq, wait for pclkack - 7h: S_L1_N_ABORT : wait for pclkack when aborting an attempt to enter L1_NNote: This register field is sticky.15130x0RLATCHED_NFTSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70114Latched N_FTS.Indicates the value of N_FTS in the received TS Ordered Sets from the Link PartnerNote: This register field is sticky.23160x00RRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70122Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L2_REGSD_STATUS_L2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr702040xBCR0x00fff000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L2_REGSilicon Debug Status(Layer2).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseTX_TLP_SEQ_NOPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70142Tx Tlp Sequence Number.Indicates next transmit sequence number for transmit TLP.Note: This register field is sticky.1100x000RRX_ACK_SEQ_NOPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70156Tx Ack Sequence Number.Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP.Note: This register field is sticky.23120xfffRDLCMSMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70171DLCMSM.Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVENote: This register field is sticky.25240x0RFC_INIT1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70184FC_INIT1.Indicates the controller is in FC_INIT1(VC0) state.Note: This register field is sticky.26260x0RFC_INIT2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70196FC_INIT2.Indicates the controller is in FC_INIT2(VC0) state.Note: This register field is sticky.27270x0RRSVDP_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70203Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3FC_REGSD_STATUS_L3FC_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr703280xC0R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REGSilicon Debug Status(Layer3 FC).The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE - CREDIT_SEL_HDFor more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseCREDIT_SEL_VCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70235Credit Select(VC).This field in conjunction with the CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 - 0x1: VC1 - 0x2: VC2 - .. - 0x7: VC7Note: This register field is sticky.200x0R/WCREDIT_SEL_CREDIT_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70251Credit Select(Credit Type).This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Rx - 0x1: TxNote: This register field is sticky.330x0R/WCREDIT_SEL_TLP_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70268Credit Select(TLP Type).This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Posted - 0x1: Non-Posted - 0x2: CompletionNote: This register field is sticky.540x0R/WCREDIT_SEL_HDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70284Credit Select(HeaderData).This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Header Credit - 0x1: Data CreditNote: This register field is sticky.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70292Reserved for future use.770x0RCREDIT_DATA0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70309Credit Data0.Current FC credit data selected by the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed ValueNote: This register field is sticky.1980x000RCREDIT_DATA1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70327Credit Data1.Current FC credit data selected by the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when DLCMSM=0x3(DL_ACTIVE).Note: This register field is sticky.31200x000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3_REGSD_STATUS_L3_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr703840xC4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L3_REGSilicon Debug Status(Layer3).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseMFTLP_POINTERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70364First Malformed TLP Error Pointer.Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length miss match - 05h: Max payload size - 06h: Message TLP without TC0 - 07h: Invalid TC - 08h: Unexpected route bit in Message TLP - 09h: Unexpected CRS status in Completion TLP - 0Ah: Byte enable - 0Bh: Memory Address 4KB boundary - 0Ch: TLP prefix rules - 0Dh: Translation request rules - 0Eh: Invalid TLP type - 0Fh: Completion rules - 7Fh: Application - Else: ReservedNote: This register field is sticky.600x00RMFTLP_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70375Malformed TLP Status.Indicates malformed TLP has occurred.770x0R/W1CRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70383Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL1_REGSD_EQ_CONTROL1_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr705240xD0R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REGSilicon Debug EQ Control 1.This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport registers.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEQ_LANE_SELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70412EQ Status Lane Select.Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15Note: This register field is sticky.300x0R/WEQ_RATE_SELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70429EQ Status Rate Select.Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed (include ESM data rate) - 0x1: 16.0GT/s Speed (include ESM data rate) - 0x2: 32.0GT/s SpeedNote: This register field is sticky.540x0R/WRSVDP_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70437Reserved for future use.760x0REXT_EQ_TIMEOUTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70461Extends EQ Phase2/3 Timeout.This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set, the value of EQ2/3 timeout is extended.EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10: 240ms (x10) - 11: No timeoutEQ Slave(DSP in EQ Phase2/USP in EQ Phase3). - 00: 32ms (default) - 01: 56ms (32ms+24ms) - 10: 248ms (32ms +9*24ms) - 11: No timeoutNote: This register field is sticky.980x0R/WRSVDP_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70469Reserved for future use.15100x00REVAL_INTERVAL_TIMEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70487Eval Interval Time.Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4usThis field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2).Note: This register field is sticky.17160x0R/WRSVDP_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70495Reserved for future use.22180x00RFOM_TARGET_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70507FOM Target Enable.Enables the FOM_TARGET fields.Note: This register field is sticky.23230x0R/WFOM_TARGETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70523FOM Target.Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2).This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit).Note: This register field is sticky.31240x00R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL2_REGSD_EQ_CONTROL2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr706680xD4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REGSilicon Debug EQ Control 2.This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseFORCE_LOCAL_TX_PRE_CURSORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70546Force Local Transmitter Pre-cursor.Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner.Note: This register field is sticky.500x00R/WFORCE_LOCAL_TX_CURSORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70560Force Local Transmitter Cursor.Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner.Note: This register field is sticky.1160x00R/WFORCE_LOCAL_TX_POST_CURSORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70574Force Local Transmitter Post-Cursor.Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner.Note: This register field is sticky.17120x00R/WFORCE_LOCAL_RX_HINTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70591Force Local Receiver Preset Hint.Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of received or set value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed, this feature is not available.Note: This register field is sticky.20180x0R/WRSVDP_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70599Reserved for future use.23210x0RFORCE_LOCAL_TX_PRESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70615Force Local Transmitter Preset.Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed, this feature is not available.Note: This register field is sticky.27240x0R/WFORCE_LOCAL_TX_COEF_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70629Force Local Transmitter Coefficient Enable.Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSORNote: This register field is sticky.28280x0R/WFORCE_LOCAL_RX_HINT_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70644Force Local Receiver Preset Hint Enable.Enables the FORCE_LOCAL_RX_HINT field.If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed, this feature is not available.Note: This register field is sticky.29290x0R/WFORCE_LOCAL_TX_PRESET_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70659Force Local Transmitter Preset Enable.Enables the FORCE_LOCAL_TX_PRESET field.If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed, this feature is not available.Note: This register field is sticky.30300x0R/WRSVDP_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70667Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL3_REGSD_EQ_CONTROL3_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr707520xD8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REGSilicon Debug EQ Control 3.This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseFORCE_REMOTE_TX_PRE_CURSORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70690Force Remote Transmitter Pre-Cursor.Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from local phy in dirchange mode.Note: This register field is sticky.500x00R/WFORCE_REMOTE_TX_CURSORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70704Force Remote Transmitter Cursor.Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from local phy in dirchange mode.Note: This register field is sticky.1160x00R/WFORCE_REMOTE_TX_POST_CURSORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70718Force Remote Transmitter Post-Cursor.Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from local phy in dirchange mode.Note: This register field is sticky.17120x00R/WRSVDP_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70726Reserved for future use.27180x000RFORCE_REMOTE_TX_COEF_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70743Force Remote Transmitter Coefficient Enable.Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSORThis function can only be used when GEN3_EQ_FB_MODE = 0000b(Direction Change)Note: This register field is sticky.28280x0R/WRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70751Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS1_REGSD_EQ_STATUS1_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr708960xE0R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REGSilicon Debug EQ Status 1.This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.The following fields are available when Equalization finished unsuccessfully(EQ_CONVERGENCE_INFO=2). - EQ_RULEA_VIOLATION - EQ_RULEB_VIOLATION - EQ_RULEC_VIOLATION - EQ_REJECT_EVENTFor more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEQ_SEQUENCEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70782EQ Sequence.Indicates that the controller is starting the equalization sequence.Note: This register field is sticky.000x0REQ_CONVERGENCE_INFOPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70801EQ Convergence Info.Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: ReservedThis bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.210x0RRSVDP_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70808Reserved for future use.330x0REQ_RULEA_VIOLATIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70829EQ Rule A Violation.Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to the rules a) from section "Rules for Transmitter Coefficents" in the PCI Express Base Specification.This bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.440x0REQ_RULEB_VIOLATIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70850EQ Rule B Violation.Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to the rules b) from section "Rules for Transmitter Coefficents" in the PCI Express Base Specification.This bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.550x0REQ_RULEC_VIOLATIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70871EQ Rule C Violation.Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to the rules c) from section "Rules for Transmitter Coefficents" in the PCI Express Base Specification.This bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.660x0REQ_REJECT_EVENTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70888EQ Reject Event.Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2).This bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.770x0RRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70895Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS2_REGSD_EQ_STATUS2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr709840xE4R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REGSilicon Debug EQ Status 2.This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.Each field is available when Equalization finished successfully(EQ_CONVERGENCE_INFO=1).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEQ_LOCAL_PRE_CURSORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70921EQ Local Pre-Cursor.Indicates Local pre cursor coefficient value.Note: This register field is sticky.500x00REQ_LOCAL_CURSORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70934EQ Local Cursor.Indicates Local cursor coefficient value.Note: This register field is sticky.1160x00REQ_LOCAL_POST_CURSORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70947EQ Local Post-Cursor.Indicates Local post cursor coefficient value.Note: This register field is sticky.17120x00REQ_LOCAL_RX_HINTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70963EQ Local Receiver Preset Hint.Indicates Local Receiver Preset Hint value.If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed, this feature is not available.Note: This register field is sticky.20180x0RRSVDP_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70970Reserved for future use.23210x0REQ_LOCAL_FOM_VALUEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr70983EQ Local Figure of Merit.Indicates Local maximum Figure of Merit value.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS3_REGSD_EQ_STATUS3_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr710690xE8R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REGSilicon Debug EQ Status 3.This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.Each field is available when Equalization finished successfully(EQ_CONVERGENCE_INFO=1).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEQ_REMOTE_PRE_CURSORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71009EQ Remote Pre-Cursor.Indicates Remote pre cursor coefficient value.Note: This register field is sticky.500x00REQ_REMOTE_CURSORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71022EQ Remote Cursor.Indicates Remote cursor coefficient value.Note: This register field is sticky.1160x00REQ_REMOTE_POST_CURSORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71035EQ Remote Post-Cursor.Indicates Remote post cursor coefficient value.Note: This register field is sticky.17120x00REQ_REMOTE_LFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71048EQ Remote LF.Indicates Remote LF value.Note: This register field is sticky.23180x00REQ_REMOTE_FSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71061EQ Remote FS.Indicates Remote FS value.Note: This register field is sticky.29240x00RRSVDP_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71068Reserved for future use.31300x0RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAPPF0_VSECRAS_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr721230x3C4R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAPPF RAS Datapath Protection Capability Structure (VSEC)registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_EXT_CAP_HDR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_VENDOR_SPECIFIC_HDR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_PROT_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNTER_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNT_REPORT_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNTER_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNT_REPORT_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_INJ_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_ERROR_LOCATION_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_ERROR_LOCATION_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_CLEAR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_CORR_ERROR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_UNCORR_ERROR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_EXT_CAP_HDR_OFFRASDP_EXT_CAP_HDR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr711300x0R0x3fc1000bPE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFFPCIe Extended capability ID, Capability version and Next capability offset.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseIDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71097PCI Express Extended Capability ID.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x000bRCAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71113Capability Version.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71129Next Capability Offset.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x3fcRregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_VENDOR_SPECIFIC_HDR_OFFRASDP_VENDOR_SPECIFIC_HDR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr711730x4R0x03810001PE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFFVendor Specific Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVSEC_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71148VSEC ID.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.1500x0001RVSEC_REVPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71160VSEC Rev.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.19160x1RVSEC_LENGTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71172VSEC Length.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.31200x038RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_PROT_CTRL_OFFRASDP_ERROR_PROT_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr71379ECC error correction control0x8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFFECC error correction control. Allows you to disable ECC error correction for RAMs and datapath.When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native controller clock (core_clk), you must not write this register while operations are in progress in the AXI master / slave interface.falsefalsefalsefalseERROR_PROT_DISABLE_TXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71197Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors.Note: This register field is sticky.000x0R/WERROR_PROT_DISABLE_AXI_BRIDGE_MASTERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71208Error correction disable for AXI bridge master completion buffer.Note: This register field is sticky.110x0R/WERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71219Error correction disable for AXI bridge outbound request path.Note: This register field is sticky.220x0R/WERROR_PROT_DISABLE_DMA_WRITEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71229Error correction disable for DMA write engine.Note: This register field is sticky.330x0R/WERROR_PROT_DISABLE_LAYER2_TXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71239Error correction disable for layer 2 Tx path.Note: This register field is sticky.440x0R/WERROR_PROT_DISABLE_LAYER3_TXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71249Error correction disable for layer 3 Tx path.Note: This register field is sticky.550x0R/WERROR_PROT_DISABLE_ADM_TXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71259Error correction disable for Adm Tx path.Note: This register field is sticky.660x0R/WERROR_PROT_DISABLE_CXS_TXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71269Error correction disable for CXS Rx path (PCIe Tx path).Note: This register field is sticky.770x0R/WERROR_PROT_DISABLE_DTIM_TXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71279Error correction disable for DTIM Tx path.Note: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71287Reserved for future use.1590x00RERROR_PROT_DISABLE_RXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71297Global error correction disable for all Rx layers.Note: This register field is sticky.16160x0R/WERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71309Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors.Note: This register field is sticky.17170x0R/WERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUESTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71320Error correction disable for AXI bridge inbound request path.Note: This register field is sticky.18180x0R/WERROR_PROT_DISABLE_DMA_READPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71330Error correction disable for DMA read engine.Note: This register field is sticky.19190x0R/WERROR_PROT_DISABLE_LAYER2_RXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71340Error correction disable for layer 2 Rx path.Note: This register field is sticky.20200x0R/WERROR_PROT_DISABLE_LAYER3_RXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71350Error correction disable for layer 3 Rx path.Note: This register field is sticky.21210x0R/WERROR_PROT_DISABLE_ADM_RXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71360Error correction disable for ADM Rx path.Note: This register field is sticky.22220x0R/WERROR_PROT_DISABLE_CXS_RXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71370Error correction disable for CXS Tx path (PCIe Rx path).Note: This register field is sticky.23230x0R/WRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71378Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNTER_CTRL_OFFRASDP_CORR_COUNTER_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr714660xCR/W0x00000010PE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFFCorrected error (1-bit ECC) counter selection and control.This is a viewport control register.Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned by the RASDP_CORR_COUNT_REPORT_OFF viewport data register.falsefalsefalsefalseCORR_CLEAR_COUNTERSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71396Clear all correctable error counters.000x0WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71404Reserved for future use.310x0RCORR_EN_COUNTERSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71416Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozenThe counters are enabled by default.440x1R/WRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71424Reserved for future use.1950x0000RCORR_COUNTER_SELECTION_REGIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71450Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200x0R/WCORR_COUNTER_SELECTIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71465Counter selection.This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf31240x00R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNT_REPORT_OFFRASDP_CORR_COUNT_REPORT_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr715280x10R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFFCorrected error (1-bit ECC) counter data.This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register.falsefalsefalsefalseCORR_COUNTERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71482Current corrected error count for the selected counter.700x00RRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71489Reserved for future use.1980x000RCORR_COUNTER_SELECTED_REGIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71516Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200x0RCORR_COUNTER_SELECTEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71527Counter selection.Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNTER_CTRL_OFFRASDP_UNCORR_COUNTER_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr716190x14R/W0x00000010PE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFFUncorrected error (2-bit ECC and parity) counter selection and control.This is a viewport control register.Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the counter data returned by the RASDP_UNCORR_COUNT_REPORT_OFF viewport data register.falsefalsefalsefalseUNCORR_CLEAR_COUNTERSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71548Clear uncorrectable errors counters.When asserted causes all counters tracking the uncorrectable errors to be cleared.000x0WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71556Reserved for future use.310x0RUNCORR_EN_COUNTERSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71568Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozenThe counters are enabled by default.440x1R/WRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71576Reserved for future use.1950x0000RUNCORR_COUNTER_SELECTION_REGIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71602Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200x0R/WUNCORR_COUNTER_SELECTIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71618Counter selection.This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf31240x00R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNT_REPORT_OFFRASDP_UNCORR_COUNT_REPORT_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr716820x18R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFFUncorrected error (2-bit ECC and parity) counter data.This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF register.falsefalsefalsefalseUNCORR_COUNTERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71636Current uncorrected error count for the selected counter700x00RRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71643Reserved for future use.1980x000RUNCORR_COUNTER_SELECTED_REGIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71670Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200x0RUNCORR_COUNTER_SELECTEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71681Counter selection.Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_INJ_CTRL_OFFRASDP_ERROR_INJ_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr71762Error injection control0x1CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFFError injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occursfalsefalsefalsefalseERROR_INJ_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71700Error injection global enable.When set enables the error insertion logic.000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71708Reserved for future use.310x0RERROR_INJ_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71719Error injection type: - 0: none - 1: 1-bit - 2: 2-bit540x0R/WRSVDP_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71727Reserved for future use.760x0RERROR_INJ_COUNTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71740Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected1580x00R/WERROR_INJ_LOCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71753Error injection location.Selects where error injection takes place.You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf23160x00R/WRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71761Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_ERROR_LOCATION_OFFRASDP_CORR_ERROR_LOCATION_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr71869Corrected errors locations.0x20R0x00d000d0PE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFFCorrected errors locations. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71777Reserved for future use.300x0RREG_FIRST_CORR_ERRORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71804Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved740xdRLOC_FIRST_CORR_ERRORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71819Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf1580x00RRSVDP_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71826Reserved for future use.19160x0RREG_LAST_CORR_ERRORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71853Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200xdRLOC_LAST_CORR_ERRORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71868Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_ERROR_LOCATION_OFFRASDP_UNCORR_ERROR_LOCATION_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr71976Uncorrected errors locations.0x24R0x00d000d0PE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFFUncorrected errors locations. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71884Reserved for future use.300x0RREG_FIRST_UNCORR_ERRORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71911Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved740xdRLOC_FIRST_UNCORR_ERRORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71926Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf1580x00RRSVDP_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71933Reserved for future use.19160x0RREG_LAST_UNCORR_ERRORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71960Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200xdRLOC_LAST_UNCORR_ERRORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr71975Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_EN_OFFRASDP_ERROR_MODE_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr72020RASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error.0x28R/W0x00000001PE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFFRASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are forwarded to your application are not guaranteed to be correct; you must discard them.For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseERROR_MODE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72000Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error.Note: This register field is sticky.000x1R/WAUTO_LINK_DOWN_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72011Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode.Note: This register field is sticky.110x0R/WRSVDP_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72019Reserved for future use.3120x00000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_CLEAR_OFFRASDP_ERROR_MODE_CLEAR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr72048Exit RASDP error mode.0x2CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFFExit RASDP error mode. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseERROR_MODE_CLEARPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72039Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs.000x0WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72047Reserved for future use.3110x00000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_CORR_ERROR_OFFRASDP_RAM_ADDR_CORR_ERROR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr72085RAM Address where a corrected error (1-bit ECC) has been detected.0x30R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFFRAM Address where a corrected error (1-bit ECC) has been detected. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseRAM_ADDR_CORR_ERRORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72067RAM Address where a corrected error (1-bit ECC) has been detected.2600x0000000RRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72074Reserved for future use.27270x0RRAM_INDEX_CORR_ERRORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72084RAM index where a corrected error (1-bit ECC) has been detected.31280x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_UNCORR_ERROR_OFFRASDP_RAM_ADDR_UNCORR_ERROR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr72122RAM Address where an uncorrected error (2-bit ECC) has been detected.0x34R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFFRAM Address where an uncorrected error (2-bit ECC) has been detected. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseRAM_ADDR_UNCORR_ERRORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72104RAM Address where an uncorrected error (2-bit ECC) has been detected.2600x0000000RRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72111Reserved for future use.27270x0RRAM_INDEX_UNCORR_ERRORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72121RAM index where an uncorrected error (2-bit ECC) has been detected.31280x0RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_DLINK_CAPPF0_DLINK_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr723030x3FCRPE0_DWC_pcie_ctl_DBI_Slave_PF0_DLINK_CAPPF DLINK Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_EXT_HDR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_CAP_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_EXT_HDR_OFFDATA_LINK_FEATURE_EXT_HDR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr72197This register provides capbility ID, capability version and next offset value.0x0R0x40810025PE0_DWC_pcie_ctl_DBI_Slave_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFFData Link Feature Extended Capability Header.This register provides capbility ID, capability version and next offset value.falsefalsefalsefalseDLINK_EXT_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72153Capability ID.This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability.Extended Capability ID for Data Link Feature is 0025h.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0025RDLINK_CAP_VERSIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72170Capability Version.This field is a PCI-SIG defined version number that indicates the version of the Capability structure present.This field is depends on version of the specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RDLINK_NEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72196Next Capability Offset.This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities.For Extended Capabilities implemented in Configuration Space, this offset is relative to the beginning of PCI-compatible Configuration Space and thus must always be either 000h (for terminating list of Capabilities) or greater than 0FFh.The bottom 2 bits of this offset are Reserved and must be implemented as 00b although software must mask them to allow for future uses of these bits.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x408RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_CAP_OFFDATA_LINK_FEATURE_CAP_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr72258This register provides description about extended feature.0x4R0x80000001PE0_DWC_pcie_ctl_DBI_Slave_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFFData Link Feature Capabilities.This register provides description about extended feature.falsefalsefalsefalseSCALED_FLOW_CNTL_SUPPORTEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72221Local Scaled Flow Control Supported.Bit 0 – Local Scaled Flow Control Supported. Bit 22:1 – RsvdP.Bits associated with features that this Port is capable of supporting are HwInit, defaulting to 1b.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 000x1RFUTURE_FEATURE_SUPPORTEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72235Local Future Data Link Feature Supported.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.2210x000000RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72242Reserved for future use.30230x00RDL_FEATURE_EXCHANGE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72257Data Link Feature Exchange Enable.If Set, this bit indicates that this Port will enter the DL_Feature negotiation state. Default is 1b.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 31310x1RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_STATUS_OFFDATA_LINK_FEATURE_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr72302This Registor privides status of the capability of data link feature.0x8R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFFData Link Feature Status Register.This Registor privides status of the capability of data link feature.falsefalsefalsefalseREMOTE_DATA_LINK_FEATURE_SUPPORTEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72279Remote Data Link Feature SupportedFeatures Currently defined are: Bit 0 - Remote Scaled Flow Control Supported.Other Bits are undefined. Default value is 00 0000h.2200x000000RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72286Reserved for future use.30230x00RDATA_LINK_FEATURE_STATUS_VALIDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72301Remote Data Link Feature Supported Valid.This bit indicates that the Port has received a Data Link Feature DLLP in state DL_Feature (see Section 3.2.1) and that the Remote Data Link Feature Supported and Remote Data Link Feature Ack fields arefield is meaningful. This bit is Cleared on entry to state DL_Inactive.Default is 0b.31310x0RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_RESBAR_CAPPF0_RESBAR_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr731450x408R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_RESBAR_CAPResizable BAR Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_HDR_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_REG_0_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RESBAR_CAP.RESBAR_CTRL_REG_0_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_HDR_REGRESBAR_CAP_HDR_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr723620x0R0x44810015PE0_DWC_pcie_ctl_DBI_Slave_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REGResizable BAR Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRESBAR_EXT_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72329Resizable BAR Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0015RRESBAR_CAP_VERSIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72345Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RRESBAR_CAP_NEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72361Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x448RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_REG_0_REGRESBAR_CAP_REG_0_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr728240x4R/W0x00000010PE0_DWC_pcie_ctl_DBI_Slave_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REGResizable BAR0 Capability Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72375Reserved for future use.300x0RRESBAR_CAP_REG_0_1MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72391Up to 1MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.440x1R/WRESBAR_CAP_REG_0_2MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72407Up to 2MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.550x0R/WRESBAR_CAP_REG_0_4MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72423Up to 4MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.660x0R/WRESBAR_CAP_REG_0_8MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72439Up to 8MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.770x0R/WRESBAR_CAP_REG_0_16MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72455Up to 16MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.880x0R/WRESBAR_CAP_REG_0_32MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72471Up to 32MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.990x0R/WRESBAR_CAP_REG_0_64MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72487Up to 64MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.10100x0R/WRESBAR_CAP_REG_0_128MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72503Up to 128MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.11110x0R/WRESBAR_CAP_REG_0_256MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72519Up to 256MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.12120x0R/WRESBAR_CAP_REG_0_512MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72535Up to 512MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.13130x0R/WRESBAR_CAP_REG_0_1GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72551Up to 1GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.14140x0R/WRESBAR_CAP_REG_0_2GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72567Up to 2GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.15150x0R/WRESBAR_CAP_REG_0_4GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72583Up to 4GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0R/WRESBAR_CAP_REG_0_8GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72599Up to 8GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0R/WRESBAR_CAP_REG_0_16GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72615Up to 16GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0R/WRESBAR_CAP_REG_0_32GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72631Up to 32GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0R/WRESBAR_CAP_REG_0_64GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72647Up to 64GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0R/WRESBAR_CAP_REG_0_128GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72663Up to 128GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0R/WRESBAR_CAP_REG_0_256GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72679Up to 256GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0R/WRESBAR_CAP_REG_0_512GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72695Up to 512GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0R/WRESBAR_CAP_REG_0_1TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72711Up to 1TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0R/WRESBAR_CAP_REG_0_2TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72727Up to 2TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0R/WRESBAR_CAP_REG_0_4TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72743Up to 4TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0R/WRESBAR_CAP_REG_0_8TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72759Up to 8TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0R/WRESBAR_CAP_REG_0_16TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72775Up to 16TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0R/WRESBAR_CAP_REG_0_32TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72791Up to 32TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0R/WRESBAR_CAP_REG_0_64TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72807Up to 64TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0R/WRESBAR_CAP_REG_0_128TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72823Up to 128TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RESBAR_CAP.RESBAR_CTRL_REG_0_REGRESBAR_CTRL_REG_0_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr731440x8R/W0x00000020PE0_DWC_pcie_ctl_DBI_Slave_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REGResizable BAR0 Control Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRESBAR_CTRL_REG_IDX_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72843BAR Index.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.200x0RRSVDP_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72851Reserved for future use.430x0RRESBAR_CTRL_REG_NUM_BARSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72865Number of Resizeable BARs.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.750x1RRESBAR_CTRL_REG_BAR_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72879BAR Size.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1380x00R/WRSVDP_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72887Reserved for future use.15140x0RRESBAR_CTRL_REG_0_256TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72903Up to 256TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0R/WRESBAR_CTRL_REG_0_512TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72919Up to 512TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0R/WRESBAR_CTRL_REG_0_1PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72935Up to 1PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0R/WRESBAR_CTRL_REG_0_2PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72951Up to 2PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0R/WRESBAR_CTRL_REG_0_4PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72967Up to 4PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0R/WRESBAR_CTRL_REG_0_8PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72983Up to 8PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0R/WRESBAR_CTRL_REG_0_16PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr72999Up to 16PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0R/WRESBAR_CTRL_REG_0_32PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73015Up to 32PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0R/WRESBAR_CTRL_REG_0_64PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73031Up to 64PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0R/WRESBAR_CTRL_REG_0_128PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73047Up to 128PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0R/WRESBAR_CTRL_REG_0_256PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73063Up to 256PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0R/WRESBAR_CTRL_REG_0_512PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73079Up to 512PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0R/WRESBAR_CTRL_REG_0_1EBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73095Up to 1EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0R/WRESBAR_CTRL_REG_0_2EBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73111Up to 2EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0R/WRESBAR_CTRL_REG_0_4EBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73127Up to 4EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0R/WRESBAR_CTRL_REG_0_8EBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73143Up to 8EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0R/WgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_VF_RESBAR_CAPPF0_VF_RESBAR_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr755510x448R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_VF_RESBAR_CAPVF Resizable BAR Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_HDR_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_0_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_0_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_1_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_1_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_HDR_REGVF_RESBAR_CAP_HDR_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr732040x0R0x00010024PE0_DWC_pcie_ctl_DBI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REGResizable BAR Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVF_RESBAR_EXT_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73171Resizable BAR Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0024RVF_RESBAR_CAP_VERSIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73187Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RVF_RESBAR_CAP_NEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73203Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_0_REGVF_RESBAR_CAP_REG_0_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr736660x4R/W0x00000010PE0_DWC_pcie_ctl_DBI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REGResizable BAR0 Capability Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73217Reserved for future use.300x0RVF_RESBAR_CAP_REG_0_1MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73233Up to 1MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.440x1R/WVF_RESBAR_CAP_REG_0_2MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73249Up to 2MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.550x0R/WVF_RESBAR_CAP_REG_0_4MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73265Up to 4MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.660x0R/WVF_RESBAR_CAP_REG_0_8MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73281Up to 8MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.770x0R/WVF_RESBAR_CAP_REG_0_16MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73297Up to 16MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.880x0R/WVF_RESBAR_CAP_REG_0_32MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73313Up to 32MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.990x0R/WVF_RESBAR_CAP_REG_0_64MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73329Up to 64MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.10100x0R/WVF_RESBAR_CAP_REG_0_128MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73345Up to 128MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.11110x0R/WVF_RESBAR_CAP_REG_0_256MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73361Up to 256MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.12120x0R/WVF_RESBAR_CAP_REG_0_512MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73377Up to 512MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.13130x0R/WVF_RESBAR_CAP_REG_0_1GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73393Up to 1GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.14140x0R/WVF_RESBAR_CAP_REG_0_2GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73409Up to 2GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.15150x0R/WVF_RESBAR_CAP_REG_0_4GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73425Up to 4GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0R/WVF_RESBAR_CAP_REG_0_8GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73441Up to 8GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0R/WVF_RESBAR_CAP_REG_0_16GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73457Up to 16GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0R/WVF_RESBAR_CAP_REG_0_32GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73473Up to 32GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0R/WVF_RESBAR_CAP_REG_0_64GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73489Up to 64GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0R/WVF_RESBAR_CAP_REG_0_128GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73505Up to 128GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0R/WVF_RESBAR_CAP_REG_0_256GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73521Up to 256GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0R/WVF_RESBAR_CAP_REG_0_512GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73537Up to 512GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0R/WVF_RESBAR_CAP_REG_0_1TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73553Up to 1TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0R/WVF_RESBAR_CAP_REG_0_2TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73569Up to 2TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0R/WVF_RESBAR_CAP_REG_0_4TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73585Up to 4TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0R/WVF_RESBAR_CAP_REG_0_8TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73601Up to 8TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0R/WVF_RESBAR_CAP_REG_0_16TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73617Up to 16TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0R/WVF_RESBAR_CAP_REG_0_32TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73633Up to 32TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0R/WVF_RESBAR_CAP_REG_0_64TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73649Up to 64TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0R/WVF_RESBAR_CAP_REG_0_128TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73665Up to 128TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_0_REGVF_RESBAR_CTRL_REG_0_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr739860x8R/W0x00000060PE0_DWC_pcie_ctl_DBI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REGResizable BAR0 Control Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVF_RESBAR_CTRL_REG_IDX_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73685BAR Index.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.200x0RRSVDP_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73693Reserved for future use.430x0RVF_RESBAR_CTRL_REG_NUM_BARSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73707Number of Resizeable BARs.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.750x3RVF_RESBAR_CTRL_REG_BAR_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73721BAR Size.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1380x00R/WRSVDP_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73729Reserved for future use.15140x0RVF_RESBAR_CTRL_REG_0_256TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73745Up to 256TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0R/WVF_RESBAR_CTRL_REG_0_512TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73761Up to 512TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0R/WVF_RESBAR_CTRL_REG_0_1PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73777Up to 1PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0R/WVF_RESBAR_CTRL_REG_0_2PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73793Up to 2PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0R/WVF_RESBAR_CTRL_REG_0_4PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73809Up to 4PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0R/WVF_RESBAR_CTRL_REG_0_8PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73825Up to 8PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0R/WVF_RESBAR_CTRL_REG_0_16PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73841Up to 16PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0R/WVF_RESBAR_CTRL_REG_0_32PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73857Up to 32PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0R/WVF_RESBAR_CTRL_REG_0_64PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73873Up to 64PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0R/WVF_RESBAR_CTRL_REG_0_128PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73889Up to 128PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0R/WVF_RESBAR_CTRL_REG_0_256PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73905Up to 256PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0R/WVF_RESBAR_CTRL_REG_0_512PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73921Up to 512PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0R/WVF_RESBAR_CTRL_REG_0_1EBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73937Up to 1EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0R/WVF_RESBAR_CTRL_REG_0_2EBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73953Up to 2EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0R/WVF_RESBAR_CTRL_REG_0_4EBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73969Up to 4EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0R/WVF_RESBAR_CTRL_REG_0_8EBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73985Up to 8EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_1_REGVF_RESBAR_CAP_REG_1_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr744480xCR/W0x00000010PE0_DWC_pcie_ctl_DBI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REGResizable BAR1 Capability Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr73999Reserved for future use.300x0RVF_RESBAR_CAP_REG_1_1MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74015Up to 1MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.440x1R/WVF_RESBAR_CAP_REG_1_2MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74031Up to 2MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.550x0R/WVF_RESBAR_CAP_REG_1_4MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74047Up to 4MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.660x0R/WVF_RESBAR_CAP_REG_1_8MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74063Up to 8MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.770x0R/WVF_RESBAR_CAP_REG_1_16MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74079Up to 16MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.880x0R/WVF_RESBAR_CAP_REG_1_32MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74095Up to 32MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.990x0R/WVF_RESBAR_CAP_REG_1_64MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74111Up to 64MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.10100x0R/WVF_RESBAR_CAP_REG_1_128MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74127Up to 128MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.11110x0R/WVF_RESBAR_CAP_REG_1_256MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74143Up to 256MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.12120x0R/WVF_RESBAR_CAP_REG_1_512MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74159Up to 512MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.13130x0R/WVF_RESBAR_CAP_REG_1_1GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74175Up to 1GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.14140x0R/WVF_RESBAR_CAP_REG_1_2GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74191Up to 2GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.15150x0R/WVF_RESBAR_CAP_REG_1_4GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74207Up to 4GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0R/WVF_RESBAR_CAP_REG_1_8GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74223Up to 8GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0R/WVF_RESBAR_CAP_REG_1_16GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74239Up to 16GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0R/WVF_RESBAR_CAP_REG_1_32GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74255Up to 32GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0R/WVF_RESBAR_CAP_REG_1_64GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74271Up to 64GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0R/WVF_RESBAR_CAP_REG_1_128GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74287Up to 128GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0R/WVF_RESBAR_CAP_REG_1_256GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74303Up to 256GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0R/WVF_RESBAR_CAP_REG_1_512GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74319Up to 512GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0R/WVF_RESBAR_CAP_REG_1_1TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74335Up to 1TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0R/WVF_RESBAR_CAP_REG_1_2TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74351Up to 2TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0R/WVF_RESBAR_CAP_REG_1_4TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74367Up to 4TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0R/WVF_RESBAR_CAP_REG_1_8TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74383Up to 8TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0R/WVF_RESBAR_CAP_REG_1_16TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74399Up to 16TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0R/WVF_RESBAR_CAP_REG_1_32TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74415Up to 32TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0R/WVF_RESBAR_CAP_REG_1_64TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74431Up to 64TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0R/WVF_RESBAR_CAP_REG_1_128TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74447Up to 128TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_1_REGVF_RESBAR_CTRL_REG_1_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr747680x10R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REGResizable BAR1 Control Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVF_RESBAR_CTRL_REG_IDX_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74467BAR Index.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.200x0RRSVDP_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74475Reserved for future use.430x0RVF_RESBAR_CTRL_REG_NUM_BARSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74489Number of Resizeable BARs.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.750x0RVF_RESBAR_CTRL_REG_BAR_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74503BAR Size.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1380x00R/WRSVDP_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74511Reserved for future use.15140x0RVF_RESBAR_CTRL_REG_1_256TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74527Up to 256TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0R/WVF_RESBAR_CTRL_REG_1_512TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74543Up to 512TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0R/WVF_RESBAR_CTRL_REG_1_1PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74559Up to 1PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0R/WVF_RESBAR_CTRL_REG_1_2PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74575Up to 2PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0R/WVF_RESBAR_CTRL_REG_1_4PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74591Up to 4PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0R/WVF_RESBAR_CTRL_REG_1_8PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74607Up to 8PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0R/WVF_RESBAR_CTRL_REG_1_16PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74623Up to 16PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0R/WVF_RESBAR_CTRL_REG_1_32PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74639Up to 32PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0R/WVF_RESBAR_CTRL_REG_1_64PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74655Up to 64PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0R/WVF_RESBAR_CTRL_REG_1_128PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74671Up to 128PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0R/WVF_RESBAR_CTRL_REG_1_256PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74687Up to 256PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0R/WVF_RESBAR_CTRL_REG_1_512PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74703Up to 512PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0R/WVF_RESBAR_CTRL_REG_1_1EBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74719Up to 1EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0R/WVF_RESBAR_CTRL_REG_1_2EBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74735Up to 2EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0R/WVF_RESBAR_CTRL_REG_1_4EBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74751Up to 4EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0R/WVF_RESBAR_CTRL_REG_1_8EBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74767Up to 8EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_2_REGVF_RESBAR_CAP_REG_2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr752300x14R/W0x00000010PE0_DWC_pcie_ctl_DBI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REGResizable BAR2 Capability Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74781Reserved for future use.300x0RVF_RESBAR_CAP_REG_2_1MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74797Up to 1MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.440x1R/WVF_RESBAR_CAP_REG_2_2MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74813Up to 2MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.550x0R/WVF_RESBAR_CAP_REG_2_4MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74829Up to 4MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.660x0R/WVF_RESBAR_CAP_REG_2_8MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74845Up to 8MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.770x0R/WVF_RESBAR_CAP_REG_2_16MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74861Up to 16MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.880x0R/WVF_RESBAR_CAP_REG_2_32MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74877Up to 32MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.990x0R/WVF_RESBAR_CAP_REG_2_64MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74893Up to 64MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.10100x0R/WVF_RESBAR_CAP_REG_2_128MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74909Up to 128MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.11110x0R/WVF_RESBAR_CAP_REG_2_256MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74925Up to 256MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.12120x0R/WVF_RESBAR_CAP_REG_2_512MBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74941Up to 512MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.13130x0R/WVF_RESBAR_CAP_REG_2_1GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74957Up to 1GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.14140x0R/WVF_RESBAR_CAP_REG_2_2GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74973Up to 2GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.15150x0R/WVF_RESBAR_CAP_REG_2_4GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr74989Up to 4GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0R/WVF_RESBAR_CAP_REG_2_8GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75005Up to 8GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0R/WVF_RESBAR_CAP_REG_2_16GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75021Up to 16GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0R/WVF_RESBAR_CAP_REG_2_32GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75037Up to 32GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0R/WVF_RESBAR_CAP_REG_2_64GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75053Up to 64GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0R/WVF_RESBAR_CAP_REG_2_128GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75069Up to 128GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0R/WVF_RESBAR_CAP_REG_2_256GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75085Up to 256GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0R/WVF_RESBAR_CAP_REG_2_512GBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75101Up to 512GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0R/WVF_RESBAR_CAP_REG_2_1TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75117Up to 1TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0R/WVF_RESBAR_CAP_REG_2_2TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75133Up to 2TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0R/WVF_RESBAR_CAP_REG_2_4TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75149Up to 4TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0R/WVF_RESBAR_CAP_REG_2_8TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75165Up to 8TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0R/WVF_RESBAR_CAP_REG_2_16TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75181Up to 16TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0R/WVF_RESBAR_CAP_REG_2_32TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75197Up to 32TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0R/WVF_RESBAR_CAP_REG_2_64TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75213Up to 64TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0R/WVF_RESBAR_CAP_REG_2_128TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75229Up to 128TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_2_REGVF_RESBAR_CTRL_REG_2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr755500x18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REGResizable BAR2 Control Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVF_RESBAR_CTRL_REG_IDX_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75249BAR Index.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.200x0RRSVDP_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75257Reserved for future use.430x0RVF_RESBAR_CTRL_REG_NUM_BARSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75271Number of Resizeable BARs.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.750x0RVF_RESBAR_CTRL_REG_BAR_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75285BAR Size.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1380x00R/WRSVDP_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75293Reserved for future use.15140x0RVF_RESBAR_CTRL_REG_2_256TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75309Up to 256TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0R/WVF_RESBAR_CTRL_REG_2_512TBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75325Up to 512TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0R/WVF_RESBAR_CTRL_REG_2_1PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75341Up to 1PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0R/WVF_RESBAR_CTRL_REG_2_2PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75357Up to 2PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0R/WVF_RESBAR_CTRL_REG_2_4PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75373Up to 4PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0R/WVF_RESBAR_CTRL_REG_2_8PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75389Up to 8PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0R/WVF_RESBAR_CTRL_REG_2_16PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75405Up to 16PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0R/WVF_RESBAR_CTRL_REG_2_32PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75421Up to 32PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0R/WVF_RESBAR_CTRL_REG_2_64PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75437Up to 64PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0R/WVF_RESBAR_CTRL_REG_2_128PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75453Up to 128PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0R/WVF_RESBAR_CTRL_REG_2_256PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75469Up to 256PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0R/WVF_RESBAR_CTRL_REG_2_512PBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75485Up to 512PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0R/WVF_RESBAR_CTRL_REG_2_1EBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75501Up to 1EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0R/WVF_RESBAR_CTRL_REG_2_2EBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75517Up to 2EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0R/WVF_RESBAR_CTRL_REG_2_4EBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75533Up to 4EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0R/WVF_RESBAR_CTRL_REG_2_8EBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75549Up to 8EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0R/WgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGICPF0_PORT_LOGICPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr813920x700R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGICPort LogicregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.ACK_LATENCY_TIMER_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VENDOR_SPEC_DLLP_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PORT_FORCE_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.ACK_F_ASPM_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PORT_LINK_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.LANE_SKEW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TIMER_CTRL_MAX_FUNC_NUM_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.SYMBOL_TIMER_FILTER_1_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.FILTER_MASK_2_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PL_DEBUG0_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PL_DEBUG1_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TX_P_FC_CREDIT_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TX_NP_FC_CREDIT_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TX_CPL_FC_CREDIT_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.QUEUE_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_1_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_2_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC0_P_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC0_NP_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC0_CPL_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC1_P_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC1_NP_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC1_CPL_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC2_P_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC2_NP_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC2_CPL_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC3_P_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC3_NP_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC3_CPL_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN2_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PHY_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PHY_CONTROL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TRGT_MAP_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_ADDR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_UPPER_ADDR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_MASK_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_MASK_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_MASK_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_MASK_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_MASK_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_MASK_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_MASK_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_MASK_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_GPIO_IO_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.CLOCK_GATING_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN3_RELATED_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN3_EQ_CONTROL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN3_EQ_FB_MODE_DIR_CHANGE_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.ORDER_RULE_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PIPE_LOOPBACK_CONTROL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MISC_CONTROL_1_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MULTI_LANE_CONTROL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PHY_INTEROP_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TRGT_CPL_LUT_DELETE_ENTRY_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.LINK_FLUSH_CONTROL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AMBA_ERROR_RESPONSE_DEFAULT_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AMBA_LINK_TIMEOUT_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AMBA_ORDERING_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_1_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_2_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_3_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_NUMBER_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_TYPE_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSIX_DOORBELL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSIX_RAM_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PL_LTR_LATENCY_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AUX_CLK_FREQ_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.L1_SUBSTATES_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.POWERDOWN_CTRL_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_1_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_2_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PIPE_RELATED_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.ACK_LATENCY_TIMER_OFFACK_LATENCY_TIMER_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr756080x0R/W0x0c23040bPE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFFAck Latency Timer and Replay Timer Register.falsefalsefalsefalseROUND_TRIP_LATENCY_TIME_LIMITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75583Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details, see "Ack Scheduling".You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.After reset, the controller updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed.The value is determined from Tables 3-7, 3-8, and 3-9 of the PCIe 3.0 specification.The limit must reflect the round trip latency from requester to completer.If there is a change in the payload size or link width, the controller will override any value that you have written to this register field, and reset the field back to the specification-defined value. It will not change the value in the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.1500x040bR/WREPLAY_TIME_LIMITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75607Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details, see "Transmit Replay".You can modify the effective timer limit with the TIMER_MOD_REPLAY_TIMER field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.After reset, the controller updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed.The value is determined from Tables 3-4, 3-5, and 3-6 of the PCIe 3.0 specification.If there is a change in the payload size or link speed, the controller will override any value that you have written to this register field, and reset the field back to the specification-defined value. It will not change the value in the TIMER_MOD_REPLAY_TIMER field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.31160x0c23R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VENDOR_SPEC_DLLP_OFFVENDOR_SPEC_DLLP_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr756300x4R/W0xffffffffPE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFFVendor Specific DLLP Register.falsefalsefalsefalseVENDOR_SPEC_DLLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75629Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP.Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register, then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to send the DLLP. - [7:0] = Type - [31:8] = Payload (24 bits)The dllp type is in bits [7:0] while the remainder is the vendor defined payload.Note: This register field is sticky.3100xffffffffR/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PORT_FORCE_OFFPORT_FORCE_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr757240x8R/W0x00800004PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_PORT_FORCE_OFFPort Force Link Register.falsefalsefalsefalseLINK_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75642Link Number. Not used for endpoint. Not used for M-PCIe.Note: This register field is sticky.700x04R/WFORCED_LTSSMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75655Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link).Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v.Note: This register field is sticky.1180x0R/WRSVDP_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75663Reserved for future use.14120x0RFORCE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75682Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state, and to force the controller to transmit a specific Link Command. Asserting this bit triggers the following actions: - Forces the LTSSM to the state specified by the Forced LTSSM State field. - Forces the controller to transmit the command specified by the Forced Link Command field.This is a self-clearing register field. Reading from this register field always returns a "0".15150x0WLINK_STATEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75694Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link).LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v.Note: This register field is sticky.21160x00R/WRSVDP_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75702Reserved for future use.22220x0RDO_DESKEW_FOR_SRISPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75715Use the transitions from TS2 to Logical Idle Symbol, SKP OS to Logical Idle Symbol, EIEOS to Logical Idle Symbol, and FTS Sequence to SKP OS to do deskew instead of using received SKP OS or TS1 to TS2 transition if DO_DESKEW_FOR_SRIS is set to 1.Note: This register field is sticky.23230x1R/WRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75723Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.ACK_F_ASPM_CTRL_OFFACK_F_ASPM_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr758510xCR/W0x1bc8c800PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFFAck Frequency and L0-L1 ASPM Control Register.falsefalsefalsefalseACK_FREQPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75752Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before scheduling an ACK DLLP. - 0: Indicates that this Ack Frequency Counter feature is turned off. The controller generates a low-priority ACK request for every TLP that it receives. The controller waits until the ACK Latency Timer expires, then converts the current low-priority ACK request to a high-priority ACK request and schedules the DLLP for transmission to the remote link partner. - 1-255: Indicates that the controller will schedule a high-priority ACK after receiving this number of TLPs. It might schedule the ACK before receiving this number of TLPs if the ACK Latency Timer expires, but never later.For a typical system, you do not have to modify the default setting. For more details, see "ACK/NAK Scheduling".Note: This register field is sticky.700x00R/WACK_N_FTSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75768N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255.The controller does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s.This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.1580xc8R/WCOMMON_CLK_N_FTSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75794Common Clock N_FTS. This is the N_FTS when common clock is used.The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. This field is only writable (sticky) when all of the following configuration parameter equations are true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCYThe controller does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 23160xc8RL0S_ENTRANCE_LATENCYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75811L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 usThis field is applicable to STALL while in L0 for M-PCIe.Note: This register field is sticky.26240x3R/WL1_ENTRANCE_LATENCYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75830L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 usNote: Programming this timer with a value greater that 32us has no effect unless extended sync is used, or all of the credits are infinite.Note: This register field is sticky.29270x3R/WENTER_ASPMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75842ASPM L1 Entry Control. - 1: Controller enters ASPM L1 after a period in which it has been idle. - 0: Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s.Note: This register field is sticky.30300x0R/WRSVDP_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75850Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PORT_LINK_CTRL_OFFPORT_LINK_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr760470x10R/W0x00000120PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFFPort Link Control Register.falsefalsefalsefalseVENDOR_SPECIFIC_DLLP_REQPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75868Vendor Specific DLLP Request. When software writes a '1' to this bit, the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF.Reading from this self-clearing register field always returns a '0'.000x0R/W1CSCRAMBLE_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75877Scramble Disable. Turns off data scrambling.Note: This register field is sticky.110x0R/WLOOPBACK_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75893Loopback Enable. Turns on loopback. For more details, see "Loopback".For M-PCIe, to force the master to enter Digital Loopback mode, you must set this field to "1" during Configuration.start state(initial discovery/configuration).M-PCIe doesn't support loopback mode from L0 state - only from Configuration.start.Note: This register field is sticky.220x0R/WRESET_ASSERTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75903Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only).Note: This register field is sticky.330x0R/WRSVDP_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75911Reserved for future use.440x0RDLL_LINK_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75922DLL Link Enable. Enables link initialization. When DLL Link Enable =0, the controller does not transmit InitFC DLLPs and does not establish a link.Note: This register field is sticky.550x1R/WLINK_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75931LINK_DISABLE is an internally reserved field. Do not use.Note: This register field is sticky.660x0R/WFAST_LINK_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75958Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster.The default scaling factor can be changed using the DEFAULT_FAST_LINK_SCALING_FACTOR parameter or through the FAST_LINK_SCALING_FACTOR field in the TIMER_CTRL_MAX_FUNC_NUM_OFF register.Fast Link Mode can also be activated by setting the diag_ctrl_bus[2] pin to '1'.For more details, see the "Fast Link Simulation Mode" section in the "Integrating the Controller with the PHY or Application RTL or Verification IP" chapter of the User Guide.For M-PCIe, this field also affects Remain Hibern8 Time, Minimum Activate Time, and RRAP timeout. If this bit is set to '1', tRRAPInitiatorResponse is set to 1.88 ms(60 ms/32).Note: This register field is sticky.770x0R/WLINK_RATEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75967LINK_RATE is an internally reserved field. Do not use.Note: This register field is sticky.1180x1R/WRSVDP_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75975Reserved for future use.15120x0RLINK_CAPABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr75999Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes. You must also change the value in the "Predetermined Number of Lanes" field of the "Link Width and Speed Change Control Register". For more information, see "How to Tie Off Unused Lanes". For information on upsizing and downsizing the link width, see "Link Establishment". - 000001: x1 - 000011: x2 - 000111: x4 - 001111: x8 - 011111: x16 - 111111: x32 (not supported)This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.2116R/W--23220x0rBEACON_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76008BEACON_ENABLE is an internally reserved field. Do not use.Note: This register field is sticky.24240x0R/WCORRUPT_LCRC_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76018CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use.Note: This register field is sticky.25250x0R/WEXTENDED_SYNCHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76028EXTENDED_SYNCH is an internally reserved field. Do not use.Note: This register field is sticky.26260x0R/WTRANSMIT_LANE_REVERSALE_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76038TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use.Note: This register field is sticky.27270x0R/WRSVDP_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76046Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.LANE_SKEW_OFFLANE_SKEW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr761280x14R/W0x3c000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_LANE_SKEW_OFFLane Skew Register.falsefalsefalsefalseINSERT_LANE_SKEWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76060INSERT_LANE_SKEW is an internally reserved field. Do not use.Note: This register field is sticky.2300x000000R/WFLOW_CTRL_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76070Flow Control Disable. Prevents the controller from sending FC DLLPs.Note: This register field is sticky.24240x0R/WACK_NAK_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76080Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs.Note: This register field is sticky.25250x0R/WELASTIC_BUFFER_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76091Selects Elasticity Buffer operating mode:0: Nominal Half Full Buffer mode1: Nominal Empty Buffer ModeNote: This register field is sticky.26260x1R/WIMPLEMENT_NUM_LANESPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76117Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanesThe number of lanes to be used when in Loopback Master. The number of lanes programmed must be equal to or less than the valid number of lanes set in LINK_CAPABLE field. You must configure this field before initiating Loopback by writing in the LOOPBACK_ENABLE field.The controller will transition from Loopback.Entry to Loopback.Active after receiving two consecutive TS1 Ordered Sets with the Loopback bit asserted on the implementation specific number of lanes configured in this field.Note: This register field is sticky.30270x7R/WDISABLE_LANE_TO_LANE_DESKEWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76127Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TIMER_CTRL_MAX_FUNC_NUM_OFFTIMER_CTRL_MAX_FUNC_NUM_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr762250x18R/W0x40000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFFTimer Control and Max Function Number Register.falsefalsefalsefalseMAX_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76142Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request).Note: This register field is sticky.700x00R/WRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76150Reserved for future use.1380x00RTIMER_MOD_REPLAY_TIMERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76170Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed, and in increments of 256 clock cycles at Gen3 speed. A value of "0" represents no modification to the timer limit. For more details, see the REPLAY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register.At Gen3 speed, the controller automatically changes the value of this field to DEFAULT_GEN3_REPLAY_ADJ.For M-PCIe, this field increases the time-out value for the replay timer in increments of 64 clock cycles at HS-Gear1, HS-Gear2, or HS-Gear3 speed.Note: This register field is sticky.1814R/WTIMER_MOD_ACK_NAKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76184Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of "0" represents no modification to the timer value. For more details, see the ROUND_TRIP_LATENCY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register.Note: This register field is sticky.23190x00R/WUPDATE_FREQ_TIMERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76194UPDATE_FREQ_TIMER is an internally reserved field. Do not use.Note: This register field is sticky.28240x00R/WFAST_LINK_SCALING_FACTORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76216Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us *a) - 1: Scaling Factor is 256 (1ms is 4us) - 2: Scaling Factor is 64 (1ms is 16us) - 3: Scaling Factor is 16 (1ms is 64us)Default is set by the hidden configuration parameter DEFAULT_FAST_LINK_SCALING_FACTOR which defaults to '0'.*a. When the LTSSM is in Config or L12 Entry State, 1ms timer is 2us, 2ms timer is 4us and 3ms timer is 6us.Not used for M-PCIe. Note: This register field is sticky.30290x2R/WRSVDP_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76224Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.SYMBOL_TIMER_FILTER_1_OFFSYMBOL_TIMER_FILTER_1_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr763820x1CR/W0x00000140PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFFSymbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.falsefalsefalsefalseSKP_INT_VALPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76264SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application must program this register accordingly. For example, if 1536 were programmed into this register (in a 250 MHz controller), then the controller actually transmits SKP ordered sets once every 1537 symbol times.The value programmed to this register is actually clock ticks and not symbol times. In a 125 MHz controller, programming the value programmed to this register should be scaled down by a factor of 2 (because one clock tick = two symbol times in this case).Note: This value is not used at Gen3 speed; the skip interval is hardcoded to 370 blocks.For M-PCIe configurations, if the 2K_PPM_DISABLED field in the M-PCIe Configuration Attribute is changed, then this field is changed automatically as follows. - 2K_PPM_DISABLED=1: 1280 / CX_NB - 2K_PPM_DISABLED=0: 228/CX_NBYou need to set this field again if necessary when 2K_PPM_DISABLED is changed.Note: This register field is sticky.1000x140R/WEIDLE_TIMERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76273EIDLE_TIMER is an internally reserved field. Do not use.Note: This register field is sticky.14110x0R/WDISABLE_FC_WD_TIMERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76282Disable FC Watchdog Timer.Note: This register field is sticky.15150x0R/WMASK_RADM_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76381Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.[31]: CX_FLT_MASK_RC_CFG_DISCARD - 0: For RADM RC filter to not allow CFG transaction being received - 1: For RADM RC filter to allow CFG transaction being received[30]: CX_FLT_MASK_RC_IO_DISCARD - 0: For RADM RC filter to not allow IO transaction being received - 1: For RADM RC filter to allow IO transaction being received[29]: CX_FLT_MASK_MSG_DROP - 0: Drop MSG TLP (except for Vendor MSG). Send decoded message on the SII. - 1: Do not Drop MSG (except for Vendor MSG). Send message TLPs to your application on TRGT1 and send decoded message on the SII. - The default for this bit is the inverse of FLT_DROP_MSG. That is, if FLT_DROP_MSG =1, then the default of this bit is "0" (drop message TLPs). This bit only controls message TLPs other than Vendor MSGs. Vendor MSGs are controlled by Filter Mask Register 2, bits [1:0]. The controller never passes ATS Invalidate messages to the SII interface regardless of this filter rule setting. The controller passes all ATS Invalidate messages to TRGT1 (or AXI bridge master), as they are too big for the SII.[28]: CX_FLT_MASK_CPL_ECRC_DISCARD - Only used when completion queue is advertised with infinite credits and is in store-and-forward mode. - 0: Discard completions with ECRC errors - 1: Allow completions with ECRC errors to be passed up - Reserved field for SW.[27]: CX_FLT_MASK_ECRC_DISCARD - 0: Discard TLPs with ECRC errors - 1: Allow TLPs with ECRC errors to be passed up[26]: CX_FLT_MASK_CPL_LEN_MATCH - 0: Enforce length match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err - 1: MASK length match for completions[25]: CX_FLT_MASK_CPL_ATTR_MATCH - 0: Enforce attribute match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask attribute match for completions[24]: CX_FLT_MASK_CPL_TC_MATCH - 0: Enforce Traffic Class match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Traffic Class match for completions[23]: CX_FLT_MASK_CPL_FUNC_MATCH - 0: Enforce function match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask function match for completions[22]: CX_FLT_MASK_CPL_REQID_MATCH - 0: Enforce Req. Id match for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Req. Id match for completions[21]: CX_FLT_MASK_CPL_TAGERR_MATCH - 0: Enforce Tag Error Rules for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Tag Error Rules for completions[20]: CX_FLT_MASK_LOCKED_RD_AS_UR - 0: Treat locked Read TLPs as UR for EP; Supported for RC - 1: Treat locked Read TLPs as Supported for EP; UR for RC[19]: CX_FLT_MASK_CFG_TYPE1_REQ_AS_UR - 0: Treat CFG type1 TLPs as UR for EP; Supported for RC - 1: Treat CFG type1 TLPs as Supported for EP; UR for RC - When CX_SRIOV_ENABLE is set then this bit is set to allow the filter to process Type 1 Config requests if the EP consumes more than one bus number.[18]: CX_FLT_MASK_UR_OUTSIDE_BAR - 0: Treat out-of-bar TLPs as UR - 1: Do not treat out-of-bar TLPs as UR[17]: CX_FLT_MASK_UR_POIS - 0: Treat poisoned request TLPs as UR - 1: Do not treat poisoned request TLPs as UR - The native controller always passes poisoned completions to your application except when you are using the DMA read channel.[16]: CX_FLT_MASK_UR_FUNC_MISMATCH - 0: Treat Function MisMatched TLPs as UR - 1: Do not treat Function MisMatched TLPs as URNote: This register field is sticky.31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.FILTER_MASK_2_OFFFILTER_MASK_2_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr764430x20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_FILTER_MASK_2_OFFFilter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.falsefalsefalsefalseMASK_RADM_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76442Filter Mask 2. This field modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.[31:10]: Reserved[9]: CX_FLT_MASK_CPL_IN_LUT_CHECK - 0: Disable masking of checking if the tag of CPL is registered in LUT - 1: Enable masking of checking if the tag of CPL is registered in LUT[8]: CX_FLT_MASK_POIS_ERROR_REPORTING - 0: Disable masking of error reporting for Poisoned TLPs - 1: Enable masking of error reporting for Poisoned TLPs[7]: CX_FLT_MASK_PRS_DROP - 0: Allow PRS message to pass through - 1: Drop PRS Messages silently - This bit is ignored when the CX_FLT_MASK_MSG_DROP bit in the MASK_RADM_1 field of the SYMBOL_TIMER_FILTER_1_OFF register is set to '1'.[6]: CX_FLT_UNMASK_TD - 0: Disable unmask TD bit if CX_STRIP_ECRC_ENABLE - 1: Enable unmask TD bit if CX_STRIP_ECRC_ENABLE[5]: CX_FLT_UNMASK_UR_POIS_TRGT0 - 0: Disable unmask CX_FLT_MASK_UR_POIS with TRGT0 destination - 1: Enable unmask CX_FLT_MASK_UR_POIS with TRGT0 destination[4]: CX_FLT_MASK_LN_VENMSG1_DROP - 0: Allow LN message to pass through - 1: Drop LN Messages silently[3]: CX_FLT_MASK_HANDLE_FLUSH - 0: Disable controller Filter to handle flush request - 1: Enable controller Filter to handle flush request[2]: CX_FLT_MASK_DABORT_4UCPL - 0: Enable DLLP abort for unexpected completion - 1: Do not enable DLLP abort for unexpected completion[1]: CX_FLT_MASK_VENMSG1_DROP - 0: Vendor MSG Type 1 dropped silently - 1: Vendor MSG Type 1 not dropped[0]: CX_FLT_MASK_VENMSG0_DROP - 0: Vendor MSG Type 0 dropped with UR error reporting - 1: Vendor MSG Type 0 not droppedNote: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFAMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr764770x24R/W0x00000001PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFAMBA Multiple Outbound Decomposed NP SubRequests Control Register.falsefalsefalsefalseOB_RD_SPLIT_BURST_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76468Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to "0" disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request. For more details, see "AXI Bridge Ordering" in the AXI chapter of the Databook.You should not clear this register unless your application master is requesting an amount of read data greater than Max_Read_Request_Size, and the remote device (or switch) is reordering completions that have different tags.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.000x1R/WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76476Reserved for future use.3110x00000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PL_DEBUG0_OFFPL_DEBUG0_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr764900x28RPE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_PL_DEBUG0_OFFDebug Register 0falsefalsefalsefalseDEB_REG_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76489The value on cxpl_debug_info[31:0].310RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PL_DEBUG1_OFFPL_DEBUG1_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr765030x2CRPE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_PL_DEBUG1_OFFDebug Register 1falsefalsefalsefalseDEB_REG_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76502The value on cxpl_debug_info[63:32].310RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TX_P_FC_CREDIT_STATUS_OFFTX_P_FC_CREDIT_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr765570x30R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFFTransmit Posted FC Credit StatusfalsefalsefalsefalseTX_P_DATA_FC_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76528Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].1500x0000RTX_P_HEADER_FC_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76549Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].27160x000RRSVDP_TX_P_FC_CREDIT_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76556Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TX_NP_FC_CREDIT_STATUS_OFFTX_NP_FC_CREDIT_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr766110x34R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFFTransmit Non-Posted FC Credit StatusfalsefalsefalsefalseTX_NP_DATA_FC_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76582Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].1500x0000RTX_NP_HEADER_FC_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76603Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].27160x000RRSVDP_TX_NP_FC_CREDIT_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76610Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TX_CPL_FC_CREDIT_STATUS_OFFTX_CPL_FC_CREDIT_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr766650x38R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFFTransmit Completion FC Credit StatusfalsefalsefalsefalseTX_CPL_DATA_FC_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76636Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].1500x0000RTX_CPL_HEADER_FC_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76657Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].27160x000RRSVDP_TX_CPL_FC_CREDIT_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76664Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.QUEUE_STATUS_OFFQUEUE_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr767690x3CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_QUEUE_STATUS_OFFQueue StatusfalsefalsefalsefalseRX_TLP_FC_CREDIT_NON_RETURNPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76682Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the link.000x0RTX_RETRY_BUFFER_NEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76693Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer.110x0RRX_QUEUE_NON_EMPTYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76704Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers.220x0RRX_QUEUE_OVERFLOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76715Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue.330x0R/W1CRSVDP_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76723Reserved for future use.1240x000RRX_SERIALIZATION_Q_NON_EMPTYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76734Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue.13130x0R--15140x0rTIMER_MOD_FLOW_CONTROLPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76747FC Latency Timer Override Value. When you set the "FC Latency Timer Override Enable" in this register, the value in this field will override the FC latency timer value that the controller calculates according to the PCIe specification. For more details, see "Flow Control".Note: This register field is sticky.28160x0000R/WRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76755Reserved for future use.30290x0RTIMER_MOD_FLOW_CONTROL_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76768FC Latency Timer Override Enable. When this bit is set, the value from the "FC Latency Timer Override Value" field in this register will override the FC latency timer value that the controller calculates according to the PCIe specification.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_1_OFFVC_TX_ARBI_1_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr768180x40R0x0000000fPE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFFVC Transmit Arbitration Register 1falsefalsefalsefalseWRR_WEIGHT_VC_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76784WRR Weight for VC0.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 700x0fRWRR_WEIGHT_VC_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76795WRR Weight for VC1.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 1580x00RWRR_WEIGHT_VC_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76806WRR Weight for VC2.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 23160x00RWRR_WEIGHT_VC_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76817WRR Weight for VC3.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_2_OFFVC_TX_ARBI_2_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr768670x44R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFFVC Transmit Arbitration Register 2falsefalsefalsefalseWRR_WEIGHT_VC_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76833WRR Weight for VC4.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 700x00RWRR_WEIGHT_VC_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76844WRR Weight for VC5.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 1580x00RWRR_WEIGHT_VC_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76855WRR Weight for VC6.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 23160x00RWRR_WEIGHT_VC_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76866WRR Weight for VC7.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC0_P_RX_Q_CTRL_OFFVC0_P_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr769710x48R/W0x462602e0PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFFSegmented-Buffer VC0 Posted Receive Queue Control.falsefalsefalsefalseVC0_P_DATA_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76884VC0 Posted Data Credits. The number of initial posted data credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x2e0R/WVC0_P_HEADER_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76898VC0 Posted Header Credits. The number of initial posted header credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76907Reserved.Note: This register field is sticky.20200x0R/WVC0_P_TLP_Q_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76916Reserved.Note: This register field is sticky.23210x1R/WVC0_P_HDR_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76926VC0 Scale Posted Header Credites.Note: This register field is sticky.25240x2R/WVC0_P_DATA_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76936VC0 Scale Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76945Reserved.Note: This register field is sticky.29280x0R/WTLP_TYPE_ORDERING_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76957TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-postedNote: This register field is sticky.30300x1R/WVC_ORDERING_RX_QPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76970VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues, used only in the segmented-buffer configuration: - 1: Strict ordering, higher numbered VCs have higher priority - 0: Round robinNote: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC0_NP_RX_Q_CTRL_OFFVC0_NP_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr770500x4CR/W0x06260060PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFFSegmented-Buffer VC0 Non-Posted Receive Queue Control.falsefalsefalsefalseVC0_NP_DATA_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr76988VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x060R/WVC0_NP_HEADER_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77002VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77011Reserved.Note: This register field is sticky.20200x0R/WVC0_NP_TLP_Q_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77020Reserved.Note: This register field is sticky.23210x1R/WVC0_NP_HDR_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77030VC0 Scale Non-Posted Header Credites.Note: This register field is sticky.25240x2R/WVC0_NP_DATA_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77040VC0 Scale Non-Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77049Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC0_CPL_RX_Q_CTRL_OFFVC0_CPL_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr771290x50R/W0x06200000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFFSegmented-Buffer VC0 Completion Receive Queue Control.falsefalsefalsefalseVC0_CPL_DATA_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77067VC0 Completion Data Credits. The number of initial Completion data credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x000R/WVC0_CPL_HEADER_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77081VC0 Completion Header Credits. The number of initial Completion header credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x00R/WRESERVED8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77090Reserved.Note: This register field is sticky.20200x0R/WVC0_CPL_TLP_Q_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77099Reserved.Note: This register field is sticky.23210x1R/WVC0_CPL_HDR_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77109VC0 Scale CPL Header Credites.Note: This register field is sticky.25240x2R/WVC0_CPL_DATA_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77119VC0 Scale CPL Data Credites.Note: This register field is sticky.27260x1R/WRESERVED9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77128Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC1_P_RX_Q_CTRL_OFFVC1_P_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr772290x54R/W0x462602e0PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFFSegmented-Buffer VC#i Posted Receive Queue Control.falsefalsefalsefalseVC1_P_DATA_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77146VC1 Posted Data Credits. The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x2e0R/WVC1_P_HEADER_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77160VC1 Posted Header Credits. The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED0_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77169Reserved.Note: This register field is sticky.20200x0R/WVC1_P_TLP_Q_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77178Reserved.Note: This register field is sticky.23210x1R/WVC1_P_HDR_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77188VC1 Scale Posted Header Credites.Note: This register field is sticky.25240x2R/WVC1_P_DATA_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77198VC1 Scale Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED1_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77207Reserved.Note: This register field is sticky.29280x0R/WTLP_TYPE_ORDERING_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77219TLP Type Ordering for VC#i. Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-postedNote: This register field is sticky.30300x1R/WRESERVED2_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77228Reserved.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC1_NP_RX_Q_CTRL_OFFVC1_NP_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr773080x58R/W0x06260001PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFFSegmented-Buffer VC#i Non-Posted Receive Queue Control.falsefalsefalsefalseVC1_NP_DATA_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77246VC#i Non-Posted Data Credits. The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x001R/WVC1_NP_HEADER_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77260VC#i Non-Posted Header Credits. The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED3_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77269Reserved.Note: This register field is sticky.20200x0R/WVC1_NP_TLP_Q_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77278Reserved.Note: This register field is sticky.23210x1R/WVC1_NP_HDR_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77288VC1 Scale Non-Posted Header Credites.Note: This register field is sticky.25240x2R/WVC1_NP_DATA_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77298VC1 Scale Non-Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED4_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77307Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC1_CPL_RX_Q_CTRL_OFFVC1_CPL_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr773870x5CR/W0x06200000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFFSegmented-Buffer VC#i Completion Receive Queue Control.falsefalsefalsefalseVC1_CPL_DATA_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77325VC#i Completion Data Credits. The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x000R/WVC1_CPL_HEADER_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77339VC#i Completion Header Credits. The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x00R/WRESERVED5_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77348Reserved.Note: This register field is sticky.20200x0R/WVC1_CPL_TLP_Q_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77357Reserved.Note: This register field is sticky.23210x1R/WVC1_CPL_HDR_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77367VC1 Scale CPL Header Credites.Note: This register field is sticky.25240x2R/WVC1_CPL_DATA_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77377VC1 Scale CPL Data Credites.Note: This register field is sticky.27260x1R/WRESERVED6_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77386Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC2_P_RX_Q_CTRL_OFFVC2_P_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr774870x60R/W0x462602e0PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFFSegmented-Buffer VC#i Posted Receive Queue Control.falsefalsefalsefalseVC2_P_DATA_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77404VC2 Posted Data Credits. The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x2e0R/WVC2_P_HEADER_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77418VC2 Posted Header Credits. The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED0_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77427Reserved.Note: This register field is sticky.20200x0R/WVC2_P_TLP_Q_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77436Reserved.Note: This register field is sticky.23210x1R/WVC2_P_HDR_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77446VC2 Scale Posted Header Credites.Note: This register field is sticky.25240x2R/WVC2_P_DATA_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77456VC2 Scale Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED1_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77465Reserved.Note: This register field is sticky.29280x0R/WTLP_TYPE_ORDERING_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77477TLP Type Ordering for VC#i. Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-postedNote: This register field is sticky.30300x1R/WRESERVED2_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77486Reserved.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC2_NP_RX_Q_CTRL_OFFVC2_NP_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr775660x64R/W0x06260001PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFFSegmented-Buffer VC#i Non-Posted Receive Queue Control.falsefalsefalsefalseVC2_NP_DATA_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77504VC#i Non-Posted Data Credits. The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x001R/WVC2_NP_HEADER_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77518VC#i Non-Posted Header Credits. The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED3_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77527Reserved.Note: This register field is sticky.20200x0R/WVC2_NP_TLP_Q_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77536Reserved.Note: This register field is sticky.23210x1R/WVC2_NP_HDR_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77546VC2 Scale Non-Posted Header Credites.Note: This register field is sticky.25240x2R/WVC2_NP_DATA_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77556VC2 Scale Non-Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED4_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77565Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC2_CPL_RX_Q_CTRL_OFFVC2_CPL_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr776450x68R/W0x06200000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFFSegmented-Buffer VC#i Completion Receive Queue Control.falsefalsefalsefalseVC2_CPL_DATA_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77583VC#i Completion Data Credits. The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x000R/WVC2_CPL_HEADER_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77597VC#i Completion Header Credits. The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x00R/WRESERVED5_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77606Reserved.Note: This register field is sticky.20200x0R/WVC2_CPL_TLP_Q_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77615Reserved.Note: This register field is sticky.23210x1R/WVC2_CPL_HDR_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77625VC2 Scale CPL Header Credites.Note: This register field is sticky.25240x2R/WVC2_CPL_DATA_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77635VC2 Scale CPL Data Credites.Note: This register field is sticky.27260x1R/WRESERVED6_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77644Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC3_P_RX_Q_CTRL_OFFVC3_P_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr777450x6CR/W0x462602e0PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFFSegmented-Buffer VC#i Posted Receive Queue Control.falsefalsefalsefalseVC3_P_DATA_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77662VC3 Posted Data Credits. The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x2e0R/WVC3_P_HEADER_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77676VC3 Posted Header Credits. The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED0_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77685Reserved.Note: This register field is sticky.20200x0R/WVC3_P_TLP_Q_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77694Reserved.Note: This register field is sticky.23210x1R/WVC3_P_HDR_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77704VC3 Scale Posted Header Credites.Note: This register field is sticky.25240x2R/WVC3_P_DATA_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77714VC3 Scale Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED1_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77723Reserved.Note: This register field is sticky.29280x0R/WTLP_TYPE_ORDERING_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77735TLP Type Ordering for VC#i. Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-postedNote: This register field is sticky.30300x1R/WRESERVED2_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77744Reserved.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC3_NP_RX_Q_CTRL_OFFVC3_NP_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr778240x70R/W0x06260001PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFFSegmented-Buffer VC#i Non-Posted Receive Queue Control.falsefalsefalsefalseVC3_NP_DATA_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77762VC#i Non-Posted Data Credits. The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x001R/WVC3_NP_HEADER_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77776VC#i Non-Posted Header Credits. The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED3_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77785Reserved.Note: This register field is sticky.20200x0R/WVC3_NP_TLP_Q_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77794Reserved.Note: This register field is sticky.23210x1R/WVC3_NP_HDR_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77804VC3 Scale Non-Posted Header Credites.Note: This register field is sticky.25240x2R/WVC3_NP_DATA_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77814VC3 Scale Non-Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED4_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77823Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC3_CPL_RX_Q_CTRL_OFFVC3_CPL_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr779030x74R/W0x06200000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFFSegmented-Buffer VC#i Completion Receive Queue Control.falsefalsefalsefalseVC3_CPL_DATA_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77841VC#i Completion Data Credits. The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x000R/WVC3_CPL_HEADER_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77855VC#i Completion Header Credits. The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x00R/WRESERVED5_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77864Reserved.Note: This register field is sticky.20200x0R/WVC3_CPL_TLP_Q_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77873Reserved.Note: This register field is sticky.23210x1R/WVC3_CPL_HDR_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77883VC3 Scale CPL Header Credites.Note: This register field is sticky.25240x2R/WVC3_CPL_DATA_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77893VC3 Scale CPL Data Credites.Note: This register field is sticky.27260x1R/WRESERVED6_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77902Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN2_CTRL_OFFGEN2_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr78187Link Width and Speed Change Control Register.0x10CR/W0x000108c8PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_GEN2_CTRL_OFFThis register is used to control various functions of the controller related to link training, lane reversal, and equalization.falsefalsefalsefalseFAST_TRAINING_SEQPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77930Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a low power state. The number should be provided by the PHY vendor. Do not set N_FTS to zero; doing so can cause the LTSSM to go into the recovery state when exiting from L0s.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.700xc8R/WNUM_OF_LANESPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_SETDWC_pcie_dbi_cpcie_usp_4x8.csr77970Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken" or "unused" lanes that detect a receiver. Indicates the number of lanes to check for exit from Electrical Idle in Polling.Active and L2.Idle. It is possible that the LTSSM might detect a receiver on a bad or broken lane during the Detect Substate. However, it is also possible that such a lane might also fail to exit Electrical Idle and therefore prevent a valid link from being configured. This value is referred to as the "Predetermined Number of Lanes" in section 4.2.6.2.1 of the PCI Express Base 3.0 Specification, revision 1.0. Encoding is as follows: - 0x01: 1 lane - 0x02: 2 lanes - 0x03: 3 lanes - ..When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes. You must also change the value in the "Link Mode Enable" field of PORT_LINK_CTRL_OFF. The value in this register is normally the same as the encoded value in PORT_LINK_CTRL_OFF. If you find that one of your used lanes is bad then you must reduce the value in this register. For more information, see "How to Tie Off Unused Lanes." For information on upsizing and downsizing the link width, see "Link Establishment."This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.1280x08R/WPRE_DET_LANEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78020Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect.This field is used to restrict the receiver detect procedure to a particular lane when the default detect and polling procedure performed on all lanes cannot be successful. A notable example of when it is useful to program this field to a value different from the default, is when a lane is asymmetrically broken, that is, it is detected in Detect LTSSM state but it cannot exit Electrical Idle in Polling LTSSM state.Note: This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.15130x0R/WfalsetruefalseLANE00x0Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/2-1 or CX_NL/4-1 or CX_NL/8-1, depending on which lane is detectedLANE10x1Connect logical Lane0 to physical lane 1LANE150x4Connect logical Lane0 to physical lane 15LANE30x2Connect logical Lane0 to physical lane 3LANE70x3connect logical lane0 to physical lane 7AUTO_LANE_FLIP_CTRL_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78038Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For more details, see the 'Lane Reversal' appendix in the Databook. This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.16160x1R/WDIRECT_SPEED_CHANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78071Directed Speed Change. Writing "1" to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed.When the speed change occurs, the controller will clear the contents of this field; and a read to this field by your software will return a "0".To manually initiate the speed change: - Write to LINK_CONTROL2_LINK_STATUS2_REG . PCIE_CAP_TARGET_LINK_SPEED in the local device - Deassert this field - Assert this fieldIf you set the default of this field using the DEFAULT_GEN2_SPEED_CHANGE configuration parameter to "1", then the speed change is initiated automatically after link up, and the controller clears the contents of this field. If you want to prevent this automatic speed change, then write a lower speed value to the Target Link Speed field of the Link Control 2 register (LINK_CONTROL2_LINK_STATUS2_OFF . PCIE_CAP_TARGET_LINK_SPEED) through the DBI before link up.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 17170x0R/WCONFIG_PHY_TX_CHANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78088Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low SwingThis field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.18180x0R/WCONFIG_TX_COMP_RXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78103Config Tx Compliance Receive Bit. When set to 1, signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to "1").This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.19190x0R/WSEL_DEEMPHASISPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78119Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dBThis field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.20200x0R/WGEN1_EI_INFERENCEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78137Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a "1" value on RxElecIdle instead of looking for a "0" on RxValid. If the PHY fails to deassert the RxValid signal in Recovery.Speed or Loopback.Active (because of corrupted EIOS for example), then EI cannot be inferred successfully in the controller by just detecting the condition RxValid=0. - 0: Use RxElecIdle signal to infer Electrical Idle - 1: Use RxValid signal to infer Electrical IdleNote: This register field is sticky.21210x0R/WRSVDP_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78145Reserved for future use.23220x0RLANE_UNDER_TESTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78161The Lane Under Test is the lane for Forced Lane Flip or for Loopback Eq. The value is from 0 to CX_NL. Only one lane is configured each time. The default of this field is the CX_DEFAULT_LANE_UNDER_TEST configuration parameter.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.27240x0R/W--29280x0rFORCE_LANE_FLIPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78178Enable to force the LANE_UNDER_TEST physical lane flips to logical lane 0. All the other physical lanes are turned off. The LINK_CAPABLE register must be set to 1 and only x1 link can be formed if the FORCE_LANE_FLIP register is set to 1.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.30300x0R/WRSVDP_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78186Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PHY_STATUS_OFFPHY_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr782110x110RPE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_PHY_STATUS_OFFPHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins.falsefalsefalsefalsePHY_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78210PHY Status. Data received directly from the phy_cfg_status bus.These is a GPIO register reflecting the values on the static phy_cfg_status input signals. The usage is left completely to the user and does not in any way influence controller functionality. You can use it for any static sideband status signalling requirements that you have for your PHY.This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.310RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PHY_CONTROL_OFFPHY_CONTROL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr782330x114R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_PHY_CONTROL_OFFPHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins.falsefalsefalsefalsePHY_CONTROLPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78232PHY Control. Data sent directly to the cfg_phy_control bus.These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller functionality. You can use it for any static sideband control signalling requirements that you have for your PHY.This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TRGT_MAP_CTRL_OFFTRGT_MAP_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr782920x11CR/W0x0000006fPE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFFProgrammable Target Map Control Register.falsefalsefalsefalseTARGET_MAP_PFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78246Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits.500x2fR/WTARGET_MAP_ROMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78257Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits.660x1R/W--1270x0rTARGET_MAP_RESERVED_13_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78269Reserved.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: R (sticky) 15130x0RTARGET_MAP_INDEXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78279The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits.20160x00R/WTARGET_MAP_RESERVED_21_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78291Reserved.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: R (sticky) 31210x000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_ADDR_OFFMSI_CTRL_ADDR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr783120x120R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFFIntegrated MSI Reception Module (iMRM) Address Register.falsefalsefalsefalseMSI_CTRL_ADDRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78311Integrated MSI Reception Module Address. System specified address for MSI memory write transaction termination.Within the AXI Bridge, every received Memory Write request is examined to see if it targets the MSI Address that has been specified in this register; and also to see if it satisfies the definition of an MSI interrupt request. When these conditions are satisfied the Memory Write request is marked as an MSI request.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_UPPER_ADDR_OFFMSI_CTRL_UPPER_ADDR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr783280x124R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFFIntegrated MSI Reception Module Upper Address Register.falsefalsefalsefalseMSI_CTRL_UPPER_ADDRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78327Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_EN_OFFMSI_CTRL_INT_0_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr783450x128R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_0_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78344MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_MASK_OFFMSI_CTRL_INT_0_MASK_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr783630x12CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_0_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78362MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_STATUS_OFFMSI_CTRL_INT_0_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr783810x130R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_0_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78380MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_EN_OFFMSI_CTRL_INT_1_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr783980x134R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_1_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78397MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_MASK_OFFMSI_CTRL_INT_1_MASK_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr784160x138R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_1_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78415MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_STATUS_OFFMSI_CTRL_INT_1_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr784340x13CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_1_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78433MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_EN_OFFMSI_CTRL_INT_2_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr784510x140R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_2_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78450MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_MASK_OFFMSI_CTRL_INT_2_MASK_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr784690x144R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_2_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78468MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_STATUS_OFFMSI_CTRL_INT_2_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr784870x148R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_2_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78486MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_EN_OFFMSI_CTRL_INT_3_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr785040x14CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_3_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78503MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_MASK_OFFMSI_CTRL_INT_3_MASK_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr785220x150R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_3_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78521MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_STATUS_OFFMSI_CTRL_INT_3_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr785400x154R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_3_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78539MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_EN_OFFMSI_CTRL_INT_4_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr785570x158R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_4_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78556MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_MASK_OFFMSI_CTRL_INT_4_MASK_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr785750x15CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_4_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78574MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_STATUS_OFFMSI_CTRL_INT_4_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr785930x160R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_4_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78592MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_EN_OFFMSI_CTRL_INT_5_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr786100x164R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_5_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78609MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_MASK_OFFMSI_CTRL_INT_5_MASK_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr786280x168R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_5_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78627MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_STATUS_OFFMSI_CTRL_INT_5_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr786460x16CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_5_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78645MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_EN_OFFMSI_CTRL_INT_6_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr786630x170R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_6_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78662MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_MASK_OFFMSI_CTRL_INT_6_MASK_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr786810x174R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_6_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78680MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_STATUS_OFFMSI_CTRL_INT_6_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr786990x178R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_6_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78698MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_EN_OFFMSI_CTRL_INT_7_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr787160x17CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_7_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78715MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_MASK_OFFMSI_CTRL_INT_7_MASK_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr787340x180R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_7_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78733MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_STATUS_OFFMSI_CTRL_INT_7_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr787520x184R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_7_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78751MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_GPIO_IO_OFFMSI_GPIO_IO_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr787660x188R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_GPIO_IO_OFFIntegrated MSI Reception Module General Purpose IO Register.falsefalsefalsefalseMSI_GPIO_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78765MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0]Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.CLOCK_GATING_CTRL_OFFCLOCK_GATING_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr788340x18CR/W0x00000003PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFFThis register enables you to disable dynamic clock gating. By default dynamic clock gating is on, allowing the controller to autonomously enable and disable its clocks. The clock gating is performed in the clock and reset module, DWC_pcie_clk_rst.v, and is initiated by the controllers clock enable signals. The following modules support dynamic clock gating: - AXI Bridge - RADMfalsefalsefalsefalseRADM_CLK_GATING_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78798RADM Clock Gating Enable. This register, if set, enables the RADM to autonomously enable and disable its clock. The DWC_pcie_clk_rst.v module provides the gated clock, radm_clk_g, to the RADM and is enabled when the controllers clock enable signal, en_radm_clk_g, is asserted. The RADM clock is a gated version of the controller clock, core_clk. The controller de-asserts en_radm_clk_g when there is no Rx traffic, Rx queues and pre/post-queue pipelines are empty, RADM completion LUT is empty, and there are no FLR actions pending. - 0: Disable - 1: Enable (default)Note: This register field is sticky.000x1R/WAXI_CLK_GATING_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78825AXI Clock Gating Enable. This register enables the AXI Bridge to autonomously enable and disable the AXI Master clock, the AXI Slave clock and the AXI DBI slave clock. The DWC_pcie_clk_rst.v module provides the gated clock, mstr_axi_aclk_gated, to the AXI Bridge and is enabled when the controllers clock enable signal, mstr_aclk_active, is asserted. For the AXI Slave this module provides the gated clock, slv_axi_aclk_gated, to the AXI Bridge and is enabled when the controllers clock enable signal, slv_aclk_active, is asserted. If the AXI DBI Slave is enabled (DBI_4SLAVE_POPULATED=1) the module provides the gated clock, dbi_axi_aclk_gated, to the AXI Bridge and is enabled when the controllers clock enable signal, dbi_aclk_active, is asserted. The controller de-asserts the clock enable signals when the respective AXI Master/Slave interfaces are idle. - 0: Disable - 1: Enable (default)Note: This register field is sticky.110x1R/WRSVDP_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78833Reserved for future use.3120x00000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN3_RELATED_OFFGEN3_RELATED_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr791790x190R/W0x00402001PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_GEN3_RELATED_OFFGen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the "Link Width and Speed Change Control Register" is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific "Directed Speed Change" field. The "Directed Speed Change" field in the "Link Width and Speed Change Control Register" is used to change to Gen2 or Gen3 speed. A speed change to Gen3 occurs if (1) the "Directed Speed Change" field is set to "1" and (2) the "Target Link Speed" field in the Link Control 2 Register is set to Gen3. Gen3 support is advertised by both sides of the link during link training.M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist.falsefalsefalsefalseGEN3_ZRXDC_NONCOMPLPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78869Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the following LTSSM states: Polling, Rx_L0s, L1, L2, and Disabled. - 0: The receiver complies with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher. - 1: The receiver does not comply with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rates.Note: This register field is sticky.000x1R/WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78877Reserved for future use.710x00RDISABLE_SCRAMBLER_GEN_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78892Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller (for example within the PHY).Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.880x0R/WEQ_PHASE_2_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78913Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description Note: This register field is sticky.990x0R/WEQ_EIEOS_CNTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78927Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.10100x0R/WEQ_REDOPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78947Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. The received presets or coefficients mismatch in Recovery.RcvrLock after Recovery EQ phases causes the EQ redo requests. If the EQ redo is infinite or you do not want eq requests and redo, setting this bit to 1 will stop the EQ requests and EQ redo so that the link can go ahead to L0 state for packet trasmissions.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.11110x0R/WRXEQ_PH01_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr78978Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be performed by the PHY. This bit is used during Virtex-7 Gen3 equalization. The programmable bits [RXEQ_PH01_EN, EQ_PHASE_2_3] can be used to obtain the following variations of the equalization procedure: - 00: Tx equalization only in phase 2/3 - 01: No Tx equalization, no Rx equalization - 10: Tx equalization in phase 2/3, Rx equalization in phase 0/1 - 11: No Tx equalization, Rx equalization in phase 0/1Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description Note: This register field is sticky.12120x0R/WRXEQ_RGRDLESS_RXTSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79004When set to '1', the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from remote partner. - 1: mac_phy_rxeqeval asserts after 500ns regardless of TS's received or not.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description Note: This register field is sticky.13130x1R/WRSVDP_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79012Reserved for future use.15140x0RGEN3_EQUALIZATION_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79026Equalization Disable. Disable equalization feature. This bit cannot be changed once the LTSSM starts link training.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.16160x0R/WGEN3_DLLP_XMT_DELAY_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79040DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.17170x0R/WGEN3_DC_BALANCE_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79052DC Balance Disable. Disable DC Balance feature.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.18180x0R/WRSVDP_19PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79060Reserved for future use.20190x0RAUTO_EQ_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79087Autonomous Equalization Disable. When the controller is in L0 state at Gen3 data rate and equalization was completed successfully in Autonomous EQ Mechanism, setting this bit in DSP will not direct the controller to Recovery state to perform Gen4 equalization. Link stays in Gen3 rate and DSP sends DLLPs to USP. If the bit is 0, DSP will block DLLPs and direct the link to perform Gen4 EQ in Autonomous Mechanism.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is RSVD. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description Note: This register field is sticky.21210x0R/WUSP_SEND_8GT_EQ_TS2_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79114Upstream Port Send 8GT/s or 16GT/s EQ TS2 Disable. The base spec defines that USP can optionally send 8GT or 16GT EQ TS2 and it means USP can set DSP TxPreset value in Gen4 or Gen5 Data Rate. If this register set to 0, USP sends 8GT or 16GT EQ TS2. If this register set to 1, USP does not send 8GT or 16GT EQ TS2. This applies to upstream ports only. No Function for downstream ports.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is RSVD. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. Value after reset in Gen4/Gen5 is 0x1.Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description Note: This register field is sticky.22220x1R/WGEN3_EQ_INVREQ_EVAL_DIFF_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79129Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.23230x0R/WRATE_SHADOW_SELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79170Rate Shadow Select. This register value decide the Data Rate of shadow register. - 00b: Gen3 Data Rate is selected for shadow register. - 01b: Gen4 Data Rate is selected for shadow register. - 10b: Gen5 Data Rate is selected for shadow register. - 11b: Reserved.The following shadow registers are controlled by this register. - GEN3_RELATED_OFF[9] EQ_PHASE_2_3 - GEN3_RELATED_OFF[12] RXEQ_PH01_EN - GEN3_RELATED_OFF[19] RE_EQ_REQUEST_ENABLE - GEN3_RELATED_OFF[21] AUTO_EQ_DISABLE - GEN3_RELATED_OFF[22] USP_SEND_8GT_EQ_TS2_DISABLE - GEN3_EQ_LOCAL_FS_LF_OFF[5:0] GEN3_EQ_LOCAL_LF - GEN3_EQ_LOCAL_FS_LF_OFF[11:6] GEN3_EQ_LOCAL_FS - GEN3_EQ_PSET_COEFF_MAP_0[5:0] GEN3_EQ_PRE_CURSOR_PSET - GEN3_EQ_PSET_COEFF_MAP_0[11:6] GEN3_EQ_CURSOR_PSET - GEN3_EQ_PSET_COEFF_MAP_0[17:12] GEN3_EQ_POSET_CURSOR_PSET - GEN3_EQ_CONTROL_OFF[3:0] GEN3_EQ_FB_MODE - GEN3_EQ_CONTROL_OFF[4] GEN3_EQ_PHASE23_EXIT_MODE - GEN3_EQ_CONTROL_OFF[5] GEN3_EQ_EVAL_2MS_DISABLE - GEN3_EQ_CONTROL_OFF[23:8] GEN3_EQ_PSET_REQ_VEC - GEN3_EQ_CONTROL_OFF[24] GEN3_EQ_FOM_INC_INITIAL_EVAL - GEN3_EQ_CONTROL_OFF[25] GEN3_EQ_PSET_REQ_AS_COEF - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[4:0] GEN3_EQ_FMDC_T_MIN_PHASE23 - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[9:5] GEN3_EQ_FMDC_N_EVALS - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[13:10] GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[17:14] GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTANote: This register field is sticky.25240x0R/WRSVDP_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79178Reserved for future use.31260x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN3_EQ_CONTROL_OFFGEN3_EQ_CONTROL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr794110x1A8R/W0x05039f71PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFFGen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP), or Phase3 in a downstream port (DSP).M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist.falsefalsefalsefalseGEN3_EQ_FB_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79207Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - .....: Reserved - 1111b: ReservedNote: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is a shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.300x1R/WGEN3_EQ_PHASE23_EXIT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79254Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3When optimal settings are not found then: - Equalization Phase 2 Successful status bit is not set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 0 - Equalization Phase 2 Successful status bit is set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 1 - Equalization Phase 2 Complete status bit is set in the "Link Status Register 2"For a DSP: Determine next LTSSM state from Phase3 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.RcvrLockWhen optimal settings are not found then: - Equalization Phase 3 Successful status bit is not set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 0 - Equalization Phase 3 Successful status bit is set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 1 - Equalization Phase 3 Complete status bit is set in the "Link Status Register 2"Note: GEN3_EQ_PHASE23_EXIT_MODE = 1 affects Direction Change feed back mode. EQ requests for Figure Of Merit mode complete before 24 ms timeout. Please see GEN3_EQ_PSET_REQ_VEC Register for more.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.440x1R/WGEN3_EQ_EVAL_2MS_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79278Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation, stop any attempt to modify the remote transmitter settings, Phase2 is terminated by the 24ms timeout - 1: ignore the 2ms timeout and continue as normal. This is used to support PHYs that require more than 2ms to respond to the assertion of RxEqEval.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.550x1R/WGEN3_LOWER_RATE_EQ_REDO_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79292Support EQ redo and lower rate change: - 0: not support - 1: supportNote: Gen3 and Gen4 share the same register bit and have the same feature.Note: This register field is sticky.660x1R/WRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79300Reserved for future use.770x0RGEN3_EQ_PSET_REQ_VECPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79355Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: "Preset=i" is requested and evaluated in EQ Master Phase. - 0000000000000000: No preset be requested and evaluated in EQ Master Phase - 000000xxxxxxxxx1: Preset 0 is requested and evaluated in EQ Master Phase - 000000xxxxxxxx1x: Preset 1 is requested and evaluated in EQ Master Phase - 000000xxxxxxx1xx: Preset 2 is requested and evaluated in EQ Master Phase - 000000xxxxxx1xxx: Preset 3 is requested and evaluated in EQ Master Phase - 000000xxxxx1xxxx: Preset 4 is requested and evaluated in EQ Master Phase - 000000xxxx1xxxxx: Preset 5 is requested and evaluated in EQ Master Phase - 000000xxx1xxxxxx: Preset 6 is requested and evaluated in EQ Master Phase - 000000xx1xxxxxxx: Preset 7 is requested and evaluated in EQ Master Phase - 000000x1xxxxxxxx: Preset 8 is requested and evaluated in EQ Master Phase - 00000x1xxxxxxxxx: Preset 9 is requested and evaluated in EQ Master Phase - 000001xxxxxxxxxx: Preset 10 is requested and evaluated in EQ Master Phase - All other encodings: ReservedNote: You must contact your PHY vendor to ensure 24 ms timeout does not occur in presets requests in EQ master phase, i.e., you must set a proper value to the GEN3_EQ_PSET_REQ_VEC register so that the EQ tunning for Figure of Merit in the EQ master phase completes before 24 ms timeout.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.2380x039fR/WGEN3_EQ_FOM_INC_INITIAL_EVALPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79375Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master, when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: IncludeNote: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.24240x1R/WGEN3_EQ_PSET_REQ_AS_COEFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79386GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use.Note: This register field is sticky.25250x0R/WGEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79402Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: requestNote: Gen3 and Gen4 share the same register bit and have the same feature.Note: This register field is sticky.26260x1R/WRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79410Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN3_EQ_FB_MODE_DIR_CHANGE_OFFGEN3_EQ_FB_MODE_DIR_CHANGE_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr795170x1ACR/W0x00000040PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFFGen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP), when you set the Feedback Mode in "Gen3 EQ Control Register" to "Direction Change." These fields allow control over the initial starting point for the search of optimal coefficient settings, and allow control over the criteria used to determine when the optimal settings have been achieved. The values are applied to all the lanes.falsefalsefalsefalseGEN3_EQ_FMDC_T_MIN_PHASE23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79442Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time, before starting to check for convergence of the coefficients.Allowed values 0,1,...,24.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.400x00R/WGEN3_EQ_FMDC_N_EVALSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79469Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found.Allowed range: 0,1,2,..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH.When set to 0, EQ Master is performed without sending any requests to the remote partner in Phase 2 for USP and Phase 3 for DSP. Therefore, the remote partner will not change its transmitter coefficients and will move to the next state.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.950x02R/WGEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79489Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth.Allowed range: 0,1,2,..15.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.13100x0R/WGEN3_EQ_FMDC_MAX_POST_CUSROR_DELTAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79508Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0,1,2,..15.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.17140x0R/WRSVDP_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79516Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.ORDER_RULE_CTRL_OFFORDER_RULE_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr795510x1B4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFFOrder Rule Control Register.falsefalsefalsefalseNP_PASS_PPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79531Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P700x00R/WCPL_PASS_PPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79542Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P1580x00R/WRSVDP_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79550Reserved for future use.31160x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PIPE_LOOPBACK_CONTROL_OFFPIPE_LOOPBACK_CONTROL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr796070x1B8R/W0x000000ffPE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFFPIPE Loopback Control Register.falsefalsefalsefalseLPBK_RXVALIDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79563LPBK_RXVALID is an internally reserved field. Do not use.Note: This register field is sticky.1500x00ffR/WRXSTATUS_LANEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79572RXSTATUS_LANE is an internally reserved field. Do not use.Note: This register field is sticky.21160x00R/WRSVDP_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79580Reserved for future use.23220x0RRXSTATUS_VALUEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79589RXSTATUS_VALUE is an internally reserved field. Do not use.2624WRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79597Reserved for future use.30270x0RPIPE_LOOPBACKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79606PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MISC_CONTROL_1_OFFMISC_CONTROL_1_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr798010x1BCR/W0x0007ff48PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MISC_CONTROL_1_OFFDBI Read-Only Write Enable Register.falsefalsefalsefalseDBI_RO_WR_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79625Write to RO Registers Using DBI. Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'.For more details, see "Writing to Read-Only Registers" in "Register Module, LBC, and DBI" section in the "Controller Operations" chapter of the Databook.Note: This register field is sticky.000x0R/WDEFAULT_TARGETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79646Default target for an IO or MEM request with UR/CA/CRS received. Based on the value of this field the controller either drops or forwards these requests to your application. - 0: The controller drops all incoming I/O or MEM requests (after corresponding error reporting). A completion with UR status is generated for non-posted requests. - 1: The controller forwards all incoming I/O or MEM requests with UR/CA/CRS status to your application.For more details, see "ECRC Handling" and "Request TLP Routing Rules" in "Receive Routing" section of the "Controller Operations" chapter of the Databook.Note: This register field is sticky.110x0R/WUR_CA_MASK_4_TRGT1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79660When this field is set to '1', the controller suppresses error logging, error message generation, and CPL generation for non-posted requests TLPs (with UR filtering status) forwarded to your application (that is, when DEFAULT_TARGET =1). For more details, see "Advanced Error Handling For Received TLPs" chapter of the Databook.Note: This register field is sticky.220x0R/WSIMPLIFIED_REPLAY_TIMERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79679Enables Simplified Replay Timer (Gen4). For more details, see "Transmit Replay" in "Transmit TLP Processing" section in the "Controller Operations" chapter of the Databook.Simplified Replay Timer can have the following Values: - A value from 24,000 to 31,000 Symbol Times when Extended Synch is 0b. - A value from 80,000 to 100,000 Symbol Times when Extended Synch is 1b.The Simplified Replay Timer value must not be changed while the link is in use.Note: This register field is sticky.330x1R/WDISABLE_AUTO_LTR_CLR_MSGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79697Disable the autonomous generation of LTR clear message in upstream port. This field can have the following values: - 0: Allow the autonomous generation of LTR clear message. - 1: Disable the autonomous generation of LTR clear message.For more details, see "Latency Tolerance Reporting (LTR) Message Generation[EP Mode]" in "Message Generation" section of the "Controller Operations" chapter of the Databook.Note: This register field is sticky.440x0R/WARI_DEVICE_NUMBERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79707When ARI is enabled, this field enables use of the device ID.Note: This register field is sticky.550x0R/WCPLQ_MNG_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79717This field enables the Completion Queue Management feature.Note: This register field is sticky.660x1R/WCFG_TLP_BYPASS_EN_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79736Setting of this field defines which field TARGET_ABOVE_CONFIG_LIMIT_REG or CONFIG_LIMIT_REG decides the destination of Configuration requests. This field can have the following values: - 0: Configuration TLPs are routed according to the setting of TARGET_ABOVE_CONFIG_LIMIT_REG - 1: Configuration TLPs are routed according to the setting of CONFIG_LIMIT_REGNote: When app_req_retry_en is asserted, the setting of this field is ignored.Note: This register field is sticky.770x0R/WCONFIG_LIMIT_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79757Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. - Configuration requests with an address less CONFIG_LIMIT_REG are directed to the CDM - Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of TARGET_ABOVE_CONFIG_LIMIT_REG field.Your application must set a proper value for this field based on your extended configuration registers. For more details, see the "CDM/ELBI Register Space Access Through CFG Request" in "Register Module, LBC, and DBI" section in the "Controller Operations" chapter of the Databook.Note: This register field is sticky.1780x3ffR/WTARGET_ABOVE_CONFIG_LIMIT_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79770Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of this field. This field can have the following values: - 1: ELBI - 2: TRGT1Note: This register field is sticky.19180x1R/WP2P_TRACK_CPL_TO_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79781Determines whether to enable Peer to Peer (P2P) error reporting. - 0: Disable P2P error reporting - 1: Enable P2P error reportingNote: This register field is sticky.20200x0R/WP2P_ERR_RPT_CTRLPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79792Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode. - 0: Do not track completion - 1: Track completionNote: This register field is sticky.21210x0R/WRSVDP_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79800Reserved for future use.31220x000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MULTI_LANE_CONTROL_OFFMULTI_LANE_CONTROL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr798750x1C0R/W0x00000080PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFFUpConfigure Multi-lane Control Register.Used when upsizing or downsizing the link width through Configuration state without bringing the link down.For more details, see the "Link Establishment" section in the "ControllerOperations" chapter of the Databook.falsefalsefalsefalseTARGET_LINK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79828Target Link Width.Values correspond to: - 6'b000000: Controller does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 - 6'b100000: x32This field is reserved (fixed to '0') for M-PCIe.500x00R/WDIRECT_LINK_WIDTH_CHANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79851Directed Link Width Change.The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in LINK_CONTROL_LINK_STATUS_REG is '0', the controller starts upconfigure or autonomous width downsizing (to the TARGET_LINK_WIDTH value) in the Configuration state. - If TARGET_LINK_WIDTH value is 0x0, the controller does not start upconfigure or autonomous width downsizing in the Configuration state.The controller self-clears this field when the controller accepts this request.This field is reserved (fixed to '0') for M-PCIe.660x0R/WUPCONFIGURE_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79866Upconfigure Support.The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state.This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.770x1R/WRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79874Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PHY_INTEROP_CTRL_OFFPHY_INTEROP_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr799910x1C4R/W0x00000a44PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFFPHY Interoperability Control Register.falsefalsefalsefalseRXSTANDBY_CONTROLPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79904Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. This field is reserved for internal use.You should not write to this field and change the default unless specifically instructed by Synopsys support. - [0]: Rx EIOS and subsequent T TX-IDLE-MIN - [1]: Rate Change - [2]: Inactive lane for upconfigure/downconfigure - [3]: PowerDown=P1orP2 - [4]: RxL0s.Idle - [5]: EI Infer in L0 - [6]: Execute RxStandby/RxStandbyStatus HandshakeThis field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.600x44R/WRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79912Reserved for future use.770x0RL1SUB_EXIT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79929L1 Exit Control Using phy_mac_pclkack_n. This field is reserved for internal use.You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller exits L1 without waiting for the PHY to assert phy_mac_pclkack_n. - 0: Controller waits for the PHY to assert phy_mac_pclkack_n before exiting L1.Note: This register field is sticky.880x0R/WL1_NOWAIT_P1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79950L1 entry control bit. This field is reserved for internal use.You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not wait for PHY to acknowledge transition to P1 before entering L1. - 0: Controller waits for the PHY to acknowledge transition to P1 before entering L1.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.990x1RL1_CLK_SELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79967L1 Clock control bit. This field is reserved for internal use.You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not request aux_clk switch and core_clk gating in L1. - 0: Controller requests aux_clk switch and core_clk gating in L1.Note: This register field is sticky.10100x0R/WP2NOBEACON_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79982P2.NoBeacon Enable bit. - 1: Controller drives P2.NoBeacon encoding for PHY power down state, when the link goes to L2. - 0: Controller drives P2 encoding for PHY power down state, when the link goes to L2.Note:This field is reserved (fixed to '0') if CX_P2NOBEACON_ENABLE is not set.Note: This register field is sticky.11110x1R/WRSVDP_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_SETDWC_pcie_dbi_cpcie_usp_4x8.csr79990Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TRGT_CPL_LUT_DELETE_ENTRY_OFFTRGT_CPL_LUT_DELETE_ENTRY_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr800270x1C8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFFTRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion because of an FLR or any other reason.Note:: The target completion LUT (and associated target completion timeout event) is watching for completions (from your application on XALI0/1/2 or AXI master read channel) corresponding to previously received non-posted requests from the PCIe wire.falsefalsefalsefalseLOOK_UP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80013This number selects one entry to delete of the TRGT_CPL_LUT.3000x00000000R/WDELETE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80026This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field.This is a self-clearing register field. Reading from this register field always returns a '0'.31310x0WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.LINK_FLUSH_CONTROL_OFFLINK_FLUSH_CONTROL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr800730x1CCR/W0xff000001PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFFLink Reset Request Flush Control Register.falsefalsefalsefalseAUTO_FLUSH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80055Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge.The flushing process is initiated if any of the following events occur: - Hot reset request. A downstream port (DSP) can "hot reset" an upstream port (USP) by sending two consecutive TS1 ordered sets with the hot reset bit asserted. - Warm (Soft) reset request. Generated when exiting from D3 to D0 and cfg_pm_no_soft_rst=0. - Link down reset request. A high to low transition on smlh_req_rst_not indicates the link has gone down and the controller is requesting a reset.If you disable automatic flushing, your application is responsible for resetting the PCIe controller and the AXI Bridge. For more details see "Warm and Hot Resets" section in the Architecture chapter of the Databook.Note: This register field is sticky.000x1R/WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80063Reserved for future use.2310x000000RRSVD_I_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80072This is an internally reserved field. Do not use.Note: This register field is sticky.31240xffR/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AMBA_ERROR_RESPONSE_DEFAULT_OFFAMBA_ERROR_RESPONSE_DEFAULT_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr80203AXI Bridge Slave Error Response Register.0x1D0R/W0x00009c00PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFFAXI Bridge Slave Error Response Register.falsefalsefalsefalseAMBA_ERROR_RESPONSE_GLOBALPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80102Global Slave Error Response Mapping. Determines the AXI slave response for all error scenarios on non-posted requests. For more details see "Error Handling" in the AXI chapter of the Databook.AHB: - 0: OKAY (with FFFF data for non-posted requests) and ignore the setting in bit [2] of this register. - 1: ERROR for normal link (data) accesses and look at bit [2] for other scenarios.AXI: - 0: OKAY (with FFFF data for non-posted requests) - 1: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping)The error response mapping is not applicable to Non-existent Vendor ID register reads.Note: This register field is sticky.000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80110Reserved for future use.110x0RAMBA_ERROR_RESPONSE_VENDORIDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80129Vendor ID Non-existent Slave Error Response Mapping. Determines the AXI slave response for errors on reads to non-existent Vendor ID register. For more details see "Error Handling" in the AXI chapter of the Databook.AHB: - 0: OKAY (with FFFF data). The controller ignores the setting in the bit when bit 0 of this register is '0'. - 1: ERRORAXI: - 0: OKAY (with FFFF data). - 1: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping)Note: This register field is sticky.220x0R/WAMBA_ERROR_RESPONSE_CRSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80151CRS Slave Error Response Mapping. Determines the AXI slave response for CRS completions. For more details see "Error Handling" in the AXI chapter of the Databook.AHB: - always returns OKAYAXI: - 00: OKAY - 01: OKAY with all FFFF_FFFF data for all CRS completions - 10: OKAY with FFFF_0001 data for CRS completions to vendor ID read requests, OKAY with FFFF_FFFF data for all other CRS completions - 11: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping)Note: This register field is sticky.430x0R/WRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80159Reserved for future use.950x00RAMBA_ERROR_RESPONSE_MAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80194AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses, slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is always mapped to OKAY. - [0] -- 0: UR (unsupported request) -> DECERR -- 1: UR (unsupported request) -> SLVERR - [1] -- 0: CRS (configuration retry status) -> DECERR -- 1: CRS (configuration retry status) -> SLVERR - [2] -- 0: CA (completer abort) -> DECERR -- 1: CA (completer abort) -> SLVERR - [3]: Reserved - [4]: Reserved - [5]: -- 0: Completion Timeout -> DECERR -- 1: Completion Timeout -> SLVERRThe AXI bridge internally drops (processes internally but not passed to your application) a completion that has been marked by the Rx filter as UC or MLF, and does not pass its status directly down to the slave interface. It waits for a timeout and then signals "Completion Timeout" to the slave interface.The controller sets the AXI slave read databus to 0xFFFF for all error responses.Note: This register field is sticky.15100x27R/WRSVDP_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80202Reserved for future use.31160x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AMBA_LINK_TIMEOUT_OFFAMBA_LINK_TIMEOUT_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr802500x1D4R/W0x00000032PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFFLink Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational, the controller starts a "flush" timer. The timeout value of the timer is set by this register. If the timer times out before the PCIe link is operational, the bridge TX request queues are flushed. For more details, see the "AXI Bridge Initialization, Clocking and Reset" section in the AXI chapter of the Databook.falsefalsefalsefalseLINK_TIMEOUT_PERIOD_DEFAULTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80231Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not transmitting any of these requests.The timer is clocked by core_clk. For an M-PCIe configuration: - Time unit of this field is 4 ms. - Margin of error for RateA clock is < 1%. - Margin of error for RateB clock is between 16% and 17%.Note: This register field is sticky.700x32R/WLINK_TIMEOUT_ENABLE_DEFAULTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80241Disable Flush. You can disable the flush feature by setting this field to "1".Note: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80249Reserved for future use.3190x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AMBA_ORDERING_CTRL_OFFAMBA_ORDERING_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr803600x1D8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFFAMBA Ordering Control.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80261Reserved for future use.000x0RAX_SNP_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80275AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR and WAW hazards at the remote link partner. For more details, see the "Optional Serialization of AXI Slave Non-posted Requests" section in the AXI chapter of the Databook.110x0R/WRSVDP_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80283Reserved for future use.220x0RAX_MSTR_ORDR_P_EVENT_SELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80327AXI Master Posted Ordering Event Selector. This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule, "NP must not pass P" at the AXI Master Interface.The AXI protocol does not support ordering between channels. Therefore, NP reads can pass P on your AXI bus fabric. This can result in an ordering violation when the read overtakes a P that is going to the same address. Therefore, the bridge master does not issue any NP requests until all outstanding P writes reach their destination. It does this by waiting for the all of the write responses on the B channel. This can affect the performance of the master read channel.For scenarios where the interconnect serializes the AXI master "AW", "W" and "AR" channels,you can increase the performance by reducing the need to wait until the complete Posted transaction has effectively reached the application slave. - 00: B'last event: wait for the all of the write responses on the B channel thereby ensuring that the complete Posted transaction has effectively reached the application slave (default). - 01: AW'last event: wait until the complete Posted transaction has left the AXI address channel at the bridge master. - 10: W'last event: wait until the complete Posted transaction has left the AXI data channel at the bridge master. - 11: ReservedNote 2: This setting will not affect: - MSI interrupt catcher and P data ordering. This is always driven by the B'last event. - DMA read engine TLP ordering. This is always driven by the B'last event. - NP write transactions which are always serialized with P write transactions.430x0R/WRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80335Reserved for future use.650x0RAX_MSTR_ZEROLREAD_FWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80351AXI Master Zero Length Read Forward to the application. The DW PCIe controller AXI bridge is able to terminate in order with the Posted transactions the zero length read, implementing the PCIe express flush semantics of the Posted transactions. - 0x0: The zero length Read is terminated at the DW PCIe AXI bridge master - 0x1: The zero length Read is forward to the application.770x0R/WRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80359Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_1_OFFCOHERENCY_CONTROL_1_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr803970x1E0R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFFACE Cache Coherency Control Register 1falsefalsefalsefalseCFG_MEMTYPE_VALUEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80374Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = PeripheralNote: This register field is sticky.000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80382Reserved for future use.110x0RCFG_MEMTYPE_BOUNDARY_LOW_ADDRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80396Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are "00". Addresses up to but not including this value are in the lower address space region; addresses equal or greater than this value are in the upper address space region.Note: This register field is sticky.3120x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_2_OFFCOHERENCY_CONTROL_2_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr804120x1E4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFFACE Cache Coherency Control Register 2falsefalsefalsefalseCFG_MEMTYPE_BOUNDARY_HIGH_ADDRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80411Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_3_OFFCOHERENCY_CONTROL_3_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr804700x1E8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFFACE Cache Coherency Control Register 3falsefalsefalsefalse--200x0rCFG_MSTR_ARCACHE_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80428Master Read CACHE Signal Behavior.Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE fieldNote: This register field is sticky.630x0R/W--1070x0rCFG_MSTR_AWCACHE_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80444Master Write CACHE Signal Behavior.Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE fieldNote: for message requests the value of mstr_awcache is always "0000" regardless of the value of this bitNote: This register field is sticky.14110x0R/W--18150x0rCFG_MSTR_ARCACHE_VALUEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80455Master Read CACHE Signal Value.Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'.Note: This register field is sticky.22190x0R/W--26230x0rCFG_MSTR_AWCACHE_VALUEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80469Master Write CACHE Signal Value.Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'.Note: not applicable to message requests; for message requests the value of mstr_awcache is always "0000"Note: This register field is sticky.30270x0R/W--31310x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_LOW_OFFAXI_MSTR_MSG_ADDR_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr805030x1F0R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFFLower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases, the third and fourth DWORDs of a message (Msg/MsgD) TLP header were delivered though the AXI master address bus (mstr_awaddr). These DWORDS are now supplied through the mstr_awmisc_info_hdr_34dw[63:0] output; and the value on mstr_awaddr is driven to the value you have programmed into the AXI_MSTR_MSG_ADDR_LOW_OFF and AXI_MSTR_MSG_ADDR_HIGH_OFF registers.falsefalsefalsefalseCFG_AXIMSTR_MSG_ADDR_LOW_RESERVEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80492Reserved for future use.Note: This register field is sticky.1100x000RCFG_AXIMSTR_MSG_ADDR_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80502Lower 20 bits of the programmable AXI address for Messages.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_HIGH_OFFAXI_MSTR_MSG_ADDR_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr805180x1F4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFFUpper 32 bits of the programmable AXI address where Messages coming from wire are mapped to.falsefalsefalsefalseCFG_AXIMSTR_MSG_ADDR_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80517Upper 32 bits of the programmable AXI address for Messages.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_NUMBER_OFFPCIE_VERSION_NUMBER_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr805430x1F8R0x3533302aPE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFFPCIe Controller IIP Release Version Number. The version number is given inhex format. You should convert each pair of hex characters to ASCII to interpret.Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x67612a2a which translates to ga**Using 4.70a-ea01 as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x65613031 which translates to ea01GA is a general release available on www.designware.comEA is an early release available on a per-customer basis.falsefalsefalsefalseVERSION_NUMBERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80542Version Number.3100x3533302aRregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_TYPE_OFFPCIE_VERSION_TYPE_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr805680x1FCR0x6c703038PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFFPCIe Controller IIP Release Version Type. The type is given inhex format. You should convert each pair of hex characters to ASCII to interpret.Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x67612a2a which translates to ga**Using 4.70a-ea01 as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x65613031 which translates to ea01GA is a general release available on www.designware.comEA is an early release available on a per-customer basis.falsefalsefalsefalseVERSION_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80567Version Type.3100x6c703038RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_LOW_OFFMSIX_ADDRESS_MATCH_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr806100x240R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFFMSI-X Address Match Low Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more details, see the Interrupts section in the "Controller Operations" chapter of the Databook. This register is only used in AXI configurations. When your local AXI application writes (MWr) to the address defined in this register (and MSIX_ADDRESS_MATCH_HIGH_OFF), the controller will load the MSIX_DOORBELL_OFF register with the contents of the MWr and subsequently create and send MSI-X TLPsfalsefalsefalsefalseMSIX_ADDRESS_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80590MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present.Note: This register field is sticky.000x0R/WMSIX_ADDRESS_MATCH_RESERVED_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80600Reserved.Note: This register field is sticky.110x0RMSIX_ADDRESS_MATCH_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80609MSI-X Address Match Low Address.Note: This register field is sticky.3120x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_HIGH_OFFMSIX_ADDRESS_MATCH_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr806320x244R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFFMSI-X Address Match High Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more details, see the Interrupts section in the "Controller Operations" chapter of the Databook. This register is only used in AXI configurations. When your local AXI application writes (MWr) to the address defined in this register (and MSIX_ADDRESS_MATCH_LOW_OFF), the controller will load the MSIX_DOORBELL_OFF register with the contents of the MWr and subsequently create and send MSI-X TLPsfalsefalsefalsefalseMSIX_ADDRESS_MATCH_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80631MSI-X Address Match High Address.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSIX_DOORBELL_OFFMSIX_DOORBELL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr807060x248W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSIX_DOORBELL_OFFMSI-X Doorbell Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more details, see the Interrupts section in the "Controller Operations" chapter of the Databook. - For AXI configurations: when your local application writes (MWr) to the address defined in MSIX_ADDRESS_MATCH_LOW_OFF, the controller will load this register with the contents of the MWr and subsequently create and send MSI-X TLPs. - For AHB configurations: the MSI-X Table RAM feature is not supported. - For non-AMBA configurations: when your local application writes to this register, the controller will create and send MSI-X TLPs.falsefalsefalsefalseMSIX_DOORBELL_VECTORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80657MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for.1000x000WMSIX_DOORBELL_RESERVED_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80664Reserved.11110x0WMSIX_DOORBELL_TCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80673MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X transaction with.14120x0WMSIX_DOORBELL_VF_ACTIVEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80682MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to generate the MSI-X transaction.15150x0WMSIX_DOORBELL_VFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80690MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction.23160x00WMSIX_DOORBELL_PFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80698MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X transaction.28240x00WMSIX_DOORBELL_RESERVED_29_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80705Reserved.31290x0WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSIX_RAM_CTRL_OFFMSIX_RAM_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr808440x24CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFFMSI-X RAM power mode and debug control register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more details, see the Interrupts section in the "Controller Operations" chapter of the Databook.falsefalsefalsefalseMSIX_RAM_CTRL_TABLE_DSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80724MSIX Table RAM Deep Sleep. Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode.Note: This register field is sticky.000x0R/WMSIX_RAM_CTRL_TABLE_SDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80735MSIX Table RAM Shut Down. Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode.Note: This register field is sticky.110x0R/WMSIX_RAM_CTRL_RESERVED_2_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80745Reserved.Note: This register field is sticky.720x00RMSIX_RAM_CTRL_PBA_DSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80756MSIX PBA RAM Deep Sleep. Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode.Note: This register field is sticky.880x0R/WMSIX_RAM_CTRL_PBA_SDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80767MSIX PBA RAM Shut Down. Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode.Note: This register field is sticky.990x0R/WMSIX_RAM_CTRL_RESERVED_10_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80777Reserved.Note: This register field is sticky.15100x00RMSIX_RAM_CTRL_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80793MSIX RAM Control Bypass. The bypass field, when set, disables the internal generation of low power signals for both RAMs.It is up to the application to ensure the RAMs are in the proper power state before trying to access them. Moreover, the application needs to observe all timing requirements of the RAM low power signals before trying to use the MSIX functionality.Note: This register field is sticky.16160x0R/WMSIX_RAM_CTRL_RESERVED_17_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80803Reserved.Note: This register field is sticky.23170x00RMSIX_RAM_CTRL_DBG_TABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80818MSIX Table RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the Table. Use can also use the dbg_table input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into the RAM and maps the entire table linearly from the base address of the BAR (indicated by the BIR) in function 0.Note: This register field is sticky.24240x0R/WMSIX_RAM_CTRL_DBG_PBAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80833MSIX PBA RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the PBA. Use can also use the dbg_pba input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into the RAM and maps the entire table linearly from the base address of the BAR (indicated by the BIR) in function 0.Note: This register field is sticky.25250x0R/WMSIX_RAM_CTRL_RESERVED_26_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80843Reserved.Note: This register field is sticky.31260x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PL_LTR_LATENCY_OFFPL_LTR_LATENCY_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr809380x430R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFFLTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port, the register fields capture the corresponding fields in the LTR messages that are transmitted by the port. For a downstream port, the register fields capture the corresponding fields in the LTR messages that are received by the port. The full content of the register is reflected on the app_ltr_latency[31:0] output.falsefalsefalsefalseSNOOP_LATENCY_VALUEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80866Snoop Latency Value.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R/W 900x000R/WSNOOP_LATENCY_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80877Snoop Latency Scale.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R/W 12100x0R/WRSVDP_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80885Reserved for future use.14130x0RSNOOP_LATENCY_REQUIREPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80896Snoop Latency Requirement.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R/W 15150x0R/WNO_SNOOP_LATENCY_VALUEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80907No Snoop Latency Value.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R/W 25160x000R/WNO_SNOOP_LATENCY_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80918No Snoop Latency Scale.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R/W 28260x0R/WRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80926Reserved for future use.30290x0RNO_SNOOP_LATENCY_REQUIREPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80937No Snoop Latency Requirement.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AUX_CLK_FREQ_OFFAUX_CLK_FREQ_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr809730x440R/W0x00000018PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFFAuxiliary Clock Frequency Control Register.falsefalsefalsefalseAUX_CLK_FREQPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80964The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk.Frequencies lower than 1 MHz are possible but with a loss of accuracy in the time counted.If the actual frequency (f) of aux_clk does not exactly match the programmed frequency (f_prog), then there is an error in the time counted by the controller that can be expressed in percentage as: err% = (f_prog/f-1)*100. For example if f=2.5 MHz and f_prog=3 MHz, then err% =(3/2.5-1)*100 =20%, meaning that the time counted by the controller on aux_clk will be 20% greater than the time in us programmed in the corresponding time register (for example T_POWER_ON).Note: This register field is sticky.900x018R/WRSVDP_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80972Reserved for future use.31100x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.L1_SUBSTATES_OFFL1_SUBSTATES_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr810330x444R/W0x000000d2PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_L1_SUBSTATES_OFFL1 Substates Timing Register.falsefalsefalsefalseL1SUB_T_POWER_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80986Duration (in 1us units) of L1.2.Entry. The actual timeout value will be L1SUB_T_POWER_OFF + 1. Range is 0.3.Note: This register field is sticky.100x2R/WL1SUB_T_L1_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr80996Duration (in 1us units) of L1.2. The actual timeout value will be L1SUB_T_L1_2 + 1. Range is 0.15.Note: This register field is sticky.520x4R/WL1SUB_T_PCLKACKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81009Max delay (in 1us units) between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this time the request is aborted.The actual timeout value will be L1SUB_T_PCLKACK + 1. Range is 0..3Note: This register field is sticky.760x3R/WL1SUB_LOW_POWER_CLOCK_SWITCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81024If this bit is set to 1'b1 the reference clock will be running regardless of the CLKREQ# setting. If this bit is set to 1'b0 the reference clock may be gated off when CLKREQ# is de-asserted. If the bit is set to 1'b1 the controller will delay the switching of aux_clk to the slow platform clock until it detects that the link partner has de-asserted CLKREQ#.Note: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81032Reserved for future use.3190x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.POWERDOWN_CTRL_STATUS_OFFPOWERDOWN_CTRL_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr810940x448R/W0x00000220PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFFPowerdown Control and Status Register.falsefalsefalsefalsePOWERDOWN_FORCEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81052This field is a one shot field. Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake regardless of whether the PHY has returned Phystatus. This field could be used for debug purposes in event that the P2 Powerdown transition does not complete. It will allow the controller to proceed with the transition to the P1 Powerdown state. This field always reads back as 1'b0.000x0WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81060Reserved for future use.310x0RPOWERDOWN_MAC_POWERDOWNPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81071This field represents the Powerdown value driven by the controller to the PHY.740x2RPOWERDOWN_PHY_POWERDOWNPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81085This field represents the Powerdown value that has been acknowledged by the PHY. It is updated with the value of Powerdown driven by the controller, when the PHY has returned the Phystatus acknowledgment for the Powerdown transition.1180x2RRSVDP_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81093Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_1_OFFGEN4_LANE_MARGINING_1_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr811820x480R/W0x05201409PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFFGen4 Lane Margining 1 Register.falsefalsefalsefalseMARGINING_NUM_TIMING_STEPSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81110M(NumTimingSteps) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.500x09R/WRSVDP_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81118Reserved for future use.760x0RMARGINING_MAX_TIMING_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81131M(MaxTimingOffset) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.1380x14R/WRSVDP_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81139Reserved for future use.15140x0RMARGINING_NUM_VOLTAGE_STEPSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81152M(NumVoltageSteps) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.22160x20R/WRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81160Reserved for future use.23230x0RMARGINING_MAX_VOLTAGE_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81173M(MaxVoltageOffset) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.29240x05R/WRSVDP_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81181Reserved for future use.31300x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_2_OFFGEN4_LANE_MARGINING_2_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr813290x484R/W0x060f0000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFFGen4 Lane Margining 2 Register.falsefalsefalsefalseMARGINING_SAMPLE_RATE_VOLTAGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81201M(SamplingRateVoltage) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This value is not used when MARGINING_IND_ERROR_SAMPLER is 0b. The M(SamplingRateVoltage) is fixed to 63 internally.Note: This register field is sticky.500x00R/WRSVDP_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81209Reserved for future use.760x0RMARGINING_SAMPLE_RATE_TIMINGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81225M(SamplingRateTiming) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter , see the PCI Express Base Specification 4.0.Note: This value is not used when MARGINING_IND_ERROR_SAMPLER is 0b. The M(SamplingRateTiming) is fixed to 63 internally.Note: This register field is sticky.1380x00R/WRSVDP_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81233Reserved for future use.15140x0RMARGINING_MAXLANESPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81246M(MaxLanes) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.20160x0fR/WRSVDP_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81254Reserved for future use.23210x0RMARGINING_VOLTAGE_SUPPORTEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81267M(VoltageSupported) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.24240x0R/WMARGINING_IND_UP_DOWN_VOLTAGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81280M(IndUpDownVoltage) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.25250x1R/WMARGINING_IND_LEFT_RIGHT_TIMINGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81293M(IndLeftRightTiming) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.26260x1R/WMARGINING_SAMPLE_REPORTING_METHODPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81307M(SampleReportingMethod) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.27270x0R/WMARGINING_IND_ERROR_SAMPLERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81320M(IndErrorSampler) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.28280x0R/WRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81328Reserved for future use.30290x0R--31310x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PIPE_RELATED_OFFPIPE_RELATED_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr813910x490R/W0x00000022PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_PIPE_RELATED_OFFPIPE Related Register.This register controls the pipe's capabitity, control, and status parameters.falsefalsefalsefalseRX_MESSAGE_BUS_WRITE_BUFFER_DEPTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81349RXMessageBusWriteBufferDepth defined in the PIPE Specification.Indicates the number of write buffer entries that the PHY has implemented to receive writes from the controller.If the value is less than 2 for PIPE 5.1.1 or 1 for PIPE 4.4.1, the controller issues only write_commited commands, never write_uncommitted.Note: This register field is sticky.300x2R/WTX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81363TXMessageBusMinWriteBufferDepth defined in the PIPE Specification.Indicates the minimum number of write buffer entries that the PHY expects the controller to implement to receive writes from it.Note: This register field is sticky.740x2RPIPE_GARBAGE_DATA_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81382PIPE Garbage Data Mode. - 0: PIPE Spec compliant mode: The MAC discards any symbols received after the electrical idle ordered-set until RxValid is deasserted. - 1: Special PHY Support mode: The MAC discards any symbols received after the electrical idle ordered-set until when any of the following three conditions are true: -- RxValid is deasserted -- a valid RxStartBlock is received at 128b/130b encoding -- a valid COM symbol is received at 8b/10b encodingNote: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81390Reserved for future use.3190x000000RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR_DBI2PF0_TYPE0_HDR_DBI2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr817390x100000R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE0_HDR_DBI2DBI2 Shadow Block: PF PCI-Compatible Configuration Space Header Type0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR_DBI2.BAR0_MASK_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR_DBI2.BAR1_MASK_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR_DBI2.BAR2_MASK_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR_DBI2.BAR3_MASK_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR_DBI2.BAR4_MASK_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR_DBI2.BAR5_MASK_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR_DBI2.EXP_ROM_BAR_MASK_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR_DBI2.BAR0_MASK_REGBAR0_MASK_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr814470x10W0xffffffffPE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REGBAR0 Mask Register. This register is the mask for BAR0_REG. If implemented, it exists as a shadow register at the BAR0_REG address.Normally, the BAR masks are used for indicating the amount of address space that each BAR requests from host software. The BAR masks determine which bits in each BAR are non-writable by host software, which determines the size of the address space claimed by each BAR. The BAR mask values indicate the range of low-order bits, in each implemented BAR, not to use for address matching. The BAR mask value also indicates the range of low-order bits in the BAR that cannot be written from the host. The application can write to all BAR bits to allow setting of memory, I/O, and other standard BAR options.Your local CPU can change the mask at runtime using the DBI. The mask register is invisible to the PCIe wire but visible to your local CPU through the DBI. You cannot read the mask register but you can write to it. It is accessed by asserting dbi_cs2 and dbi_cs. If you only assert dbi_cs then you will access the BAR which is the primary register at that location. Use CS2 instead of dbi_cs2 when you are using the AHB/AXI bridge.falsefalsefalsefalsePCI_TYPE0_BAR0_ENABLEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81432BAR0 Mask Enabled.Note: This register field is sticky.000x1WPCI_TYPE0_BAR0_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81446BAR0 Mask.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: W (sticky)Note: This register field is sticky.3110x7fffffffWregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR_DBI2.BAR1_MASK_REGBAR1_MASK_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr814970x14W0xfffffffePE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REGBAR1 Mask Register. This register is the mask for BAR1_REG. If implemented, it exists as a shadow register at the BAR1_REG address.Normally, the BAR masks are used for indicating the amount of address space that each BAR requests from host software. The BAR masks determine which bits in each BAR are non-writable by host software, which determines the size of the address space claimed by each BAR. The BAR mask values indicate the range of low-order bits, in each implemented BAR, not to use for address matching. The BAR mask value also indicates the range of low-order bits in the BAR that cannot be written from the host. The application can write to all BAR bits to allow setting of memory, I/O, and other standard BAR options.Your local CPU can change the mask at runtime using the DBI. The mask register is invisible to the PCIe wire but visible to your local CPU through the DBI. You cannot read the mask register but you can write to it. It is accessed by asserting dbi_cs2 and dbi_cs. If you only assert dbi_cs then you will access the BAR which is the primary register at that location. Use CS2 instead of dbi_cs2 when you are using the AHB/AXI bridge.falsefalsefalsefalsePCI_TYPE0_BAR1_ENABLEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81482BAR1 Mask Enabled.Note: This register field is sticky.000x0WPCI_TYPE0_BAR1_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81496BAR1 Mask.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: W (sticky)Note: This register field is sticky.3110x7fffffffWregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR_DBI2.BAR2_MASK_REGBAR2_MASK_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr815470x18W0xffffffffPE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REGBAR2 Mask Register. This register is the mask for BAR2_REG. If implemented, it exists as a shadow register at the BAR2_REG address.Normally, the BAR masks are used for indicating the amount of address space that each BAR requests from host software. The BAR masks determine which bits in each BAR are non-writable by host software, which determines the size of the address space claimed by each BAR. The BAR mask values indicate the range of low-order bits, in each implemented BAR, not to use for address matching. The BAR mask value also indicates the range of low-order bits in the BAR that cannot be written from the host. The application can write to all BAR bits to allow setting of memory, I/O, and other standard BAR options.Your local CPU can change the mask at runtime using the DBI. The mask register is invisible to the PCIe wire but visible to your local CPU through the DBI. You cannot read the mask register but you can write to it. It is accessed by asserting dbi_cs2 and dbi_cs. If you only assert dbi_cs then you will access the BAR which is the primary register at that location. Use CS2 instead of dbi_cs2 when you are using the AHB/AXI bridge.falsefalsefalsefalsePCI_TYPE0_BAR2_ENABLEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81532BAR2 Mask Enabled.Note: This register field is sticky.000x1WPCI_TYPE0_BAR2_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81546BAR2 Mask.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: W (sticky)Note: This register field is sticky.3110x7fffffffWregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR_DBI2.BAR3_MASK_REGBAR3_MASK_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr815970x1CW0xfffffffePE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REGBAR3 Mask Register. This register is the mask for BAR3_REG. If implemented, it exists as a shadow register at the BAR3_REG address.Normally, the BAR masks are used for indicating the amount of address space that each BAR requests from host software. The BAR masks determine which bits in each BAR are non-writable by host software, which determines the size of the address space claimed by each BAR. The BAR mask values indicate the range of low-order bits, in each implemented BAR, not to use for address matching. The BAR mask value also indicates the range of low-order bits in the BAR that cannot be written from the host. The application can write to all BAR bits to allow setting of memory, I/O, and other standard BAR options.Your local CPU can change the mask at runtime using the DBI. The mask register is invisible to the PCIe wire but visible to your local CPU through the DBI. You cannot read the mask register but you can write to it. It is accessed by asserting dbi_cs2 and dbi_cs. If you only assert dbi_cs then you will access the BAR which is the primary register at that location. Use CS2 instead of dbi_cs2 when you are using the AHB/AXI bridge.falsefalsefalsefalsePCI_TYPE0_BAR3_ENABLEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81582BAR3 Mask Enabled.Note: This register field is sticky.000x0WPCI_TYPE0_BAR3_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81596BAR3 Mask.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: W (sticky)Note: This register field is sticky.3110x7fffffffWregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR_DBI2.BAR4_MASK_REGBAR4_MASK_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr816470x20W0xffffffffPE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REGBAR4 Mask Register. This register is the mask for BAR4_REG. If implemented, it exists as a shadow register at the BAR4_REG address.Normally, the BAR masks are used for indicating the amount of address space that each BAR requests from host software. The BAR masks determine which bits in each BAR are non-writable by host software, which determines the size of the address space claimed by each BAR. The BAR mask values indicate the range of low-order bits, in each implemented BAR, not to use for address matching. The BAR mask value also indicates the range of low-order bits in the BAR that cannot be written from the host. The application can write to all BAR bits to allow setting of memory, I/O, and other standard BAR options.Your local CPU can change the mask at runtime using the DBI. The mask register is invisible to the PCIe wire but visible to your local CPU through the DBI. You cannot read the mask register but you can write to it. It is accessed by asserting dbi_cs2 and dbi_cs. If you only assert dbi_cs then you will access the BAR which is the primary register at that location. Use CS2 instead of dbi_cs2 when you are using the AHB/AXI bridge.falsefalsefalsefalsePCI_TYPE0_BAR4_ENABLEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81632BAR4 Mask Enabled.Note: This register field is sticky.000x1WPCI_TYPE0_BAR4_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81646BAR4 Mask.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: W (sticky)Note: This register field is sticky.3110x7fffffffWregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR_DBI2.BAR5_MASK_REGBAR5_MASK_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr816970x24W0xfffffffePE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REGBAR5 Mask Register. This register is the mask for BAR5_REG. If implemented, it exists as a shadow register at the BAR5_REG address.Normally, the BAR masks are used for indicating the amount of address space that each BAR requests from host software. The BAR masks determine which bits in each BAR are non-writable by host software, which determines the size of the address space claimed by each BAR. The BAR mask values indicate the range of low-order bits, in each implemented BAR, not to use for address matching. The BAR mask value also indicates the range of low-order bits in the BAR that cannot be written from the host. The application can write to all BAR bits to allow setting of memory, I/O, and other standard BAR options.Your local CPU can change the mask at runtime using the DBI. The mask register is invisible to the PCIe wire but visible to your local CPU through the DBI. You cannot read the mask register but you can write to it. It is accessed by asserting dbi_cs2 and dbi_cs. If you only assert dbi_cs then you will access the BAR which is the primary register at that location. Use CS2 instead of dbi_cs2 when you are using the AHB/AXI bridge.falsefalsefalsefalsePCI_TYPE0_BAR5_ENABLEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81682BAR5 Mask Enabled.Note: This register field is sticky.000x0WPCI_TYPE0_BAR5_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81696BAR5 Mask.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: W (sticky)Note: This register field is sticky.3110x7fffffffWregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE0_HDR_DBI2.EXP_ROM_BAR_MASK_REGEXP_ROM_BAR_MASK_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr817380x30R/W0x0001ffffPE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REGExpansion ROM BAR Mask Register. This register is the mask for EXP_ROM_BASE_ADDR_REG register. If implemented, it exists as a shadow register at EXP_ROM_BAR_MASK_REG address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to this register.falsefalsefalsefalseROM_BAR_ENABLEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81721Expansion ROM Bar Mask Register Enabled.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if ROM_MASK_WRITABLE then WNote: This register field is sticky.000x1WROM_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE0_HDR_DBI2_EXP_ROM_BAR_MASK_REG_ROM_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81737Expansion ROM Mask.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if ROM_BAR_ENABLED && ROM_MASK_WRITABLE then WNote: This register field is sticky.3110x0000ffffRmemoryPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP_DBI2PF0_PCIE_CAP_DBI2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DBI2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DBI2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DBI2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DBI2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr817450x1000700xFR/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_PCIE_CAP_DBI2DBI2 Shadow Block: PF PCI Express Capability StructuregroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP_DBI2PF0_MSIX_CAP_DBI2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr818770x1000B0RPE0_DWC_pcie_ctl_DBI_Slave_PF0_MSIX_CAP_DBI2DBI2 Shadow Block: PF MSI-X Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_TABLE_OFFSET_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_PBA_OFFSET_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REGSHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr817900x0R0x00800000PE0_DWC_pcie_ctl_DBI_Slave_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REGMSI-X Capability ID, Next Pointer, Control Registers.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81764Reserved for future use.1500x0000RPCI_MSIX_TABLE_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81780MSI-X Table Size in the shadow register.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W else RNote: This register field is sticky.26160x080RRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81789Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_TABLE_OFFSET_REGSHADOW_MSIX_TABLE_OFFSET_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr818330x4R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REGMSI-X Table Offset and BIR Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCI_MSIX_BIRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81814MSI-X Table BAR Indicator Register Field.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1 ) then R/W else RNote: This register field is sticky.200x0RPCI_MSIX_TABLE_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81832MSI-X Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1 ) then R/W else RNote: This register field is sticky.3130x00000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_PBA_OFFSET_REGSHADOW_MSIX_PBA_OFFSET_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr818760x8R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REGMSI-X PBA Offset and BIR Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCI_MSIX_PBA_BIRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81857MSI-X PBA BIR.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1 ) then R/W else RNote: This register field is sticky.200x0RPCI_MSIX_PBA_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81875MSI-X PBA Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1 ) then R/W else RNote: This register field is sticky.3130x00000000RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP_DBI2PF0_TPH_CAP_DBI2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr820330x100208RPE0_DWC_pcie_ctl_DBI_Slave_PF0_TPH_CAP_DBI2DBI2 Shadow Block: PF TLP Processing Hints Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP_DBI2.SHADOW_TPH_REQ_CAP_REG_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP_DBI2.SHADOW_TPH_REQ_CAP_REG_REGSHADOW_TPH_REQ_CAP_REG_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr820320x4R0x00000001PE0_DWC_pcie_ctl_DBI_Slave_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REGShadow register TPH Requestor Capability Register.falsefalsefalsefalseTPH_REQ_NO_ST_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81897No ST Mode Supported in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x1RTPH_REQ_CAP_INT_VECPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81915Interrupt Vector Mode Supported in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)Note: This register field is sticky.110x0RTPH_REQ_DEVICE_SPECPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81933Device Specific Mode Supported in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)Note: This register field is sticky.220x0RRSVDP_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81942Reserved for future use.730x00RTPH_REQ_EXTENDED_TPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81960Extended TPH Requester Supported in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)Note: This register field is sticky.880x0RTPH_REQ_CAP_ST_TABLE_LOC_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81978ST Table Location Bit 0 in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)Note: This register field is sticky.990x0RTPH_REQ_CAP_ST_TABLE_LOC_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr81996ST Table Location Bit 1 in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)Note: This register field is sticky.10100x0RRSVDP_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82005Reserved for future use.15110x00RTPH_REQ_CAP_ST_TABLE_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82022ST Table Size in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W else RNote: This register field is sticky.26160x000RRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82031Reserved for future use.31270x00RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAPPF0_ATU_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1078300x300000R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAPATU Por Logic StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_0IATU_REGION_CTRL_1_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr821400x0R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82051When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82062When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82071This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82082When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82094When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82106Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82119When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82139Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_0IATU_REGION_CTRL_2_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr823480x4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82161MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82173TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82193TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82205TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82218Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82230Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82253TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82270Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82291Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82305DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82325CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82337Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82347Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr823850x8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82373Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82384Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr824010xCR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82400Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_0IATU_LIMIT_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr824280x10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82417Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82427Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr824570x14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82456When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr824710x18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82470Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr825030x20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82490Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82502Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_0IATU_REGION_CTRL_1_OFF_INBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr826160x100R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82517When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82530When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82543When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82556When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82569When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82581Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82595When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82615Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_0IATU_REGION_CTRL_2_OFF_INBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr829110x104R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82641MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82666BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82684Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82695TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82706TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82718ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82731TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82745Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82764Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82777PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82793Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82809Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82828Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82843CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82855Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82900Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82910Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_0IATU_LWR_BASE_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr829480x108R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82936Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82947Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_0IATU_UPPER_BASE_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr829620x10CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82961Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_0IATU_LIMIT_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr829890x110R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82978Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr82988Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_0IATU_LWR_TARGET_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr830280x114R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83014Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83027Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr830440x118R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83043Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr830760x120R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83063Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83075Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_1IATU_REGION_CTRL_1_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr831790x200R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83090When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83101When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83110This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83121When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83133When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83145Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83158When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83178Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_1IATU_REGION_CTRL_2_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr833870x204R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83200MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83212TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83232TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83244TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83257Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83269Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83292TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83309Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83330Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83344DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83364CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83376Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83386Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr834240x208R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83412Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83423Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr834400x20CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83439Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_1IATU_LIMIT_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr834670x210R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83456Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83466Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr834960x214R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83495When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr835100x218R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83509Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr835420x220R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83529Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83541Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_1IATU_REGION_CTRL_1_OFF_INBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr836550x300R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83556When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83569When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83582When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83595When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83608When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83620Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83634When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83654Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_1IATU_REGION_CTRL_2_OFF_INBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr839500x304R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83680MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83705BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83723Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83734TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83745TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83757ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83770TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83784Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83803Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83816PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83832Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83848Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83867Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83882CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83894Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83939Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83949Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_1IATU_LWR_BASE_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr839870x308R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83975Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr83986Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_1IATU_UPPER_BASE_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr840010x30CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84000Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_1IATU_LIMIT_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr840280x310R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84017Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84027Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_1IATU_LWR_TARGET_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr840670x314R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84053Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84066Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr840830x318R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84082Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr841150x320R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84102Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84114Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_2IATU_REGION_CTRL_1_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr842180x400R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84129When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84140When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84149This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84160When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84172When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84184Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84197When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84217Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_2IATU_REGION_CTRL_2_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr844260x404R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84239MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84251TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84271TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84283TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84296Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84308Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84331TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84348Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84369Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84383DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84403CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84415Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84425Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr844630x408R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84451Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84462Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr844790x40CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84478Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_2IATU_LIMIT_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr845060x410R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84495Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84505Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr845350x414R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84534When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr845490x418R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84548Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr845810x420R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84568Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84580Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_2IATU_REGION_CTRL_1_OFF_INBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr846940x500R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84595When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84608When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84621When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84634When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84647When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84659Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84673When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84693Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_2IATU_REGION_CTRL_2_OFF_INBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr849890x504R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84719MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84744BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84762Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84773TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84784TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84796ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84809TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84823Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84842Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84855PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84871Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84887Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84906Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84921CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84933Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84978Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr84988Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_2IATU_LWR_BASE_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr850260x508R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85014Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85025Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_2IATU_UPPER_BASE_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr850400x50CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85039Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_2IATU_LIMIT_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr850670x510R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85056Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85066Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_2IATU_LWR_TARGET_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr851060x514R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85092Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85105Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr851220x518R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85121Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr851540x520R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85141Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85153Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_3IATU_REGION_CTRL_1_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr852570x600R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85168When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85179When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85188This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85199When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85211When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85223Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85236When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85256Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_3IATU_REGION_CTRL_2_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr854650x604R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85278MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85290TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85310TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85322TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85335Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85347Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85370TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85387Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85408Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85422DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85442CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85454Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85464Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr855020x608R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85490Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85501Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr855180x60CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85517Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_3IATU_LIMIT_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr855450x610R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85534Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85544Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr855740x614R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85573When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr855880x618R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85587Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr856200x620R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85607Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85619Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_3IATU_REGION_CTRL_1_OFF_INBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr857330x700R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85634When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85647When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85660When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85673When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85686When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85698Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85712When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85732Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_3IATU_REGION_CTRL_2_OFF_INBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr860280x704R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85758MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85783BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85801Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85812TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85823TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85835ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85848TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85862Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85881Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85894PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85910Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85926Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85945Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85960CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr85972Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86017Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86027Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_3IATU_LWR_BASE_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr860650x708R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86053Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86064Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_3IATU_UPPER_BASE_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr860790x70CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86078Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_3IATU_LIMIT_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr861060x710R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86095Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86105Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_3IATU_LWR_TARGET_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr861450x714R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86131Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86144Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr861610x718R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86160Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr861930x720R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86180Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86192Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_4IATU_REGION_CTRL_1_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr862960x800R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86207When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86218When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86227This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86238When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86250When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86262Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86275When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86295Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_4IATU_REGION_CTRL_2_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr865040x804R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86317MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86329TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86349TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86361TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86374Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86386Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86409TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86426Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86447Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86461DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86481CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86493Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86503Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr865410x808R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86529Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86540Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr865570x80CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86556Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_4IATU_LIMIT_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr865840x810R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86573Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86583Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr866130x814R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86612When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr866270x818R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86626Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr866590x820R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86646Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86658Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_4IATU_REGION_CTRL_1_OFF_INBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr867720x900R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86673When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86686When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86699When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86712When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86725When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86737Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86751When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86771Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_4IATU_REGION_CTRL_2_OFF_INBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr870670x904R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86797MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86822BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86840Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86851TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86862TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86874ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86887TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86901Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86920Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86933PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86949Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86965Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86984Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr86999CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87011Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87056Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87066Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_4IATU_LWR_BASE_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr871040x908R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87092Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87103Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_4IATU_UPPER_BASE_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr871180x90CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87117Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_4IATU_LIMIT_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr871450x910R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87134Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87144Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_4IATU_LWR_TARGET_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr871840x914R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87170Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87183Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr872000x918R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87199Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr872320x920R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87219Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87231Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_5IATU_REGION_CTRL_1_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr873350xA00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87246When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87257When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87266This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87277When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87289When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87301Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87314When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87334Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_5IATU_REGION_CTRL_2_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr875430xA04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87356MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87368TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87388TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87400TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87413Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87425Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87448TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87465Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87486Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87500DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87520CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87532Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87542Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr875800xA08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87568Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87579Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr875960xA0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87595Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_5IATU_LIMIT_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr876230xA10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87612Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87622Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr876520xA14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87651When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr876660xA18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87665Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr876980xA20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87685Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87697Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_5IATU_REGION_CTRL_1_OFF_INBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr878110xB00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87712When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87725When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87738When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87751When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87764When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87776Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87790When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87810Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_5IATU_REGION_CTRL_2_OFF_INBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr881060xB04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87836MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87861BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87879Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87890TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87901TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87913ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87926TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87940Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87959Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87972PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr87988Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88004Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88023Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88038CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88050Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88095Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88105Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_5IATU_LWR_BASE_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr881430xB08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88131Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88142Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_5IATU_UPPER_BASE_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr881570xB0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88156Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_5IATU_LIMIT_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr881840xB10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88173Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88183Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_5IATU_LWR_TARGET_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr882230xB14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88209Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88222Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr882390xB18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88238Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr882710xB20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88258Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88270Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_6IATU_REGION_CTRL_1_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr883740xC00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88285When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88296When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88305This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88316When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88328When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88340Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88353When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88373Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_6IATU_REGION_CTRL_2_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr885820xC04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88395MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88407TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88427TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88439TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88452Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88464Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88487TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88504Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88525Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88539DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88559CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88571Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88581Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr886190xC08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88607Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88618Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr886350xC0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88634Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_6IATU_LIMIT_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr886620xC10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88651Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88661Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr886910xC14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88690When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr887050xC18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88704Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr887370xC20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88724Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88736Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_6IATU_REGION_CTRL_1_OFF_INBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr888500xD00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88751When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88764When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88777When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88790When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88803When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88815Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88829When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88849Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_6IATU_REGION_CTRL_2_OFF_INBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr891450xD04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88875MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88900BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88918Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88929TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88940TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88952ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88965TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88979Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr88998Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89011PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89027Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89043Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89062Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89077CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89089Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89134Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89144Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_6IATU_LWR_BASE_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr891820xD08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89170Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89181Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_6IATU_UPPER_BASE_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr891960xD0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89195Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_6IATU_LIMIT_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr892230xD10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89212Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89222Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_6IATU_LWR_TARGET_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr892620xD14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89248Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89261Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr892780xD18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89277Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr893100xD20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89297Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89309Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_7IATU_REGION_CTRL_1_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr894130xE00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89324When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89335When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89344This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89355When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89367When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89379Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89392When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89412Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_7IATU_REGION_CTRL_2_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr896210xE04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89434MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89446TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89466TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89478TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89491Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89503Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89526TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89543Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89564Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89578DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89598CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89610Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89620Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr896580xE08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89646Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89657Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr896740xE0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89673Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_7IATU_LIMIT_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr897010xE10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89690Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89700Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr897300xE14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89729When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr897440xE18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89743Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr897760xE20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89763Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89775Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_7IATU_REGION_CTRL_1_OFF_INBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr898890xF00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89790When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89803When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89816When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89829When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89842When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89854Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89868When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89888Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_7IATU_REGION_CTRL_2_OFF_INBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr901840xF04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89914MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89939BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89957Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89968TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89979TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr89991ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90004TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90018Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90037Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90050PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90066Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90082Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90101Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90116CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90128Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90173Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90183Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_7IATU_LWR_BASE_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr902210xF08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90209Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90220Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_7IATU_UPPER_BASE_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr902350xF0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90234Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_7IATU_LIMIT_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr902620xF10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90251Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90261Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_7IATU_LWR_TARGET_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr903010xF14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90287Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90300Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr903170xF18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90316Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr903490xF20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90336Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90348Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_8IATU_REGION_CTRL_1_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr904520x1000R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90363When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90374When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90383This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90394When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90406When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90418Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90431When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90451Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_8IATU_REGION_CTRL_2_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr906600x1004R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90473MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90485TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90505TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90517TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90530Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90542Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90565TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90582Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90603Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90617DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90637CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90649Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90659Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr906970x1008R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90685Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90696Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr907130x100CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90712Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_8IATU_LIMIT_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr907400x1010R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90729Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90739Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr907690x1014R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90768When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr907830x1018R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90782Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr908150x1020R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90802Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90814Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_8IATU_REGION_CTRL_1_OFF_INBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr909280x1100R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90829When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90842When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90855When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90868When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90881When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90893Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90907When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90927Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_8IATU_REGION_CTRL_2_OFF_INBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr912230x1104R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90953MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90978BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr90996Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91007TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91018TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91030ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91043TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91057Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91076Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91089PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91105Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91121Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91140Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91155CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91167Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91212Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91222Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_8IATU_LWR_BASE_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr912600x1108R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91248Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91259Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_8IATU_UPPER_BASE_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr912740x110CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91273Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_8IATU_LIMIT_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr913010x1110R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91290Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91300Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_8IATU_LWR_TARGET_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr913400x1114R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91326Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91339Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr913560x1118R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91355Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr913880x1120R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91375Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91387Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_9IATU_REGION_CTRL_1_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr914910x1200R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91402When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91413When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91422This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91433When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91445When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91457Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91470When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91490Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_9IATU_REGION_CTRL_2_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr916990x1204R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91512MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91524TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91544TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91556TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91569Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91581Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91604TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91621Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91642Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91656DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91676CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91688Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91698Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr917360x1208R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91724Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91735Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr917520x120CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91751Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_9IATU_LIMIT_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr917790x1210R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91768Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91778Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr918080x1214R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91807When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr918220x1218R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91821Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr918540x1220R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91841Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91853Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_9IATU_REGION_CTRL_1_OFF_INBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr919670x1300R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91868When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91881When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91894When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91907When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91920When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91932Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91946When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91966Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_9IATU_REGION_CTRL_2_OFF_INBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr922620x1304R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr91992MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92017BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92035Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92046TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92057TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92069ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92082TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92096Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92115Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92128PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92144Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92160Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92179Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92194CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92206Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92251Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92261Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_9IATU_LWR_BASE_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr922990x1308R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92287Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92298Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_9IATU_UPPER_BASE_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr923130x130CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92312Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_9IATU_LIMIT_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr923400x1310R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92329Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92339Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_9IATU_LWR_TARGET_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr923790x1314R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92365Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92378Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr923950x1318R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92394Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr924270x1320R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92414Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92426Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_10IATU_REGION_CTRL_1_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr925300x1400R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92441When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92452When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92461This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92472When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92484When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92496Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92509When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92529Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_10IATU_REGION_CTRL_2_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr927380x1404R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92551MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92563TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92583TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92595TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92608Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92620Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92643TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92660Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92681Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92695DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92715CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92727Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92737Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr927750x1408R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92763Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92774Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr927910x140CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92790Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_10IATU_LIMIT_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr928180x1410R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92807Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92817Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr928470x1414R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92846When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr928610x1418R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92860Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr928930x1420R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92880Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92892Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_10IATU_REGION_CTRL_1_OFF_INBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr930060x1500R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92907When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92920When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92933When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92946When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92959When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92971Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr92985When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93005Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_10IATU_REGION_CTRL_2_OFF_INBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr933010x1504R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93031MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93056BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93074Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93085TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93096TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93108ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93121TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93135Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93154Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93167PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93183Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93199Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93218Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93233CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93245Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93290Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93300Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_10IATU_LWR_BASE_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr933380x1508R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93326Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93337Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_10IATU_UPPER_BASE_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr933520x150CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93351Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_10IATU_LIMIT_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr933790x1510R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93368Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93378Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_10IATU_LWR_TARGET_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr934180x1514R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93404Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93417Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr934340x1518R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93433Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr934660x1520R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93453Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93465Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_11IATU_REGION_CTRL_1_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr935690x1600R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93480When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93491When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93500This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93511When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93523When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93535Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93548When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93568Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_11IATU_REGION_CTRL_2_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr937770x1604R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93590MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93602TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93622TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93634TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93647Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93659Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93682TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93699Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93720Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93734DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93754CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93766Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93776Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr938140x1608R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93802Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93813Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr938300x160CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93829Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_11IATU_LIMIT_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr938570x1610R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93846Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93856Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr938860x1614R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93885When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr939000x1618R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93899Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr939320x1620R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93919Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93931Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_11IATU_REGION_CTRL_1_OFF_INBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr940450x1700R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93946When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93959When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93972When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93985When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr93998When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94010Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94024When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94044Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_11IATU_REGION_CTRL_2_OFF_INBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr943400x1704R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94070MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94095BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94113Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94124TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94135TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94147ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94160TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94174Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94193Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94206PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94222Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94238Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94257Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94272CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94284Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94329Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94339Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_11IATU_LWR_BASE_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr943770x1708R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94365Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94376Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_11IATU_UPPER_BASE_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr943910x170CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94390Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_11IATU_LIMIT_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr944180x1710R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94407Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94417Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_11IATU_LWR_TARGET_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr944570x1714R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94443Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94456Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr944730x1718R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94472Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr945050x1720R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94492Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94504Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_12IATU_REGION_CTRL_1_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr946080x1800R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94519When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94530When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94539This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94550When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94562When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94574Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94587When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94607Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_12IATU_REGION_CTRL_2_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr948160x1804R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94629MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94641TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94661TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94673TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94686Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94698Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94721TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94738Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94759Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94773DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94793CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94805Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94815Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr948530x1808R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94841Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94852Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr948690x180CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94868Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_12IATU_LIMIT_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr948960x1810R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94885Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94895Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr949250x1814R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94924When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr949390x1818R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94938Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr949710x1820R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94958Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94970Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_12IATU_REGION_CTRL_1_OFF_INBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr950840x1900R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94985When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr94998When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95011When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95024When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95037When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95049Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95063When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95083Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_12IATU_REGION_CTRL_2_OFF_INBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr953790x1904R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95109MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95134BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95152Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95163TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95174TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95186ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95199TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95213Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95232Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95245PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95261Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95277Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95296Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95311CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95323Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95368Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95378Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_12IATU_LWR_BASE_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr954160x1908R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95404Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95415Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_12IATU_UPPER_BASE_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr954300x190CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95429Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_12IATU_LIMIT_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr954570x1910R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95446Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95456Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_12IATU_LWR_TARGET_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr954960x1914R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95482Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95495Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr955120x1918R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95511Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr955440x1920R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95531Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95543Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_13IATU_REGION_CTRL_1_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr956470x1A00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95558When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95569When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95578This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95589When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95601When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95613Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95626When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95646Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_13IATU_REGION_CTRL_2_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr958550x1A04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95668MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95680TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95700TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95712TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95725Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95737Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95760TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95777Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95798Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95812DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95832CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95844Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95854Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr958920x1A08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95880Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95891Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr959080x1A0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95907Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_13IATU_LIMIT_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr959350x1A10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95924Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95934Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr959640x1A14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95963When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr959780x1A18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95977Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr960100x1A20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr95997Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96009Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_13IATU_REGION_CTRL_1_OFF_INBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr961230x1B00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96024When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96037When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96050When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96063When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96076When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96088Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96102When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96122Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_13IATU_REGION_CTRL_2_OFF_INBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr964180x1B04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96148MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96173BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96191Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96202TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96213TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96225ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96238TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96252Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96271Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96284PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96300Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96316Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96335Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96350CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96362Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96407Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96417Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_13IATU_LWR_BASE_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr964550x1B08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96443Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96454Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_13IATU_UPPER_BASE_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr964690x1B0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96468Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_13IATU_LIMIT_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr964960x1B10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96485Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96495Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_13IATU_LWR_TARGET_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr965350x1B14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96521Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96534Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr965510x1B18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96550Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr965830x1B20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96570Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96582Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_14IATU_REGION_CTRL_1_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr966860x1C00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96597When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96608When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96617This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96628When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96640When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96652Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96665When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96685Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_14IATU_REGION_CTRL_2_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr968940x1C04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96707MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96719TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96739TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96751TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96764Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96776Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96799TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96816Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96837Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96851DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96871CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96883Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96893Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr969310x1C08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96919Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96930Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr969470x1C0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96946Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_14IATU_LIMIT_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr969740x1C10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96963Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr96973Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr970030x1C14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97002When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr970170x1C18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97016Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr970490x1C20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97036Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97048Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_14IATU_REGION_CTRL_1_OFF_INBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr971620x1D00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97063When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97076When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97089When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97102When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97115When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97127Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97141When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97161Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_14IATU_REGION_CTRL_2_OFF_INBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr974570x1D04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97187MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97212BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97230Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97241TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97252TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97264ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97277TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97291Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97310Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97323PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97339Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97355Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97374Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97389CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97401Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97446Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97456Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_14IATU_LWR_BASE_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr974940x1D08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97482Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97493Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_14IATU_UPPER_BASE_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr975080x1D0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97507Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_14IATU_LIMIT_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr975350x1D10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97524Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97534Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_14IATU_LWR_TARGET_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr975740x1D14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97560Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97573Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr975900x1D18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97589Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr976220x1D20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97609Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97621Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_15IATU_REGION_CTRL_1_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr977250x1E00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97636When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97647When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97656This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97667When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97679When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97691Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97704When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97724Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_15IATU_REGION_CTRL_2_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr979330x1E04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97746MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97758TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97778TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97790TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97803Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97815Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97838TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97855Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97876Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97890DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97910CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97922Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97932Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr979700x1E08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97958Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97969Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr979860x1E0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr97985Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_15IATU_LIMIT_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr980130x1E10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98002Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98012Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr980420x1E14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98041When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr980560x1E18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98055Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr980880x1E20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98075Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98087Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_15IATU_REGION_CTRL_1_OFF_INBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr982010x1F00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98102When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98115When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98128When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98141When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98154When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98166Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98180When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98200Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_15IATU_REGION_CTRL_2_OFF_INBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr984960x1F04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98226MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98251BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98269Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98280TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98291TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98303ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98316TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98330Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98349Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98362PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98378Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98394Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98413Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98428CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98440Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98485Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98495Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_15IATU_LWR_BASE_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr985330x1F08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98521Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98532Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_15IATU_UPPER_BASE_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr985470x1F0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98546Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_15IATU_LIMIT_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr985740x1F10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98563Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98573Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_15IATU_LWR_TARGET_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr986130x1F14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98599Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98612Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr986290x1F18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98628Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr986610x1F20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98648Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98660Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_16IATU_REGION_CTRL_1_OFF_INBOUND_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr987740x2100R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98675When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98688When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98701When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98714When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98727When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98739Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98753When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98773Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_16IATU_REGION_CTRL_2_OFF_INBOUND_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr990690x2104R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98799MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98824BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98842Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98853TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98864TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98876ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98889TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98903Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98922Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98935PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98951Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98967Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr98986Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99001CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99013Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99058Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99068Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_16IATU_LWR_BASE_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr991060x2108R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99094Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99105Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_16IATU_UPPER_BASE_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr991200x210CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99119Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_16IATU_LIMIT_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr991470x2110R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99136Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99146Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_16IATU_LWR_TARGET_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr991860x2114R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99172Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99185Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr992020x2118R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99201Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr992340x2120R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99221Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99233Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_17IATU_REGION_CTRL_1_OFF_INBOUND_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr993470x2300R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99248When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99261When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99274When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99287When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99300When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99312Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99326When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99346Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_17IATU_REGION_CTRL_2_OFF_INBOUND_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr996420x2304R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99372MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99397BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99415Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99426TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99437TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99449ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99462TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99476Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99495Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99508PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99524Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99540Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99559Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99574CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99586Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99631Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99641Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_17IATU_LWR_BASE_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr996790x2308R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99667Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99678Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_17IATU_UPPER_BASE_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr996930x230CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99692Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_17IATU_LIMIT_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr997200x2310R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99709Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99719Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_17IATU_LWR_TARGET_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr997590x2314R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99745Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99758Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr997750x2318R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99774Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr998070x2320R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99794Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99806Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_18IATU_REGION_CTRL_1_OFF_INBOUND_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr999200x2500R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99821When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99834When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99847When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99860When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99873When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99885Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99899When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99919Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_18IATU_REGION_CTRL_2_OFF_INBOUND_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1002150x2504R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99945MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99970BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99988Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr99999TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100010TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100022ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100035TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100049Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100068Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100081PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100097Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100113Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100132Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100147CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100159Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100204Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100214Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_18IATU_LWR_BASE_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1002520x2508R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100240Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100251Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_18IATU_UPPER_BASE_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1002660x250CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100265Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_18IATU_LIMIT_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1002930x2510R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100282Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100292Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_18IATU_LWR_TARGET_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1003320x2514R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100318Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100331Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1003480x2518R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100347Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1003800x2520R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100367Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100379Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_19IATU_REGION_CTRL_1_OFF_INBOUND_19PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1004930x2700R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100394When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100407When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100420When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100433When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100446When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100458Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100472When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100492Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_19IATU_REGION_CTRL_2_OFF_INBOUND_19PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1007880x2704R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100518MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100543BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100561Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100572TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100583TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100595ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100608TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100622Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100641Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100654PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100670Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100686Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100705Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100720CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100732Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100777Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100787Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_19IATU_LWR_BASE_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1008250x2708R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100813Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100824Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_19IATU_UPPER_BASE_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1008390x270CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100838Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_19IATU_LIMIT_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1008660x2710R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100855Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100865Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_19IATU_LWR_TARGET_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1009050x2714R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100891Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100904Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1009210x2718R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100920Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1009530x2720R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100940Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100952Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_20IATU_REGION_CTRL_1_OFF_INBOUND_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1010660x2900R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100967When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100980When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr100993When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101006When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101019When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101031Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101045When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101065Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_20IATU_REGION_CTRL_2_OFF_INBOUND_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1013610x2904R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101091MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101116BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101134Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101145TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101156TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101168ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101181TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101195Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101214Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101227PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101243Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101259Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101278Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101293CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101305Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101350Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101360Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_20IATU_LWR_BASE_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1013980x2908R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101386Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101397Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_20IATU_UPPER_BASE_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1014120x290CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101411Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_20IATU_LIMIT_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1014390x2910R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101428Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101438Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_20IATU_LWR_TARGET_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1014780x2914R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101464Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101477Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1014940x2918R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101493Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1015260x2920R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101513Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101525Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_21IATU_REGION_CTRL_1_OFF_INBOUND_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1016390x2B00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101540When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101553When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101566When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101579When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101592When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101604Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101618When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101638Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_21IATU_REGION_CTRL_2_OFF_INBOUND_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1019340x2B04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101664MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101689BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101707Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101718TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101729TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101741ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101754TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101768Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101787Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101800PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101816Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101832Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101851Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101866CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101878Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101923Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101933Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_21IATU_LWR_BASE_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1019710x2B08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101959Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101970Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_21IATU_UPPER_BASE_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1019850x2B0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr101984Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_21IATU_LIMIT_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1020120x2B10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102001Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102011Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_21IATU_LWR_TARGET_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1020510x2B14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102037Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102050Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1020670x2B18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102066Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1020990x2B20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102086Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102098Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_22IATU_REGION_CTRL_1_OFF_INBOUND_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1022120x2D00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102113When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102126When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102139When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102152When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102165When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102177Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102191When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102211Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_22IATU_REGION_CTRL_2_OFF_INBOUND_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1025070x2D04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102237MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102262BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102280Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102291TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102302TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102314ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102327TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102341Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102360Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102373PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102389Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102405Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102424Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102439CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102451Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102496Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102506Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_22IATU_LWR_BASE_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1025440x2D08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102532Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102543Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_22IATU_UPPER_BASE_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1025580x2D0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102557Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_22IATU_LIMIT_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1025850x2D10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102574Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102584Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_22IATU_LWR_TARGET_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1026240x2D14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102610Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102623Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1026400x2D18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102639Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1026720x2D20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102659Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102671Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_23IATU_REGION_CTRL_1_OFF_INBOUND_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1027850x2F00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102686When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102699When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102712When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102725When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102738When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102750Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102764When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102784Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_23IATU_REGION_CTRL_2_OFF_INBOUND_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1030800x2F04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102810MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102835BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102853Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102864TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102875TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102887ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102900TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102914Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102933Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102946PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102962Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102978Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr102997Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103012CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103024Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103069Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103079Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_23IATU_LWR_BASE_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1031170x2F08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103105Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103116Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_23IATU_UPPER_BASE_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1031310x2F0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103130Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_23IATU_LIMIT_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1031580x2F10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103147Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103157Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_23IATU_LWR_TARGET_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1031970x2F14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103183Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103196Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1032130x2F18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103212Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1032450x2F20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103232Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103244Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_24IATU_REGION_CTRL_1_OFF_INBOUND_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1033580x3100R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103259When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103272When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103285When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103298When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103311When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103323Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103337When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103357Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_24IATU_REGION_CTRL_2_OFF_INBOUND_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1036530x3104R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103383MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103408BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103426Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103437TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103448TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103460ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103473TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103487Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103506Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103519PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103535Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103551Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103570Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103585CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103597Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103642Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103652Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_24IATU_LWR_BASE_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1036900x3108R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103678Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103689Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_24IATU_UPPER_BASE_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1037040x310CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103703Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_24IATU_LIMIT_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1037310x3110R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103720Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103730Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_24IATU_LWR_TARGET_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1037700x3114R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103756Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103769Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1037860x3118R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103785Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1038180x3120R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103805Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103817Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_25IATU_REGION_CTRL_1_OFF_INBOUND_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1039310x3300R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103832When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103845When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103858When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103871When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103884When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103896Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103910When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103930Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_25IATU_REGION_CTRL_2_OFF_INBOUND_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1042260x3304R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103956MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103981BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr103999Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104010TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104021TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104033ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104046TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104060Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104079Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104092PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104108Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104124Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104143Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104158CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104170Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104215Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104225Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_25IATU_LWR_BASE_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1042630x3308R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104251Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104262Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_25IATU_UPPER_BASE_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1042770x330CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104276Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_25IATU_LIMIT_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1043040x3310R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104293Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104303Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_25IATU_LWR_TARGET_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1043430x3314R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104329Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104342Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1043590x3318R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104358Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1043910x3320R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104378Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104390Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_26IATU_REGION_CTRL_1_OFF_INBOUND_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1045040x3500R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104405When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104418When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104431When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104444When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104457When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104469Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104483When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104503Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_26IATU_REGION_CTRL_2_OFF_INBOUND_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1047990x3504R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104529MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104554BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104572Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104583TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104594TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104606ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104619TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104633Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104652Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104665PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104681Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104697Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104716Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104731CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104743Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104788Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104798Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_26IATU_LWR_BASE_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1048360x3508R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104824Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104835Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_26IATU_UPPER_BASE_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1048500x350CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104849Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_26IATU_LIMIT_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1048770x3510R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104866Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104876Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_26IATU_LWR_TARGET_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1049160x3514R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104902Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104915Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1049320x3518R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104931Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1049640x3520R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104951Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104963Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_27IATU_REGION_CTRL_1_OFF_INBOUND_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1050770x3700R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104978When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr104991When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105004When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105017When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105030When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105042Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105056When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105076Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_27IATU_REGION_CTRL_2_OFF_INBOUND_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1053720x3704R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105102MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105127BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105145Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105156TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105167TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105179ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105192TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105206Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105225Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105238PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105254Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105270Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105289Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105304CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105316Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105361Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105371Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_27IATU_LWR_BASE_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1054090x3708R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105397Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105408Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_27IATU_UPPER_BASE_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1054230x370CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105422Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_27IATU_LIMIT_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1054500x3710R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105439Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105449Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_27IATU_LWR_TARGET_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1054890x3714R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105475Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105488Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1055050x3718R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105504Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1055370x3720R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105524Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105536Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_28IATU_REGION_CTRL_1_OFF_INBOUND_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1056500x3900R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105551When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105564When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105577When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105590When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105603When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105615Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105629When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105649Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_28IATU_REGION_CTRL_2_OFF_INBOUND_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1059450x3904R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105675MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105700BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105718Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105729TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105740TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105752ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105765TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105779Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105798Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105811PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105827Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105843Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105862Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105877CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105889Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105934Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105944Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_28IATU_LWR_BASE_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1059820x3908R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105970Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105981Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_28IATU_UPPER_BASE_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1059960x390CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr105995Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_28IATU_LIMIT_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1060230x3910R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106012Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106022Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_28IATU_LWR_TARGET_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1060620x3914R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106048Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106061Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1060780x3918R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106077Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1061100x3920R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106097Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106109Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_29IATU_REGION_CTRL_1_OFF_INBOUND_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1062230x3B00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106124When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106137When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106150When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106163When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106176When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106188Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106202When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106222Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_29IATU_REGION_CTRL_2_OFF_INBOUND_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1065180x3B04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106248MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106273BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106291Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106302TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106313TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106325ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106338TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106352Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106371Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106384PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106400Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106416Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106435Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106450CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106462Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106507Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106517Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_29IATU_LWR_BASE_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1065550x3B08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106543Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106554Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_29IATU_UPPER_BASE_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1065690x3B0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106568Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_29IATU_LIMIT_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1065960x3B10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106585Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106595Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_29IATU_LWR_TARGET_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1066350x3B14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106621Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106634Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1066510x3B18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106650Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1066830x3B20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106670Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106682Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_30IATU_REGION_CTRL_1_OFF_INBOUND_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1067960x3D00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106697When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106710When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106723When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106736When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106749When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106761Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106775When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106795Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_30IATU_REGION_CTRL_2_OFF_INBOUND_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1070910x3D04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106821MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106846BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106864Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106875TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106886TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106898ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106911TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106925Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106944Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106957PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106973Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr106989Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107008Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107023CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107035Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107080Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107090Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_30IATU_LWR_BASE_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1071280x3D08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107116Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107127Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_30IATU_UPPER_BASE_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1071420x3D0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107141Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_30IATU_LIMIT_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1071690x3D10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107158Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107168Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_30IATU_LWR_TARGET_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1072080x3D14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107194Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107207Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1072240x3D18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107223Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1072560x3D20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107243Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107255Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_31IATU_REGION_CTRL_1_OFF_INBOUND_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1073690x3F00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107270When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107283When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107296When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107309When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107322When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107334Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107348When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107368Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_31IATU_REGION_CTRL_2_OFF_INBOUND_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1076640x3F04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107394MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107419BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107437Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107448TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107459TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107471ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107484TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107498Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107517Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107530PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107546Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107562Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107581Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107596CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107608Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107653Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107663Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_31IATU_LWR_BASE_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1077010x3F08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107689Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107700Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_31IATU_UPPER_BASE_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1077150x3F0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107714Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_31IATU_LIMIT_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1077420x3F10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107731Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107741Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_31IATU_LWR_TARGET_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1077810x3F14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107767Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107780Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1077970x3F18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107796Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1078290x3F20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107816Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107828Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAPPF0_DMA_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1141780x380000R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAPDMA Port Logic StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CTRL_DATA_ARB_PRIOR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DOORBELL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DOORBELL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_MASK_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_CLEAR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ERR_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH01_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH23_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH45_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH67_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_LINKED_LIST_ERR_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_MASK_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_CLEAR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_LINKED_LIST_ERR_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH01_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH23_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH45_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH67_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CTRL_DATA_ARB_PRIOR_OFFDMA_CTRL_DATA_ARB_PRIOR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1079080x0R/W0x00000688PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFFDMA Arbitration Scheme for TRGT1 Interface. This register is used to control traffic priorities among various sources that are delivered to your application through TRGT1 where 0x0 represents the highest priority. - Non-DMA Rx Requests - DMA Write Channel MRd Requests (DMA data requests and LL element/descriptor access) - DMA Read Channel MRd Requests (LL element/descriptor access) - DMA Read Channel MWr RequestsConcurrent traffic from channels with same priority are sorted according to Round-Robin arbitration rules.The arbitration priority defaults to Non-DMA requests (highest), Write Channel MRd, Read Channel MRd, Read Channel MWr.For more details, see the For more details, see the Internal Architecture section in the DMA chapter of the Databook.falsefalsefalsefalseRTRGT1_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107864Non-DMA Rx Requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 200x0R/WWR_CTRL_TRGT_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107876DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 530x1R/WRD_CTRL_TRGT_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107888DMA Read Channel MRd Requests. For LL element/descriptor access.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 860x2R/WRDBUFF_TRGT_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107899DMA Read Channel MWr Requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1190x3R/WRSVDP_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107907Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CTRL_OFFDMA_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1079840x8R/W0x00040004PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CTRL_OFFDMA Number of Channels Register.falsefalsefalsefalseNUM_DMA_WR_CHANPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107921Number of Write Channels. You can read this register to determine the number of write channels the DMA controller has been configured to support.300x4RRSVDP_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107929Reserved for future use.1540x000RNUM_DMA_RD_CHANPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107939Number of Read Channels. You can read this register to determine the number of read channels the DMA controller has been configured to support.19160x4RRSVDP_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107947Reserved for future use.23200x0RDIS_C2W_CACHE_WRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107961Disable DMA Write Channels "completion to memory write" context cache pre-fetch function.Note: For internal debugging only.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDIS_C2W_CACHE_RDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107975Disable DMA Read Channels "completion to memory write" context cache pre-fetch function.Note: For internal debugging only.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WRSVDP_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_SETDWC_pcie_dbi_cpcie_usp_4x8.csr107983Reserved for future use.31260x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_EN_OFFDMA_WRITE_ENGINE_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1081430xCR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFFDMA Write Engine Enable Register.falsefalsefalsefalseDMA_WRITE_ENGINEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108038DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset)For normal operation, you must initially set this bit to "1", before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation.You should set this bit to "0" when you want to "Soft Reset" the DMA controller write logic. There are three possible reasons for resetting the DMA controller write logic: - The "Abort Interrupt Status" bit is set (in the "DMA Write Interrupt Status Register" DMA_WRITE_INT_STATUS_OFF), and any of the bits is in the "DMA Write Error Status Register" (DMA_WRITE_ERR_STATUS_OFF) are set. Resetting the DMA controller write logic re-initializes the control logic, ensuring that the next DMA write transfer is executed successfully. - You have executed the procedure outlined in "Stop Bit" , after which, the "Abort Interrupt Status" bit is set and the Channel Status field (CS) of the DMA write "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_WRCH_0) is set to "Stopped." Resetting the DMA controller write logic re-initializes the control logic ensuring that the next DMA write transfer is executed successfully. - During software development, when you incorrectly program the DMA write engine.To "Soft Reset" the DMA controller write logic, you must: - De-assert the DMA write engine enable bit. - Wait for the DMA to complete any in-progress TLP transfer, by waiting until a read on the DMA write engine enable bit returns a "0". - Assert the DMA write engine enable bit.This "Soft Reset" does not clear the DMA configuration registers. The DMA write transfer does not start until you write to the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108046Reserved for future use.1510x0000RDMA_WRITE_ENGINE_EN_HSHAKE_CH0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108057Enable Handshake for DMA Write Engine Channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16160x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108068Enable Handshake for DMA Write Engine Channel 1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 17170x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108079Enable Handshake for DMA Write Engine Channel 2.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 18180x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108090Enable Handshake for DMA Write Engine Channel 3.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19190x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108101Enable Handshake for DMA Write Engine Channel 4.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 20200x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108112Enable Handshake for DMA Write Engine Channel 5.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21210x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108123Enable Handshake for DMA Write Engine Channel 6.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108134Enable Handshake for DMA Write Engine Channel 7.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108142Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DOORBELL_OFFDMA_WRITE_DOORBELL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1081960x10R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFFDMA Write Doorbell Register.falsefalsefalsefalseWR_DOORBELL_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108166Doorbell Number. You must write the channel number to this register to start the DMA write transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. You do not need to toggle or write any other value to this register to start a new transfer.The range of this field is 0x0 to 0x7, and 0x0 corresponds to channel 0. Also note that a write to this field triggers the controller to exit L1 substates.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 200x0R/WRSVDP_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108174Reserved for future use.3030x0000000RWR_STOPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108195Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests, sets the channel status to "Stopped", and asserts the "Abort" interrupt if it is enabled. Before setting the Stop bit, you must read the channel Status field (CS) of the "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_WRCH_0) to ensure that the write channel is "Running" (transferring data).For more information, see "Stopping the DMA Transfer (Software Stop)."Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFDMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1082780x18R/W0x00008421PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFDMA Write Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for write channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to the arbitration routine. When the channel weight count is reached or DMA channel request transfer size reaches zero, the WWR arbiter selects the next channel to be processed. Your software must initialize this register before ringing the doorbell. For more details, see "Multichannel Arbitration". Value range is (0-0x1F) corresponding to (1-32) transaction requests.falsefalsefalsefalseWRITE_CHANNEL0_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108224Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 400x01R/WWRITE_CHANNEL1_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108239Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 950x01R/WWRITE_CHANNEL2_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108254Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 14100x01R/WWRITE_CHANNEL3_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108269Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19150x01R/WRSVDP_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108277Reserved for future use.31200x000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFDMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1083600x1CR/W0x00008421PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFDMA Write Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for write channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to the arbitration routine. When the channel weight count is reached or DMA channel request transfer size reaches zero, the WWR arbiter selects the next channel to be processed. Your software must initialize this register before ringing the doorbell. For more details, see "Multichannel Arbitration". Value range is (0-0x1F) corresponding to (1-32) transaction requests.falsefalsefalsefalseWRITE_CHANNEL4_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108306Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 400x01R/WWRITE_CHANNEL5_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108321Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 950x01R/WWRITE_CHANNEL6_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108336Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 14100x01R/WWRITE_CHANNEL7_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108351Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19150x01R/WRSVDP_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108359Reserved for future use.31200x000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_EN_OFFDMA_READ_ENGINE_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1085180x2CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFFDMA Read Engine Enable Register.falsefalsefalsefalseDMA_READ_ENGINEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108413DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset)For normal operation, you must initially set this bit to "1", before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation.You should set this field to "0" when you want to "Soft Reset" the DMA controller read logic. There are three possible reasons for resetting the DMA controller read logic: - The "Abort Interrupt Status" bit is set (in the "DMA Read Interrupt Status Register" (DMA_READ_INT_STATUS_OFF), and any of the bits in the "DMA Read Error Status Low Register" (DMA_READ_ERR_STATUS_LOW_OFF) is set. Resetting the DMA controller read logic re-initializes the control logic, ensuring that the next DMA read transfer is executed successfully. - You have executed the procedure outlined in "Stop Bit", after which, the "Abort Interrupt Status" bit is set and the channel Status field (CS) of the DMA read "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_WRCH_0) is set to "Stopped". Resetting the DMA controller read logic re-initializes the control logic ensuring that the next DMA read transfer is executed successfully. - During software development, when you incorrectly program the DMA read engine.To "Soft Reset" the DMA controller read logic, you must: - De-assert the DMA read engine enable bit. - Wait for the DMA to complete any in-progress TLP transfer, by waiting until a read on the DMA read engine enable bit returns a "0". - Assert the DMA read engine enable bit.This "Soft Reset" does not clear the DMA configuration registers. The DMA read transfer does not start until you write to the "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108421Reserved for future use.1510x0000RDMA_READ_ENGINE_EN_HSHAKE_CH0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108432Enable Handshake for DMA Read Engine Channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16160x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108443Enable Handshake for DMA Read Engine Channel 1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 17170x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108454Enable Handshake for DMA Read Engine Channel 2.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 18180x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108465Enable Handshake for DMA Read Engine Channel 3.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19190x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108476Enable Handshake for DMA Read Engine Channel 4.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 20200x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108487Enable Handshake for DMA Read Engine Channel 5.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21210x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108498Enable Handshake for DMA Read Engine Channel 6.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108509Enable Handshake for DMA Read Engine Channel 7.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108517Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DOORBELL_OFFDMA_READ_DOORBELL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1085690x30R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_DOORBELL_OFFDMA Read Doorbell Register.falsefalsefalsefalseRD_DOORBELL_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108539Doorbell Number. You must write 0x0 to this register to start the DMA read transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change.The range of this field is 0x0 to 0x7, and 0x0 corresponds to channel 0. Also note that a write to this field triggers the controller to exit L1 substates.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 200x0R/WRSVDP_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108547Reserved for future use.3030x0000000RRD_STOPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108568Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests, sets the channel status to "Stopped", and asserts the "Abort" interrupt if it is enabled. Before setting the Stop bit, you must read the channel Status field (CS) of the "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_RDCH_0) to ensure that the read channel is "Running" (transferring data).For more information, see "Stopping the DMA Transfer (Software Stop)".Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFDMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1086460x38R/W0x00008421PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFDMA Read Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for read channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to the arbitration routine. When the channel weight count is reached or DMA channel request transfer size reaches zero, the WWR arbiter selects the next channel to be processed. Your software must initialize this register before ringing the doorbell. For more details, see "Multichannel Arbitration". Value range is (0-0x1F) corresponding to (1-32) transaction requests.falsefalsefalsefalseREAD_CHANNEL0_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108595Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 400x01R/WREAD_CHANNEL1_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108609Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 950x01R/WREAD_CHANNEL2_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108623Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 14100x01R/WREAD_CHANNEL3_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108637Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19150x01R/WRSVDP_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108645Reserved for future use.31200x000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFDMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1087230x3CR/W0x00008421PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFDMA Read Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for read channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to the arbitration routine. When the channel weight count is reached or DMA channel request transfer size reaches zero, the WWR arbiter selects the next channel to be processed. Your software must initialize this register before ringing the doorbell. For more details, see "Multichannel Arbitration". Value range is (0-0x1F) corresponding to (1-32) transaction requests.falsefalsefalsefalseREAD_CHANNEL4_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108672Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 400x01R/WREAD_CHANNEL5_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108686Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 950x01R/WREAD_CHANNEL6_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108700Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 14100x01R/WREAD_CHANNEL7_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108714Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19150x01R/WRSVDP_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108722Reserved for future use.31200x000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_STATUS_OFFDMA_WRITE_INT_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1087970x4CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFFDMA Write Interrupt Status Register.falsefalsefalsefalseWR_DONE_INT_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108753Done Interrupt Status. The DMA write channel has successfully completed the DMA transfer. For more details, see "Interrupts and Error Handling". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA write interrupt Clear register to clear this interrupt bit. Note: You can write to this register to emulate interrupt generation, during software or hardware testing. A write to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this register.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 700x00R/WRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108761Reserved for future use.1580x00RWR_ABORT_INT_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108788Abort Interrupt Status. The DMA write channel has detected an error, or you manually stopped the transfer as described in "Error Handling Assistance by Remote Software". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA write interrupt Clear register to clear this interrupt bit. Note: You can write to this register to emulate interrupt generation, during software or hardware testing. A write to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this register.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23160x00R/WRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108796Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_MASK_OFFDMA_WRITE_INT_MASK_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1088450x54R/W0x000f000fPE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFFDMA Write Interrupt Mask Register.falsefalsefalsefalseWR_DONE_INT_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108814Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 300xfR/W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108822Reserved for future use.1580x00RWR_ABORT_INT_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108836Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19160xfR/W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108844Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_CLEAR_OFFDMA_WRITE_INT_CLEAR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1088970x58R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFFDMA Write Interrupt Clear Register.falsefalsefalsefalseWR_DONE_INT_CLEARPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108864Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: Reading from this self-clearing register field always returns a "0".300x0W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108872Reserved for future use.1580x00RWR_ABORT_INT_CLEARPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108888Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: Reading from this self-clearing register field always returns a "0".19160x0W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108896Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ERR_STATUS_OFFDMA_WRITE_ERR_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1089590x5CR0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFFDMA Write Error Status RegisterfalsefalsefalsefalseAPP_READ_ERR_DETECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108922Application Read Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading data from it. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Write Interrupt Clear Register" (DMA_WRITE_INT_CLEAR_OFF) to clear this error bit.700x00RRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108929Reserved for future use.1580x00RLINKLIST_ELEMENT_FETCH_ERR_DETECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108951Linked List Element Fetch Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Write Interrupt Clear Register" (DMA_WRITE_INT_CLEAR_OFF) to clear this error bit.23160x00RRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108958Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_LOW_OFFDMA_WRITE_DONE_IMWR_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1089760x60R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFFDMA Write Done IMWr Address Low Register.falsefalsefalsefalseDMA_WRITE_DONE_LOW_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108975The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be "00" as this address must be dword aligned.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_HIGH_OFFDMA_WRITE_DONE_IMWR_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1089920x64R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFFDMA Write Done IMWr Interrupt Address High Register.falsefalsefalsefalseDMA_WRITE_DONE_HIGH_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr108991The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_LOW_OFFDMA_WRITE_ABORT_IMWR_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1090100x68R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFFDMA Write Abort IMWr Address Low Register.falsefalsefalsefalseDMA_WRITE_ABORT_LOW_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109009The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. Bits [1:0] must be "00" as this address must be dword aligned.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_HIGH_OFFDMA_WRITE_ABORT_IMWR_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1090260x6CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFFDMA Write Abort IMWr Address High Register.falsefalsefalsefalseDMA_WRITE_ABORT_HIGH_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109025The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH01_IMWR_DATA_OFFDMA_WRITE_CH01_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1090540x70R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFFDMA Write Channel 1 and 0 IMWr Data Register.falsefalsefalsefalseWR_CHANNEL_0_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109041The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WWR_CHANNEL_1_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109053The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH23_IMWR_DATA_OFFDMA_WRITE_CH23_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1090820x74R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFFDMA Write Channel 3 and 2 IMWr Data Register.falsefalsefalsefalseWR_CHANNEL_2_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109069The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WWR_CHANNEL_3_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109081The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH45_IMWR_DATA_OFFDMA_WRITE_CH45_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1091100x78R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFFDMA Write Channel 5 and 4 IMWr Data Register.falsefalsefalsefalseWR_CHANNEL_4_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109097The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 4.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WWR_CHANNEL_5_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109109The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 5.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH67_IMWR_DATA_OFFDMA_WRITE_CH67_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1091380x7CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFFDMA Write Channel 7 and 6 IMWr Data Register.falsefalsefalsefalseWR_CHANNEL_6_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109125The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 6.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WWR_CHANNEL_7_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109137The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 7.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_LINKED_LIST_ERR_EN_OFFDMA_WRITE_LINKED_LIST_ERR_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1091960x90R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFFDMA Write Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel "done" interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel "abort" interrupts (local and remote).falsefalsefalsefalseWR_CHANNEL_LLRAIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109162Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Used in linked list mode only.For more details, see "Interrupt Handling".Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 300x0R/W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109170Reserved for future use.1580x00RWR_CHANNEL_LLLAIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109187Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Used in linked list mode only.For more details, see "Interrupt Handling".Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19160x0R/W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109195Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_STATUS_OFFDMA_READ_INT_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1092730xA0R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFFDMA Read Interrupt Status Register.falsefalsefalsefalseRD_DONE_INT_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109225Done Interrupt Status. The DMA read channel has successfully completed the DMA read transfer.Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA read interrupt Clear register to clear this interrupt bit. Note: You can write to this register to emulate interrupt generation, during software or hardware testing. A write to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this register.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 700x00R/WRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109233Reserved for future use.1580x00RRD_ABORT_INT_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109264Abort Interrupt Status. The DMA read channel has detected an error, or you manually stopped the transfer as described in "Stopping the DMA Transfer (Software Stop)". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.You can read the "DMA Read Error Status Low Register" (DMA_READ_ERR_STATUS_LOW_OFF) and "DMA Read Error Status High Register" (DMA_READ_ERR_STATUS_HIGH_OFF) to determine the source of the error. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA read interrupt Clear register to clear this interrupt bit. Note: You can write to this register to emulate interrupt generation, during software or hardware testing. A write to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this register.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23160x00R/WRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109272Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_MASK_OFFDMA_READ_INT_MASK_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1093210xA8R/W0x000f000fPE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_INT_MASK_OFFDMA Read Interrupt Mask Register.falsefalsefalsefalseRD_DONE_INT_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109290Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 300xfR/W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109298Reserved for future use.1580x00RRD_ABORT_INT_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109312Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19160xfR/W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109320Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_CLEAR_OFFDMA_READ_INT_CLEAR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1093730xACR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFFDMA Read Interrupt Clear Register.falsefalsefalsefalseRD_DONE_INT_CLEARPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109340Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: Reading from this self-clearing register field always returns a "0".700x00WRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109348Reserved for future use.1580x00RRD_ABORT_INT_CLEARPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109364Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: Reading from this self-clearing register field always returns a "0".23160x00WRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109372Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_LOW_OFFDMA_READ_ERR_STATUS_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1094410xB4R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFFDMA Read Error Status Low Register.falsefalsefalsefalseAPP_WR_ERR_DETECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109403Application Write Error Detected. The DMA read channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while writing data to it. This error is fatal. You must restart the transfer from the beginning, as the channel context is corrupted, and the transfer is not rolled back. For more details, see "Linked List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this clears all bits in this register, and also the DMA Read Error Status High register (DMA_READ_ERR_STATUS_HIGH_OFF).700x00RRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109410Reserved for future use.1580x00RLINK_LIST_ELEMENT_FETCH_ERR_DETECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109433Linked List Element Fetch Error Detected. - The DMA read channel has received an error response from the AXI bus while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this clears all bits in this register, and also the DMA Read Error Status High register (DMA_READ_ERR_STATUS_HIGH_OFF).23160x00RRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109440Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_HIGH_OFFDMA_READ_ERR_STATUS_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1095420xB8R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFFDMA Read Error Status High Register.falsefalsefalsefalseUNSUPPORTED_REQPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109468Unsupported Request. The DMA read channel has received a PCIe unsupported request completion status from the remote device in response to the MRd request. For more details, see "Linked List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the same channel in this register and in the DMA Read Error Status Low register.700x00RCPL_ABORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109492Completer Abort. The DMA read channel has received a PCIe completer abort completion status from the remote device in response to the MRd request. For more details, see "Linked List Mode".Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the same channel in this register and in the DMA Read Error Status Low register.1580x00RCPL_TIMEOUTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109515Completion Time Out. The DMA read channel has timed-out while waiting for the remote device to respond to the MRd request, or a malformed CplD has been received. For more details, see "Linked List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling" . - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the same channel in this register and in the DMA Read Error Status Low register.23160x00RDATA_POISIONINGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109541Data Poisoning. The DMA read channel has detected data poisoning in the completion from the remote device (in response to the MRd request).The DMA read channel will drop the completion and then be halted. The CX_FLT_MASK_UR_POIS filter rule does not affect this behavior.Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the same channel in this register and in the DMA Read Error Status Low register.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_LINKED_LIST_ERR_EN_OFFDMA_READ_LINKED_LIST_ERR_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1095990xC4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFFDMA Read Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel "done" interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel "abort" interrupts (local and remote).falsefalsefalsefalseRD_CHANNEL_LLRAIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109565Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Used in linked list mode only.For more details, see "Interrupt Handling".Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 300x0R/W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109573Reserved for future use.1580x00RRD_CHANNEL_LLLAIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109590Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Used in linked list mode only.For more details, see "Interrupt Handling".Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19160x0R/W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109598Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_LOW_OFFDMA_READ_DONE_IMWR_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1096160xCCR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFFDMA Read Done IMWr Address Low Register.falsefalsefalsefalseDMA_READ_DONE_LOW_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109615The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be "00" as this address must be dword aligned.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_HIGH_OFFDMA_READ_DONE_IMWR_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1096320xD0R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFFDMA Read Done IMWr Address High Register.falsefalsefalsefalseDMA_READ_DONE_HIGH_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109631The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_LOW_OFFDMA_READ_ABORT_IMWR_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1096490xD4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFFDMA Read Abort IMWr Address Low Register.falsefalsefalsefalseDMA_READ_ABORT_LOW_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109648The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP. Bits [1:0] must be "00" as this address must be dword aligned.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_HIGH_OFFDMA_READ_ABORT_IMWR_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1096650xD8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFFDMA Read Abort IMWr Address High Register.falsefalsefalsefalseDMA_READ_ABORT_HIGH_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109664The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH01_IMWR_DATA_OFFDMA_READ_CH01_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1096930xDCR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFFDMA Read Channel 1 and 0 IMWr Data Register.falsefalsefalsefalseRD_CHANNEL_0_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109680The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WRD_CHANNEL_1_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109692The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH23_IMWR_DATA_OFFDMA_READ_CH23_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1097210xE0R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFFDMA Read Channel 3 and 2 IMWr Data Register.falsefalsefalsefalseRD_CHANNEL_2_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109708The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 2.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WRD_CHANNEL_3_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109720The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 3.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH45_IMWR_DATA_OFFDMA_READ_CH45_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1097490xE4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFFDMA Read Channel 5 and 4 IMWr Data Register.falsefalsefalsefalseRD_CHANNEL_4_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109736The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 4.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WRD_CHANNEL_5_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109748The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 5.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH67_IMWR_DATA_OFFDMA_READ_CH67_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1097770xE8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFFDMA Read Channel 7 and 6 IMWr Data Register.falsefalsefalsefalseRD_CHANNEL_6_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109764The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 6.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WRD_CHANNEL_7_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109776The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 7.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFDMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1098500x108R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFDMA Write Engine Handshake Counter Channel 0/1/2/3 Register.falsefalsefalsefalseDMA_WRITE_ENGINE_HSHAKE_CNT_CH0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109791DMA handshake counter for DMA Write Engine Channel 0. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.400x00RRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109798Reserved for future use.750x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109808DMA handshake counter for DMA Write Engine Channel 1. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109815Reserved for future use.15130x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109825DMA handshake counter for DMA Write Engine Channel 2. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.20160x00RRSVDP_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109832Reserved for future use.23210x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109842DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.28240x00RRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109849Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFDMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1099230x10CR0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFDMA Write Engine Handshake Counter Channel 4/5/6/7 Register.falsefalsefalsefalseDMA_WRITE_ENGINE_HSHAKE_CNT_CH4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109864DMA handshake counter for DMA Write Engine Channel 4. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.400x00RRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109871Reserved for future use.750x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109881DMA handshake counter for DMA Write Engine Channel 5. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109888Reserved for future use.15130x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109898DMA handshake counter for DMA Write Engine Channel 6. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.20160x00RRSVDP_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109905Reserved for future use.23210x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109915DMA handshake counter for DMA Write Engine Channel 7. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.28240x00RRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109922Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFDMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1099960x118R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFDMA Read Engine Handshake Counter Channel 0/1/2/3 Register.falsefalsefalsefalseDMA_READ_ENGINE_HSHAKE_CNT_CH0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109937DMA handshake counter for DMA Read Engine Channel 0. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.400x00RRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109944Reserved for future use.750x0RDMA_READ_ENGINE_HSHAKE_CNT_CH1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109954DMA handshake counter for DMA Read Engine Channel 1. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109961Reserved for future use.15130x0RDMA_READ_ENGINE_HSHAKE_CNT_CH2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109971DMA handshake counter for DMA Read Engine Channel 2. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.20160x00RRSVDP_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109978Reserved for future use.23210x0RDMA_READ_ENGINE_HSHAKE_CNT_CH3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109988DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.28240x00RRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_usp_4x8.csr109995Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFDMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1100690x11CR0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFDMA Read Engine Handshake Counter Channel 4/5/6/7 Register.falsefalsefalsefalseDMA_READ_ENGINE_HSHAKE_CNT_CH4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110010DMA handshake counter for DMA Read Engine Channel 4. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.400x00RRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110017Reserved for future use.750x0RDMA_READ_ENGINE_HSHAKE_CNT_CH5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110027DMA handshake counter for DMA Read Engine Channel 5. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110034Reserved for future use.15130x0RDMA_READ_ENGINE_HSHAKE_CNT_CH6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110044DMA handshake counter for DMA Read Engine Channel 6. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.20160x00RRSVDP_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110051Reserved for future use.23210x0RDMA_READ_ENGINE_HSHAKE_CNT_CH7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110061DMA handshake counter for DMA Read Engine Channel 7. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.28240x00RRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110068Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_0DMA_CH_CONTROL1_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1103760x200R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0DMA Write Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110089Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110108Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110125Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110146Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110167Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110188Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110200Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110218Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110231Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110243Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110259Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Write Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_WRCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110271Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110293Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110307Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110321Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110335Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110347Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110361Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110375Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_0DMA_CH_CONTROL2_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1104320x204R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0DMA Write Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110392Steering Tag (ST). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110404Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110417Processing Hints (PH). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110431TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_0DMA_TRANSFER_SIZE_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1104630x208R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0DMA Write Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110462DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_0DMA_SAR_LOW_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1104840x20CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0DMA Write SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110483Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Write: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_0DMA_SAR_HIGH_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1105020x210R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0DMA Write SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110501Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_0DMA_DAR_LOW_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1105230x214R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0DMA Write DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110522Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Write: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_0DMA_DAR_HIGH_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1105420x218R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0DMA Write DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110541Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_0DMA_LLP_LOW_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1105640x21CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0DMA Write Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110563Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_0DMA_LLP_HIGH_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1105830x220R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0DMA Write Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110582Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_0DMA_CH_CONTROL1_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1108900x300R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0DMA Read Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110603Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110622Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110639Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110660Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110681Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110702Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Read Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110714Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110732Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110745Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110757Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110773Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Read Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_RDCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110785Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110807Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110821Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110835Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110849Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110861Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110875Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110889Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_0DMA_CH_CONTROL2_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1109460x304R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0DMA Read Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110906Steering Tag (ST). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110918Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110931Processing Hints (PH). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110945TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_0DMA_TRANSFER_SIZE_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1109770x308R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0DMA Read Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110976DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_0DMA_SAR_LOW_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1109980x30CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0DMA Read SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr110997Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Read: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_0DMA_SAR_HIGH_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1110160x310R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0DMA Read SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111015Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_0DMA_DAR_LOW_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1110370x314R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0DMA Read DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111036Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Read: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_0DMA_DAR_HIGH_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1110550x318R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0DMA Read DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111054Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_0DMA_LLP_LOW_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1110770x31CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0DMA Read Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111076Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_0DMA_LLP_HIGH_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1110960x320R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0DMA Read Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111095Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_1DMA_CH_CONTROL1_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1114030x400R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1DMA Write Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111116Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111135Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111152Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111173Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111194Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111215Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111227Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111245Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111258Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111270Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111286Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Write Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_WRCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111298Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111320Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111334Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111348Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111362Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111374Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111388Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111402Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_1DMA_CH_CONTROL2_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1114590x404R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1DMA Write Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111419Steering Tag (ST). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111431Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111444Processing Hints (PH). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111458TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_1DMA_TRANSFER_SIZE_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1114900x408R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1DMA Write Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111489DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_1DMA_SAR_LOW_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1115110x40CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1DMA Write SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111510Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Write: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_1DMA_SAR_HIGH_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1115290x410R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1DMA Write SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111528Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_1DMA_DAR_LOW_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1115500x414R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1DMA Write DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111549Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Write: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_1DMA_DAR_HIGH_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1115690x418R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1DMA Write DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111568Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_1DMA_LLP_LOW_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1115910x41CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1DMA Write Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111590Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_1DMA_LLP_HIGH_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1116100x420R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1DMA Write Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111609Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_1DMA_CH_CONTROL1_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1119170x500R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1DMA Read Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111630Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111649Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111666Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111687Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111708Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111729Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Read Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111741Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111759Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111772Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111784Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111800Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Read Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_RDCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111812Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111834Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111848Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111862Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111876Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111888Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111902Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111916Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_1DMA_CH_CONTROL2_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1119730x504R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1DMA Read Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111933Steering Tag (ST). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111945Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111958Processing Hints (PH). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr111972TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_1DMA_TRANSFER_SIZE_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1120040x508R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1DMA Read Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112003DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_1DMA_SAR_LOW_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1120250x50CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1DMA Read SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112024Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Read: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_1DMA_SAR_HIGH_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1120430x510R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1DMA Read SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112042Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_1DMA_DAR_LOW_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1120640x514R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1DMA Read DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112063Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Read: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_1DMA_DAR_HIGH_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1120820x518R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1DMA Read DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112081Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_1DMA_LLP_LOW_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1121040x51CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1DMA Read Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112103Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_1DMA_LLP_HIGH_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1121230x520R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1DMA Read Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112122Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_2DMA_CH_CONTROL1_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1124300x600R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2DMA Write Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112143Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112162Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112179Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112200Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112221Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112242Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112254Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112272Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112285Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112297Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112313Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Write Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_WRCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112325Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112347Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112361Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112375Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112389Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112401Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112415Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112429Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_2DMA_CH_CONTROL2_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1124860x604R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2DMA Write Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112446Steering Tag (ST). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112458Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112471Processing Hints (PH). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112485TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_2DMA_TRANSFER_SIZE_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1125170x608R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2DMA Write Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112516DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_2DMA_SAR_LOW_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1125380x60CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2DMA Write SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112537Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Write: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_2DMA_SAR_HIGH_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1125560x610R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2DMA Write SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112555Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_2DMA_DAR_LOW_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1125770x614R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2DMA Write DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112576Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Write: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_2DMA_DAR_HIGH_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1125960x618R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2DMA Write DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112595Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_2DMA_LLP_LOW_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1126180x61CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2DMA Write Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112617Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_2DMA_LLP_HIGH_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1126370x620R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2DMA Write Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112636Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_2DMA_CH_CONTROL1_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1129440x700R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2DMA Read Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112657Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112676Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112693Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112714Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112735Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112756Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Read Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112768Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112786Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112799Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112811Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112827Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Read Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_RDCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112839Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112861Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112875Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112889Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112903Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112915Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112929Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112943Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_2DMA_CH_CONTROL2_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1130000x704R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2DMA Read Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112960Steering Tag (ST). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112972Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112985Processing Hints (PH). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr112999TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_2DMA_TRANSFER_SIZE_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1130310x708R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2DMA Read Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113030DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_2DMA_SAR_LOW_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1130520x70CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2DMA Read SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113051Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Read: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_2DMA_SAR_HIGH_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1130700x710R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2DMA Read SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113069Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_2DMA_DAR_LOW_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1130910x714R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2DMA Read DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113090Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Read: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_2DMA_DAR_HIGH_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1131090x718R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2DMA Read DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113108Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_2DMA_LLP_LOW_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1131310x71CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2DMA Read Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113130Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_2DMA_LLP_HIGH_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1131500x720R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2DMA Read Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113149Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_3DMA_CH_CONTROL1_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1134570x800R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3DMA Write Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113170Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113189Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113206Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113227Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113248Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113269Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113281Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113299Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113312Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113324Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113340Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Write Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_WRCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113352Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113374Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113388Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113402Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113416Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113428Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113442Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113456Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_3DMA_CH_CONTROL2_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1135130x804R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3DMA Write Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113473Steering Tag (ST). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113485Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113498Processing Hints (PH). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113512TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_3DMA_TRANSFER_SIZE_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1135440x808R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3DMA Write Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113543DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_3DMA_SAR_LOW_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1135650x80CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3DMA Write SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113564Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Write: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_3DMA_SAR_HIGH_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1135830x810R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3DMA Write SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113582Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_3DMA_DAR_LOW_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1136040x814R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3DMA Write DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113603Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Write: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_3DMA_DAR_HIGH_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1136230x818R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3DMA Write DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113622Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_3DMA_LLP_LOW_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1136450x81CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3DMA Write Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113644Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_3DMA_LLP_HIGH_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1136640x820R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3DMA Write Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113663Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_3DMA_CH_CONTROL1_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1139710x900R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3DMA Read Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113684Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113703Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113720Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113741Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113762Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113783Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Read Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113795Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113813Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113826Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113838Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113854Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Read Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_RDCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113866Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113888Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113902Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113916Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113930Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113942Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113956Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113970Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_3DMA_CH_CONTROL2_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1140270x904R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3DMA Read Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113987Steering Tag (ST). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_usp_4x8.csr113999Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr114012Processing Hints (PH). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr114026TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_3DMA_TRANSFER_SIZE_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1140580x908R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3DMA Read Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_usp_4x8.csr114057DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_3DMA_SAR_LOW_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1140790x90CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3DMA Read SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr114078Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Read: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_3DMA_SAR_HIGH_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1140970x910R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3DMA Read SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr114096Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_3DMA_DAR_LOW_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1141180x914R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3DMA Read DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr114117Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Read: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_3DMA_DAR_HIGH_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1141360x918R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3DMA Read DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr114135Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_3DMA_LLP_LOW_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1141580x91CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3DMA Read Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_SETDWC_pcie_dbi_cpcie_usp_4x8.csr114157Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_3DMA_LLP_HIGH_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_usp_4x8.csr1141770x920R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3DMA Read Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_SETDWC_pcie_dbi_cpcie_usp_4x8.csr114176Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/W
Addressmap Information for 'DWC_pcie_dbi_cpcie_usp_4x8'